diff options
8 files changed, 147 insertions, 11 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H index 41a391c68..80e902e9f 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -204,9 +204,10 @@ HCD_CONST(SGPE_QUAD_SPECIFIC_RING_SRAM_OFF_BYTE, 0x30) HCD_CONST(SGPE_QUAD_SCOM_RESTORE_SRAM_OFF_BYTE, 0x34) HCD_CONST(SGPE_QUAD_SCOM_RESTORE_MEM_OFF_BYTE, 0x38) HCD_CONST(SGPE_QUAD_SCOM_RESTORE_LENGTH_BYTE, 0x3C) -HCD_CONST(SGPE_AUX_DATA_OFFSET_BYTE, 0x40) -HCD_CONST(SGPE_AUX_DATA_LENGTH_BYTE, 0x44) -HCD_CONST(PGPE_AUX_CTRL_BYTE, 0x48) +HCD_CONST(SGPE_AUX_DATA_OFFSET_BYTE, 0x40) +HCD_CONST(SGPE_AUX_DATA_LENGTH_BYTE, 0x44) +HCD_CONST(SGPE_AUX_CTRL_BYTE, 0x48) +HCD_CONST(SGPE_CHTM_MEM_CFG_BYTE, 0x50) HCD_CONST(SGPE_RESET_ADDR_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_SYSTEM_RESET_ADDR_BYTE)) HCD_CONST(SGPE_BUILD_DATE_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_BUILD_DATE_BYTE)) @@ -216,7 +217,8 @@ HCD_CONST(SGPE_STOP_4_TO_2_BIT_POS, 0x80000000) HCD_CONST(SGPE_STOP_5_TO_4_BIT_POS, 0x40000000) HCD_CONST(SGPE_STOP_8_TO_5_BIT_POS, 0x20000000) HCD_CONST(SGPE_STOP_11_TO_8_BIT_POS, 0x10000000) -HCD_CONST(SGPE_CME_INSTRUCTION_TRACE_BIT_POS, 0x08000000) +HCD_CONST(SGPE_ENABLE_CME_TRACE_ARRAY_BIT_POS, 0x08000000) +HCD_CONST(SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS, 0x04000000) HCD_CONST(SGPE_PROC_FAB_ADDR_BAR_MODE_POS, 0x00008000) ///24x7 @@ -358,7 +360,7 @@ HCD_CONST(CME_STOP_4_TO_2_BIT_POS, 0x40000000) HCD_CONST(CME_STOP_5_TO_4_BIT_POS, 0x20000000) HCD_CONST(CME_STOP_8_TO_5_BIT_POS, 0x10000000) HCD_CONST(CME_STOP_11_TO_8_BIT_POS, 0x08000000) -HCD_CONST(CME_QUEUED_SCAN_DISABLE, 0x00000002) +HCD_CONST(CME_QUEUED_SCAN_DISABLE_BIT_POS, 0x00000002) HCD_CONST(CME_SKIP_CORE_POWEROFF_BIT_POS, 0x00000001) /// CME Hcode @@ -385,6 +387,16 @@ HCD_CONST(CME_QUAD_PSTATE_SIZE, HALF_KB) HCD_CONST(CME_REGION_SIZE, (64 * ONE_KB)) +// Debug + +HCD_CONST(CPMR_TRACE_REGION_OFFSET, (512 * ONE_KB)) +HCD_CONST(CME_TRACE_REGION_SIZE, (16 * ONE_KB)) +HCD_CONST(CPMR_TRACE_REGION_SIZE, (CME_TRACE_REGION_SIZE* MAX_CMES_PER_CHIP)) // 192K +HCD_CONST(CPMR_DEBUG_REGION_OFFSET, CPMR_TRACE_REGION_OFFSET + CPMR_TRACE_REGION_SIZE) +HCD_CONST(CPMR_DEBUG_REGION_SIZE, (64 * ONE_KB)) // 192K + 64K = 256K + + + //--------------------------------------------------------------------------------------- /// PPMR Header diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H index adf1b73ed..c5a09b9df 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H @@ -66,6 +66,9 @@ HCD_CONST(HOMER_AUX_BASE_ADDR, (HOMER_QPMR_BASE_ADDR + QPMR_AUX_OFFSET)) HCD_CONST(HOMER_CPMR_BASE_ADDR, (HOMER_BASE_ADDR + (CPMR_HOMER_OFFSET))) HCD_CONST(HOMER_CPMR_HEADER_ADDR, HOMER_CPMR_BASE_ADDR) +HCD_CONST(HOMER_CPMR_TRACE_ADDR, (HOMER_CPMR_BASE_ADDR + CPMR_TRACE_REGION_OFFSET)) +HCD_CONST(HOMER_CPMR_DEBUG_ADDR, (HOMER_CPMR_BASE_ADDR + CPMR_DEBUG_REGION_OFFSET)) + /// PPMR diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 9774a2eda..0d8920436 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -235,6 +235,7 @@ HCD_HDR_UINT32(g_sgpe_aux_offset, 0); HCD_HDR_UINT32(g_sgpe_aux_length, 0); HCD_HDR_UINT32(g_sgpe_aux_control, 0); HCD_HDR_UINT32(g_sgpe_reserve4, 0); +HCD_HDR_UINT64(g_sgpe_chtm_mem_cfg, 0); HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); #ifdef __ASSEMBLER__ .endm diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index 704600c9c..b406dee9c 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -658,9 +658,10 @@ uint32_t copySectionToHomer( uint8_t* i_destPtr, uint8_t* i_srcPtr, uint8_t i_se */ fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) { - uint8_t attrVal = 0; - uint32_t cmeFlag = 0; - uint32_t sgpeFlag = 0; + uint8_t attrVal = 0; + uint64_t chtmVal = 0; + uint32_t cmeFlag = 0; + uint32_t sgpeFlag = 0; pgpe_flags_t pgpeFlags; const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; @@ -729,11 +730,35 @@ fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PRO if( attrVal ) { - sgpeFlag |= SGPE_CME_INSTRUCTION_TRACE_BIT_POS; + sgpeFlag |= SGPE_ENABLE_CME_TRACE_ARRAY_BIT_POS; } FAPI_DBG("CME Instruction Trace Enabled : %s", attrVal ? "TRUE" : "FALSE" ); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CME_CHTM_TRACE_ENABLE, + i_procTgt, + attrVal), + "Error from FAPI_ATTR_GET for attribute ATTR_CME_CHTM_TRACE_ENABLE"); + + if( attrVal ) + { + sgpeFlag |= SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS; + } + + FAPI_DBG("CME CHTM Trace Enabled : %s", attrVal ? "TRUE" : "FALSE" ); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CME_CHTM_TRACE_MEMORY_CONFIG, + i_procTgt, + chtmVal), + "Error from FAPI_ATTR_GET for attribute ATTR_CME_CHTM_TRACE_MEMORY_CONFIG" ); + + if( chtmVal ) + { + pSgpeHdr->g_sgpe_chtm_mem_cfg = SWIZZLE_8_BYTE(chtmVal); + } + + FAPI_DBG("CME CHTM Memory Config : %016llx", chtmVal); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_DISABLE_QUEUED_SCAN, FAPI_SYSTEM, attrVal), @@ -741,7 +766,7 @@ fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PRO if( attrVal ) { - cmeFlag |= CME_QUEUED_SCAN_DISABLE; + cmeFlag |= CME_QUEUED_SCAN_DISABLE_BIT_POS; } FAPI_DBG("QUEUED_SCAN_DISABLE : %s", attrVal ? "TRUE" : "FALSE" ); @@ -769,6 +794,7 @@ fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PRO FAPI_INF("CME Flag Value : 0x%08x", SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags)); FAPI_INF("SGPE Flag Value : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags)); + FAPI_INF("SGPE Chtm Config : 0x%016llx", SWIZZLE_8_BYTE(pSgpeHdr->g_sgpe_chtm_mem_cfg)); FAPI_INF("PGPE Flag Value : 0x%08x", SWIZZLE_2_BYTE(pPgpeHdr->g_pgpe_flags)); FAPI_DBG(" -------------------- CME/SGPE Flags Ends ---------------=="); diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml index cc87473b4..eb6ad0379 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml @@ -1604,6 +1604,44 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_CME_CHTM_TRACE_ENABLE</id> + <description> + Enables the SGPE Hcode to enable the CME instruction traces into the CHTM + for debug. Note: all configured CMEs will be put into this + mode if this attribute is ON. + + Consumer: p9_hcode_image_build.c -> + SGPE Header field + + Platform default: OFF + </description> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <valueType>uint8</valueType> + <enum> + OFF = 0x00, ON = 0x01 + </enum> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CME_CHTM_TRACE_MEMORY_CONFIG</id> + <description> + CHTM Trace Memory Configuration value goes directly into CHTM_MEM register. + User is responsible to put correct data for each bit field of the register. + + Consumer: p9_hcode_image_build.c -> + SGPE Header field + + Platform default: 0 + </description> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <valueType>uint64</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_PGPE_HCODE_FUNCTION_ENABLE</id> <description> Enables the PGPE Hcode to physically perform frequency and voltage operations diff --git a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml index 7a81d8be3..46ac410d2 100644 --- a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml +++ b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml @@ -169,6 +169,16 @@ <default>0x01</default> </attribute> + <attribute> + <id>ATTR_CME_CHTM_TRACE_ENABLE</id> + <default>0x00</default> + </attribute> + <attribute> + <id>ATTR_CME_CHTM_TRACE_MEMORY_CONFIG</id> + <default>0x00</default> + </attribute> + + <!-- ===================================================================== End of temporary definitions ================================================================= --> diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index a96d3c590..a3a5a80d8 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -33643,4 +33643,49 @@ Measured in GB</description> </hwpfToHbAttrMap> </attribute> +<attribute> + <id>CME_CHTM_TRACE_ENABLE</id> + <description> + Enables the SGPE Hcode to enable the CME instruction traces into the CHTM + for debug. Note: all configured CMEs will be put into this + mode if this attribute is ON. + + Consumer: p9_hcode_image_build.c -> + SGPE Header field + + Platform default: OFF + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_CME_CHTM_TRACE_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>CME_CHTM_TRACE_MEMORY_CONFIG</id> + <description> + CHTM Trace Memory Configuration value goes directly into CHTM_MEM register. + User is responsible to put correct data for each bit field of the register. + + Consumer: p9_hcode_image_build.c -> + SGPE Header field + + Platform default: 0 + </description> + <simpleType> + <uint64_t></uint64_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_CME_CHTM_TRACE_MEMORY_CONFIG</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + </attributes> diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 7efa71ffb..438021e40 100755 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -1330,7 +1330,8 @@ <attribute><id>DO_MSS_TRAINING_BAD_BITS</id></attribute> <!-- END memory workaround for DD1.02 --> <attribute><id>DO_BLUE_WATERFALL_ADJUST</id></attribute> - + <attribute><id>CME_CHTM_TRACE_ENABLE</id></attribute> + <attribute><id>CME_CHTM_TRACE_MEMORY_CONFIG</id></attribute> </targetType><!-- chip-processor-power9 --> <!-- chip-processor-nimbus --> |
