diff options
4 files changed, 89 insertions, 7 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C index b35c5084f..869e18f25 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -70,7 +70,6 @@ namespace mss namespace nvdimm { - /// /// @brief Wrapper to read MAINT_ADDR_MODE_EN /// Specialization for TARGET_TYPE_MCA @@ -593,6 +592,7 @@ template<> fapi2::ReturnCode post_restore_transition( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) { mss::states l_maint_addr_enabled = mss::states::LOW; + mss::states l_refresh_overrun_mask = mss::states::OFF; const bool NVDIMM_WORKAROUND = true; FAPI_TRY(get_maint_addr_mode_en(i_target, l_maint_addr_enabled)); @@ -604,6 +604,10 @@ fapi2::ReturnCode post_restore_transition( const fapi2::Target<fapi2::TARGET_TYP FAPI_TRY(change_maint_addr_mode_en(i_target, mss::states::LOW)); } + // Save the current mask value and mask the refresh overrun error + FAPI_TRY(get_refresh_overrun_mask(i_target, l_refresh_overrun_mask)); + FAPI_TRY(change_refresh_overrun_mask(i_target, mss::states::ON)); + // Restore the rcd FAPI_TRY( rcd_restore( i_target ) ); @@ -619,9 +623,13 @@ fapi2::ReturnCode post_restore_transition( const fapi2::Target<fapi2::TARGET_TYP // Latch in the rank averaged vref value FAPI_TRY(wr_vref_latch(i_target)); - //Restore main_addr_mode_en to previous setting + // Restore main_addr_mode_en to previous setting FAPI_TRY(change_maint_addr_mode_en(i_target, l_maint_addr_enabled)); + // Restore the refresh overrun mask to previous and clear the fir + FAPI_TRY(clear_refresh_overrun_fir(i_target)); + FAPI_TRY(change_refresh_overrun_mask(i_target, l_refresh_overrun_mask)); + fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H index 5df44c13c..a3c4914a4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,12 +38,79 @@ #include <lib/shared/mss_const.H> #include <lib/ccs/ccs.H> #include <lib/phy/dp16.H> +#include <lib/mc/port.H> namespace mss { namespace nvdimm { +/// +/// @brief get refresh overrun fir mask +/// @param[in] i_target the target associated with this subroutine +/// @param[out] i_state the state to change to +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +inline fapi2::ReturnCode get_refresh_overrun_mask( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + mss::states& o_state ) +{ + typedef portTraits<mss::mc_type::NIMBUS> TT; + fapi2::buffer<uint64_t> l_data; + + FAPI_TRY( mss::getScom(i_target, TT::CALFIRMASK, l_data), + "%s Failed getScom", mss::c_str(i_target) ); + + o_state = l_data.getBit<TT::CALFIRMASK_REFRESH_OVERRUN>() ? mss::states::ON : mss::states::OFF; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief change refresh overrun fir mask +/// @param[in] i_target the target associated with this subroutine +/// @param[in] i_state the state to change to +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +inline fapi2::ReturnCode change_refresh_overrun_mask( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + const mss::states i_state ) +{ + typedef portTraits<mss::mc_type::NIMBUS> TT; + fapi2::buffer<uint64_t> l_data; + + FAPI_TRY( mss::getScom(i_target, TT::CALFIRMASK, l_data), + "%s Failed getScom", mss::c_str(i_target) ); + + l_data.writeBit<TT::CALFIRMASK_REFRESH_OVERRUN>(i_state); + + FAPI_TRY( mss::putScom(i_target, TT::CALFIRMASK, l_data), + "%s Failed putScom", mss::c_str(i_target) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Clear the refresh overrun fir +/// @param[in] i_target the target associated with this subroutine +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +inline fapi2::ReturnCode clear_refresh_overrun_fir( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) +{ + typedef portTraits<mss::mc_type::NIMBUS> TT; + fapi2::buffer<uint64_t> l_data; + + FAPI_TRY( mss::getScom(i_target, TT::CALFIRQ, l_data), + "%s Failed getScom", mss::c_str(i_target) ); + + l_data.clearBit<TT::CALFIRQ_REFRESH_OVERRUN>(); + + FAPI_TRY( mss::putScom(i_target, TT::CALFIRQ, l_data), + "%s Failed putScom", mss::c_str(i_target) ); + +fapi_try_exit: + return fapi2::current_err; +} /// /// @brief Wrapper to read MAINT_ADDR_MODE_EN diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H index 252ebc5a9..45ffbee13 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H @@ -85,6 +85,8 @@ class portTraits<mss::mc_type::NIMBUS> static constexpr uint64_t CAL3Q_REG = MCA_MBA_CAL3Q; static constexpr uint64_t DSM0Q_REG = MCA_MBA_DSM0Q; static constexpr uint64_t FWMS_REG = MCA_FWMS0; + static constexpr uint64_t CALFIRQ = MCA_MBACALFIRQ; + static constexpr uint64_t CALFIRMASK = MCA_MBACALFIR_MASK; // Danger Will Robinson <wave robot arms> MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0 uses PHY rank ordinal numbers // which are different between PHYs. So if you're playing with this register, be sure to map rank numbers. @@ -238,6 +240,9 @@ class portTraits<mss::mc_type::NIMBUS> CAL3Q_ALL_PERIODIC_LENGTH_LEN = MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_LENGTH_LEN, CAL3Q_FREEZE_ON_PARITY_ERROR_DIS = MCA_MBA_CAL3Q_CFG_FREEZE_ON_PARITY_ERROR_DIS, + CALFIRQ_REFRESH_OVERRUN = MCA_MBACALFIRQ_REFRESH_OVERRUN, + CALFIRMASK_REFRESH_OVERRUN = MCA_MBACALFIR_MASK_REFRESH_OVERRUN, + RECR_ENABLE_UE_NOISE_WINDOW = MCA_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW, RECR_TCE_CORRECTION = MCA_RECR_MBSECCQ_ENABLE_TCE_CORRECTION, RECR_READ_POINTER_DLY = MCA_RECR_MBSECCQ_READ_POINTER_DELAY, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C index 13c3cffae..f6a8b3467 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C @@ -241,6 +241,11 @@ fapi2::ReturnCode execute_inst_array(const fapi2::Target<fapi2::TARGET_TYPE_MCBI FAPI_TRY(mss::ccs::start_stop(i_target, mss::START), "%s Error in execute_inst_array", mss::c_str(i_port) ); + // ccs_add_mux_sel back to low. Per Shelton, it is okay to change the mux while ccs is running + // when doing single port execute. ccs will remain in control until the end of the program then + // mainline takes over + FAPI_TRY(mss::change_addr_mux_sel(i_port, mss::LOW)); + mss::poll(i_target, TT::STATQ_REG, i_program.iv_poll, [&status](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool { @@ -250,9 +255,6 @@ fapi2::ReturnCode execute_inst_array(const fapi2::Target<fapi2::TARGET_TYPE_MCBI }, i_program.iv_probes); - // ccs_add_mux_sel back to low to give control back to mainline - FAPI_TRY(mss::change_addr_mux_sel(i_port, mss::LOW)); - // Check for done and success. DONE being the only bit set. if (status == STAT_QUERY_SUCCESS) { |
