diff options
13 files changed, 373 insertions, 24 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.H index e33973ba5..5131f43b2 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.H @@ -28,11 +28,12 @@ // *HWP Level: 1 // *HWP Consumed by: FSP:HB -#include <fapi2.H> +#ifndef __P9_MSS_ATTR_UPDATE__ +#define __P9_MSS_ATTR_UPDATE__ -using fapi2::TARGET_TYPE_MCS; +#include <fapi2.H> -typedef fapi2::ReturnCode (*p9_mss_attr_update_FP_t) (const fapi2::Target<TARGET_TYPE_MCS>&); +typedef fapi2::ReturnCode (*p9_mss_attr_update_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCS>&); extern "C" { @@ -42,7 +43,8 @@ extern "C" /// @param[in] i_target, the controller (e.g., MCS) /// @return FAPI2_RC_SUCCESS iff ok /// - fapi2::ReturnCode p9_mss_attr_update( const fapi2::Target<TARGET_TYPE_MCS>& i_target ); + fapi2::ReturnCode p9_mss_attr_update( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target ); } +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.H new file mode 100644 index 000000000..b10f472c6 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.H @@ -0,0 +1,50 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9_mss_ddr_phy_reset.H +/// @brief Perform reset of the DDR PHY +/// +// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB + +#ifndef __P9_MSS_DDR_PHY_RESET__ +#define __P9_MSS_DDR_PHY_RESET__ + +#include <fapi2.H> + +typedef fapi2::ReturnCode (*p9_mss_ddr_phy_reset_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>&); + +extern "C" +{ + +/// +/// @brief Reset the DDR PHY +/// @param[in] i_target, the McBIST of the ports of the dram you're training +/// @return FAPI2_RC_SUCCESS iff ok +/// + fapi2::ReturnCode p9_mss_ddr_phy_reset( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); +} + +#endif + diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.H new file mode 100644 index 000000000..5edf9ec5b --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.H @@ -0,0 +1,50 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/memory/p9_mss_draminit.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9_mss_draminit.H +/// @brief Reset and initialze DRAM +/// +// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB + +#ifndef __P9_MSS_DRAMINIT__ +#define __P9_MSS_DRAMINIT__ + +#include <fapi2.H> + +typedef fapi2::ReturnCode (*p9_mss_draminit_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>&); + +extern "C" +{ + +/// +/// @brief Initialize dram +/// @param[in] i_target, the McBIST of the ports of the dram you're training +/// @return FAPI2_RC_SUCCESS iff ok +/// + fapi2::ReturnCode p9_mss_draminit( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); +} + +#endif + diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H new file mode 100644 index 000000000..f32c74796 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H @@ -0,0 +1,47 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// @file p9_mss_draminit_mc.H +/// @brief Initialize the memory controller to take over the DRAM +/// +// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB + +#ifndef __P9_MSS_DRAMINIT_MC__ +#define __P9_MSS_DRAMINIT_MC__ + +#include <fapi2.H> + +typedef fapi2::ReturnCode (*p9_mss_draminit_mc_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>&); + +extern "C" +{ +/// +/// @brief Initialize the MC now that DRAM is up +/// @param[in] i_target, the McBIST of the ports of the dram you're training +/// @return FAPI2_RC_SUCCESS iff ok +/// + fapi2::ReturnCode p9_mss_draminit_mc( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.H new file mode 100644 index 000000000..4594a8df5 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.H @@ -0,0 +1,47 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/memory/p9_mss_draminit_training.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// @file p9_mss_draminit_training.H +/// @brief Train DRAM +/// +// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB + +#ifndef __P9_MSS_DRAMINIT_TRAINING__ +#define __P9_MSS_DRAMINIT_TRAINING__ + +#include <fapi2.H> + +typedef fapi2::ReturnCode (*p9_mss_draminit_training_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>&); + +extern "C" +{ +/// +/// @brief Train dram +/// @param[in] i_target, the McBIST of the ports of the dram you're training +/// @return FAPI2_RC_SUCCESS iff ok +/// + fapi2::ReturnCode p9_mss_draminit_training( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.H index 24d52c73e..c3bc819ce 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.H @@ -28,11 +28,12 @@ // *HWP Level: 1 // *HWP Consumed by: FSP:HB -#include <fapi2.H> +#ifndef __P9_MSS_EFF_CONFIG__ +#define __P9_MSS_EFF_CONFIG__ -using fapi2::TARGET_TYPE_MCS; +#include <fapi2.H> -typedef fapi2::ReturnCode (*p9_mss_eff_config_FP_t) (const fapi2::Target<TARGET_TYPE_MCS>&); +typedef fapi2::ReturnCode (*p9_mss_eff_config_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCS>&); extern "C" { @@ -42,7 +43,8 @@ extern "C" /// @param[in] i_target, the controller (e.g., MCS) /// @return FAPI2_RC_SUCCESS iff ok /// - fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<TARGET_TYPE_MCS>& i_target ); + fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target ); } +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.H index 9e1c7373a..cb28e681e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.H @@ -28,11 +28,12 @@ // *HWP Level: 1 // *HWP Consumed by: FSP:HB -#include <fapi2.H> +#ifndef __P9_MSS_EFF_CONFIG_THERMAL__ +#define __P9_MSS_EFF_CONFIG_THERMAL__ -using fapi2::TARGET_TYPE_MCS; +#include <fapi2.H> -typedef fapi2::ReturnCode (*p9_mss_eff_config_thermal_FP_t) (const fapi2::Target<TARGET_TYPE_MCS>&); +typedef fapi2::ReturnCode (*p9_mss_eff_config_thermal_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCS>&); extern "C" { @@ -42,7 +43,9 @@ extern "C" /// @param[in] i_target, the controller (e.g., MCS) /// @return FAPI2_RC_SUCCESS iff ok /// - fapi2::ReturnCode p9_mss_eff_config_thermal( const fapi2::Target<TARGET_TYPE_MCS>& i_target ); + fapi2::ReturnCode p9_mss_eff_config_thermal( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target ); } +#endif + diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H index 352dff54b..d95e0c170 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H @@ -28,11 +28,12 @@ // *HWP Level: 1 // *HWP Consumed by: FSP:HB -#include <fapi2.H> +#ifndef __P9_MSS_FREQ__ +#define __P9_MSS_FREQ__ -using fapi2::TARGET_TYPE_MCS; +#include <fapi2.H> -typedef fapi2::ReturnCode (*p9_mss_freq_FP_t) (const fapi2::Target<TARGET_TYPE_MCS>&); +typedef fapi2::ReturnCode (*p9_mss_freq_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCS>&); extern "C" { @@ -42,7 +43,8 @@ extern "C" /// @param[in] i_target, the controller (e.g., MCS) /// @return FAPI2_RC_SUCCESS iff ok /// - fapi2::ReturnCode p9_mss_freq( const fapi2::Target<TARGET_TYPE_MCS>& i_target ); + fapi2::ReturnCode p9_mss_freq( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target ); } +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_memdiag.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_memdiag.H new file mode 100644 index 000000000..d64913495 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_memdiag.H @@ -0,0 +1,47 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/memory/p9_mss_memdiag.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// @file p9_mss_memdiag.H +/// @brief Mainstore pattern testing +/// +// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB + +#ifndef __P9_MSS_MEMDIAG__ +#define __P9_MSS_MEMDIAG__ + +#include <fapi2.H> + +typedef fapi2::ReturnCode (*p9_mss_memdiag_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>&); + +extern "C" +{ +/// +/// @brief Pattern test the DRAM +/// @param[in] i_target, the McBIST of the ports of the dram you're training +/// @return FAPI2_RC_SUCCESS iff ok +/// + fapi2::ReturnCode p9_mss_memdiag( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_power_cleanup.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_power_cleanup.H new file mode 100644 index 000000000..94f932b77 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_power_cleanup.H @@ -0,0 +1,47 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/memory/p9_mss_power_cleanup.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// @file p9_mss_powercleanup.H +/// @brief Perform any necessary power cleanup +/// +// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB + +#ifndef __P9_MSS_POWERCLEAN__ +#define __P9_MSS_POWERCLEAN__ + +#include <fapi2.H> + +typedef fapi2::ReturnCode (*p9_mss_power_cleanup_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>&); + +extern "C" +{ +/// +/// @brief Perform any necessary power cleanup +/// @param[in] i_target, the McBIST of the ports of the dram you're training +/// @return FAPI2_RC_SUCCESS iff ok +/// + fapi2::ReturnCode p9_mss_power_cleanup( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.H index 2ff814714..b59076254 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.H @@ -28,11 +28,12 @@ // *HWP Level: 1 // *HWP Consumed by: FSP:HB -#include <fapi2.H> +#ifndef __P9_MSS_SCOMINIT__ +#define __P9_MSS_SCOMINIT__ -using fapi2::TARGET_TYPE_MBIST; +#include <fapi2.H> -typedef fapi2::ReturnCode (*p9_mss_scominit_FP_t) (const fapi2::Target<TARGET_TYPE_MCBIST>&); +typedef fapi2::ReturnCode (*p9_mss_scominit_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>&); extern "C" { @@ -42,7 +43,9 @@ extern "C" /// @param[in] i_target, the MCBIST /// @return FAPI2_RC_SUCCESS iff ok /// - fapi2::ReturnCode p9_mss_scominit( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ); + fapi2::ReturnCode p9_mss_scominit( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); } +#endif + diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H new file mode 100644 index 000000000..0969db97c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H @@ -0,0 +1,47 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// @file p9_mss_thermal_init.H +/// @brief Initialize thermal sensors +/// +// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB + +#ifndef __P9_MSS_THERMAL_INIT__ +#define __P9_MSS_THERMAL_INIT__ + +#include <fapi2.H> + +typedef fapi2::ReturnCode (*p9_mss_thermal_init_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>&); + +extern "C" +{ +/// +/// @brief Initialize thermal sensors +/// @param[in] i_target, the McBIST of the ports of the dram you're training +/// @return FAPI2_RC_SUCCESS iff ok +/// + fapi2::ReturnCode p9_mss_thermal_init( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.H index fc2b625db..f578495a5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.H @@ -28,11 +28,12 @@ // *HWP Level: 1 // *HWP Consumed by: FSP:HB -#include <fapi2.H> +#ifndef __P9_MSS_VOLT__ +#define __P9_MSS_VOLT__ -using fapi2::TARGET_TYPE_MCS; +#include <fapi2.H> -typedef fapi2::ReturnCode (*p9_mss_volt_FP_t) (const fapi2::Target<TARGET_TYPE_MCS>&); +typedef fapi2::ReturnCode (*p9_mss_volt_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCS>&); extern "C" { @@ -42,7 +43,8 @@ extern "C" /// @param[in] i_target, the controller (e.g., MCS) /// @return FAPI2_RC_SUCCESS iff ok /// - fapi2::ReturnCode p9_mss_volt( const fapi2::Target<TARGET_TYPE_MCS>& i_target ); + fapi2::ReturnCode p9_mss_volt( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target ); } +#endif |
