diff options
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C | 12 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H | 23 |
2 files changed, 29 insertions, 6 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C index f06a7cc9f..7614ac044 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C @@ -73,15 +73,17 @@ fapi2::ReturnCode rcd_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target { FS0, 3, eff_dimm_ddr4_rc03, mss::tmrd_l() }, { FS0, 4, eff_dimm_ddr4_rc04, mss::tmrd_l() }, { FS0, 5, eff_dimm_ddr4_rc05, mss::tmrd_l() }, - { FS0, 6, eff_dimm_ddr4_rc06_07, mss::tmrd() }, + // Note: the tMRC1 timing as it is larger for saftey's sake + // The concern is that if geardown mode is ever required in the future, we would need the longer timing + { FS0, 6, eff_dimm_ddr4_rc06_07, mss::tmrc1() }, { FS0, 8, eff_dimm_ddr4_rc08, mss::tmrd() }, { FS0, 9, eff_dimm_ddr4_rc09, mss::tmrd() }, { FS0, 10, eff_dimm_ddr4_rc0a, tSTAB }, - { FS0, 11, eff_dimm_ddr4_rc0b, mss::tmrd() }, + { FS0, 11, eff_dimm_ddr4_rc0b, mss::tmrd_l() }, { FS0, 12, eff_dimm_ddr4_rc0c, mss::tmrd() }, - { FS0, 13, eff_dimm_ddr4_rc0d, mss::tmrd() }, + { FS0, 13, eff_dimm_ddr4_rc0d, mss::tmrd_l2() }, { FS0, 14, eff_dimm_ddr4_rc0e, mss::tmrd() }, - { FS0, 15, eff_dimm_ddr4_rc0f, mss::tmrd() }, + { FS0, 15, eff_dimm_ddr4_rc0f, mss::tmrd_l2() }, }; // RCD 8-bit data - integral represents rc# @@ -93,7 +95,7 @@ fapi2::ReturnCode rcd_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target { FS0, 4, eff_dimm_ddr4_rc_4x, mss::tmrd() }, { FS0, 5, eff_dimm_ddr4_rc_5x, mss::tmrd() }, { FS0, 6, eff_dimm_ddr4_rc_6x, mss::tmrd() }, - { FS0, 7, eff_dimm_ddr4_rc_7x, mss::tmrd() }, + { FS0, 7, eff_dimm_ddr4_rc_7x, mss::tmrd_l() }, { FS0, 8, eff_dimm_ddr4_rc_8x, mss::tmrd() }, { FS0, 9, eff_dimm_ddr4_rc_9x, mss::tmrd() }, { FS0, 10, eff_dimm_ddr4_rc_ax, mss::tmrd() }, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H index cdecb3ff3..bfce9ee75 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H @@ -223,7 +223,7 @@ fapi_try_exit: /// @tparam OT the output type, derrived from the parameters /// @param[in] timing_in_ps timing parameter in ps /// @param[out] o_value_nck the end calculation in nck -/// @return the clock cycles of timing parameter (provided in ps) +/// @return the clock cycles of timing parameter (provided in ps)F /// @note Uses DDR4 SPD Contents Rounding Algorithm /// @note Item 2220.46 /// @@ -323,6 +323,27 @@ constexpr uint64_t tmrd_l() } /// +/// @brief Control word to control word delay for L2 (using F0RC0D or F0RC0F) +/// @return constexpr value of 32 clocks +/// +constexpr uint64_t tmrd_l2() +{ + // Per DDR4RCD02 Spec Rev 0.85 + return 32; +} + +/// +/// @brief Control word F0RC06 with or without geardown mode +/// @note using the geardown mode which is longer for saftey +/// @return constexpr value of 32 clocks +/// +constexpr uint64_t tmrc1() +{ + // Per DDR4RCD02 Spec Rev 0.85 + return 32; +} + +/// /// @brief Stabilization time /// @return constexpr value of 5 us /// |
