diff options
| -rwxr-xr-x | src/include/usr/hwpf/plat/fapiPlatAttributeService.H | 4 | ||||
| -rwxr-xr-x | src/usr/hwpf/hwp/fapiTestHwpAttr.C | 37 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/memory_attributes.xml | 1231 | ||||
| -rw-r--r-- | src/usr/hwpf/makefile | 3 | ||||
| -rw-r--r-- | src/usr/pnor/pnorrp.C | 4 | ||||
| -rw-r--r-- | src/usr/pnor/test/pnorrptest.H | 2 | ||||
| -rw-r--r-- | src/usr/targeting/attrrp.C | 6 | ||||
| -rw-r--r-- | src/usr/targeting/target.C | 1 | ||||
| -rw-r--r-- | src/usr/targeting/xmltohb/attribute_types.xml | 1538 | ||||
| -rw-r--r-- | src/usr/targeting/xmltohb/makefile | 22 | ||||
| -rwxr-xr-x | src/usr/targeting/xmltohb/mergexml.sh | 2 | ||||
| -rw-r--r-- | src/usr/targeting/xmltohb/target_types.xml | 88 | ||||
| -rwxr-xr-x | src/usr/targeting/xmltohb/xmltohb.pl | 27 |
13 files changed, 2904 insertions, 61 deletions
diff --git a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H index e932bca6d..ebbec599d 100755 --- a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H +++ b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H @@ -102,7 +102,7 @@ namespace platAttrSvc * attribute to the equivalent host boot request */ #define FAPI_PLAT_ATTR_SVC_GETMACRO_DIRECT(ID, PTARGET, VAL) \ - ( ((PTARGET) ? \ + ( ((PTARGET > 0) ? \ static_cast<TARGETING::Target*>( \ static_cast<const fapi::Target*>(PTARGET)->get()) \ : fapi::platAttrSvc::getSystemTarget())->tryGetAttr< \ @@ -114,7 +114,7 @@ namespace platAttrSvc * attribute to the equivalent host boot request */ #define FAPI_PLAT_ATTR_SVC_SETMACRO_DIRECT(ID, PTARGET, VAL) \ - ( ((PTARGET) ? \ + ( ((PTARGET > 0) ? \ static_cast<TARGETING::Target*>( \ static_cast<const fapi::Target*>(PTARGET)->get()) \ : fapi::platAttrSvc::getSystemTarget())->trySetAttr< \ diff --git a/src/usr/hwpf/hwp/fapiTestHwpAttr.C b/src/usr/hwpf/hwp/fapiTestHwpAttr.C index 0f58479c5..21a9a7356 100755 --- a/src/usr/hwpf/hwp/fapiTestHwpAttr.C +++ b/src/usr/hwpf/hwp/fapiTestHwpAttr.C @@ -45,6 +45,9 @@ */ #include <fapiTestHwpAttr.H> +#include <targeting/targetservice.H> +#include <targeting/predicates/predicatectm.H> +#include <targeting/iterators/rangefilter.H> extern "C" { @@ -55,13 +58,43 @@ extern "C" fapi::ReturnCode hwpTestAttributes() { FAPI_INF("hwpTestAttributes: Start HWP"); - - // Attempt to call the attribute get/set macros for the scratch attributes fapi::ReturnCode l_rc; do { //---------------------------------------------------------------------- + // Test ATTR_MSS_DIMM_MFG_ID_CODE + //---------------------------------------------------------------------- + { + uint32_t l_data[2][2]; + + TARGETING::PredicateCTM l_pred(TARGETING::CLASS_UNIT, TARGETING::TYPE_MBA); + TARGETING::TargetRangeFilter l_filter(TARGETING::targetService().begin(), + TARGETING::targetService().end(), + &l_pred); + + // Just look at the first MBA chiplet + if (l_filter) + { + fapi::Target l_target(fapi::TARGET_TYPE_MBA_CHIPLET, *l_filter); + + l_rc = FAPI_ATTR_GET(ATTR_MSS_DIMM_MFG_ID_CODE, &l_target, l_data); + + if (l_rc) + { + FAPI_ERR("hwpTestAttributes: ATTR_MSS_DIMM_MFG_ID_CODE. Error from GET"); + break; + } + } + else + { + FAPI_ERR("hwpTestAttributes: ATTR_MSS_DIMM_MFG_ID_CODE. No MBAs found"); + FAPI_SET_HWP_ERROR(l_rc, RC_HWP_ATTR_UNIT_TEST_FAIL); + break; + } + } + + //---------------------------------------------------------------------- // Test ATTR_SCRATCH_UINT8_1 //---------------------------------------------------------------------- { diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml new file mode 100644 index 000000000..28f10755b --- /dev/null +++ b/src/usr/hwpf/hwp/memory_attributes.xml @@ -0,0 +1,1231 @@ +<!-- IBM_PROLOG_BEGIN_TAG + This is an automatically generated prolog. + + $Source: src/usr/hwpf/hwp/memory_attributes.xml $ + + IBM CONFIDENTIAL + + COPYRIGHT International Business Machines Corp. 2012 + + p1 + + Object Code Only (OCO) source materials + Licensed Internal Code Source Materials + IBM HostBoot Licensed Internal Code + + The source code for this program is not published or other- + wise divested of its trade secrets, irrespective of what has + been deposited with the U.S. Copyright Office. + + Origin: 30 + + IBM_PROLOG_END --> +<attributes> + +<attribute> + <id>ATTR_MSS_VOLT</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>DRAM Voltage, each voltage rail would need to have a value. Computed in mss_volt C code - in millivolts +creator: mss_volt +consumer: mss_eff_cnfg, others +firmware notes: none</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MSS_FREQ</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Frequency of this memory channel in MHz, comprising of three DIMMs. Computed in mss_freq +creator: mss_freq +consumer: mss_eff_cnfg, others +firmware notes: none</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_DIMM_MFG_ID_CODE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Manufacturer ID Code RCD: bits(31:16), Module: bits(15:0)</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_RANKS_CONFIGED</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Bit wise representation of master ranks in each DIMM that are used for reads and writes. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_EFF_NUM_RANKS_PER_DIMM</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Number of ranks in each DIMM. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_TYPE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Type of DIMM: CDIMM, RDIMM, UDIMM, LRDIMM. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_WIDTH</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DRAM Device Width: X4, X8, X16, X32. Used in various locations and is computed in mss_eff_cnfg. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>X4 = 0, X8 = 1, X16 = 2, X32 = 3, </enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_GEN</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Generation of memory: DDR3, DDR4. Used in various locations and is computed in mss_eff_cnfg. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>EMPTY = 0, DDR3 = 1, DDR4 = 2,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_PRIMARY_RANK_GROUP0</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_PRIMARY_RANK_GROUP1</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_PRIMARY_RANK_GROUP2</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_PRIMARY_RANK_GROUP3</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_SECONDARY_RANK_GROUP0</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_SECONDARY_RANK_GROUP1</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_SECONDARY_RANK_GROUP2</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_SECONDARY_RANK_GROUP3</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_TERTIARY_RANK_GROUP0</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_TERTIARY_RANK_GROUP1</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_TERTIARY_RANK_GROUP2</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_TERTIARY_RANK_GROUP3</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_QUATERNARY_RANK_GROUP0</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_QUATERNARY_RANK_GROUP1</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_QUATERNARY_RANK_GROUP2</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_QUATERNARY_RANK_GROUP3</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_rank_group +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>INVALID = 255,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_ODT_RD</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Read ODT. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_termination +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2 4</array> +</attribute> + +<attribute> + <id>ATTR_EFF_ODT_WR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Write ODT. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_termination +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2 4</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_RON</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DRAM Ron. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_termination +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>OHM34 = 34, OHM40 = 40,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_RTT_NOM</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DRAM Rtt_Nom. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_termination +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>DISABLED = 0, OHM20 = 20, OHM30 = 30, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2 4</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_RTT_WR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DRAM Rtt_WR. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_termination +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>DISABLED = 0, OHM60 = 60, OHM120 = 120,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2 4</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_WR_VREF</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DRAM Write Vref. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_termination +consumer: various +firmware notes: none</description> + <valueType>uint32</valueType> + <enum>VDD420 = 420, VDD425 = 425, VDD430 = 430, VDD435 = 435, VDD440 = 440, VDD445 = 445, VDD450 = 450, VDD455 = 455, VDD460 = 460, VDD465 = 465, VDD470 = 470, VDD475 = 475, VDD480 = 480, VDD485 = 485, VDD490 = 490, VDD495 = 495, VDD500 = 500, VDD505 = 505, VDD510 = 510, VDD515 = 515, VDD520 = 520, VDD525 = 525, VDD530 = 530, VDD535 = 535, VDD540 = 540, VDD545 = 545, VDD550 = 550, VDD555 = 555, VDD560 = 560, VDD565 = 565, VDD570 = 570, VDD575 = 575</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_CEN_DRV_IMP_DQ_DQS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Centaur DQ and DQS Drive Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_termination +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>OHM24 = 24, OHM30 = 30, OHM34 = 34, OHM40 = 40,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_CEN_DRV_IMP_CMD</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Centaur Command Drive Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_termination +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_CEN_DRV_IMP_CNTL</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Centaur Control Drive Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_termination +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_CEN_RCV_IMP_DQ_DQS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Centaur DQ and DQS Receiver Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_termination +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM120 = 120,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_CEN_SLEW_RATE_DQ</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Centaur DQ Slew Rate Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_termination +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>SLOW = 0x00, FAST = 0x01,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_CEN_SLEW_RATE_DQS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Centaur DQS Slew Rate Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_termination +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>SLOW = 0x00, FAST = 0x01,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_CEN_SLEW_RATE_CMD</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Centaur Command Slew Rate Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_termination +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>SLOW = 0x00, FAST = 0x01,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_CEN_SLEW_RATE_CNTL</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Centaur Control Slew Rate Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_termination +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>SLOW = 0x00, FAST = 0x01,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_CEN_RD_VREF</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Centaur Read Vref. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: mss_eff_cnfg_termination +consumer: various +firmware notes: none</description> + <valueType>uint32</valueType> + <enum>VDD40375 = 40375, VDD41750 = 41750, VDD43125 = 43125, VDD44500 = 44500, VDD45875 = 45875, VDD47250 = 47250, VDD48625 = 48625, VDD50000 = 50000, VDD51375 = 51375, VDD52750 = 52750, VDD54125 = 54125, VDD55500 = 55500, VDD56875 = 56875, VDD58250 = 58250, VDD59625 = 59625, VDD61000 = 61000, VDD60375 = 60375, VDD61750 = 61750, VDD63125 = 63125, VDD64500 = 64500, VDD65875 = 65875, VDD67250 = 67250, VDD68625 = 68625, VDD70000 = 70000, VDD71375 = 71375, VDD72750 = 72750, VDD74125 = 74125, VDD75500 = 75500, VDD76875 = 76875, VDD78250 = 78250, VDD79625 = 79625, VDD81000 = 81000</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_SIZE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DIMM Size. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_BANKS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Number of DRAM banks. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_ROWS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Number of DRAM rows. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_COLS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Number of DRAM columns. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_DENSITY</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DRAM Density. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_TRCD</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RAS to CAS Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg_timing +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_TRRD</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Row ACT to Row ACT Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg_timing +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_TRP</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Row Precharge Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg_timing +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_TRAS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>ACT to Precharge Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg_timing +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_TRC</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>ACT to ACT/Refresh Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg_timing +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_TRFC</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Refresh Recovery Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg_timing +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_TWTR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Internal Write to Read Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg_timing +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_TRTP</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Internal Read to Precharge Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg_timing +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_TFAW</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Four ACT Window Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg_timing +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_BL</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Burst Length. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>BL8 = 0, OTF = 1, BC4 = 2,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_CL</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>CAS Latency. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg_timing +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_AL</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Additive Latency. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg_timing +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>DISABLE = 0, CL_MINUS_1 = 1, CL_MUNUS_2 = 2,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_CWL</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>CAS Write Latency. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg_timing +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_RBT</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Read Burst Type. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>SEQUENTIAL = 0, INTERLEAVE = 1,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_TM</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Test Mode. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>NORMAL= 0, TEST = 1,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_DLL_RESET</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DLL Reset. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>NO = 0, YES = 1,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_WR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Write Recovery. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg_timing +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_DLL_PPD</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DLL Precharge PD. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>SLOWEXIT = 0, FASTEXIT = 1,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_DLL_ENABLE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DLL Enable. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>ENABLE = 0, DISABLE = 1,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_TDQS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>TDQS. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_WR_LVL_ENABLE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Write Level Enable. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_OUTPUT_BUFFER</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DRAM Qoff. Enables or disables DRAM output. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>ENABLE = 0, DISABLE = 1,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_PASR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Partial Array Self-Refresh. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>FULL = 0, FIRST_HALF = 1, FIRST_QUARTER = 2, FIRST_EIGHTH = 3, LAST_THREE_FOURTH = 4, LAST_HALF = 5, LAST_QUARTER = 6, LAST_EIGHTH = 7,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_ASR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Auto Self-Refresh. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>SRT = 0, ASR = 1,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DRAM_SRT</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Self-Refresh Temperature Range. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>NORMAL = 0, EXTEND = 1,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_MPR_LOC</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Multi Purpose Register Location. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_MPR_MODE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Multi Purpose Register Mode. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1,</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RCD Control Word. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint64</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_MSS_THROTTLE_NUMERATOR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Each DIMM can have a throttle amount. This is the numerator +creator: mss_eff_cnfg +consumer: mc_config +firmware notes: none</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_THROTTLE_DENOMINATOR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Each DIMM can have a throttle amount. This is the denominator +creator: mss_eff_cnfg +consumer: mc_config +firmware notes: none</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_THROTTLE_CHANNEL_NUMERATOR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This is a channel throttle amount +this is the numerator +creator: mss_eff_cnfg +consumer: mc config +firmware notes:none</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_THROTTLE_CHANNEL_DENOMINATOR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This is a channel throttle amount +this is the denominator +creator: mss_eff_cnfg +consumer: mc config +firmware notes:none</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_WATT_TARGET</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Total memory watts upper limit for this memory channel. Used to compute the throttles on the channel and/or dimms +creator: unknown +consumer: mss_eff_config +firmware notes: none</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_POWER_SLOPE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Power slope value for dimm in double drop config</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_POWER_INT</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Power intercept value for dimm in double drop config</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_DIMM_MAXBANDWIDTH_GBS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DIMM Max Bandwidth in GBs output from thermal procedures</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_DIMM_MAXBANDWIDTH_MRS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DIMM Max Bandwidth in MRs output from thermal procedures</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_CHANNEL_MAXBANDWIDTH_GBS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Channel Max Bandwidth in GBs output from thermal procedures</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_CHANNEL_MAXBANDWIDTH_MRS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Channel Max Bandwidth MRs output from thermal procedures</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_DIMM_MAXPOWER</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DIMM Max Power output from thermal procedures</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_CHANNEL_MAXPOWER</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Channel Max Power output from thermal procedures</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_MEMSIZE</id> + <targetType>TARGET_TYPE_MCS_CHIPLET</targetType> + <description>The amount of memory to set aside for this memory controller. There maybe gaps in the complete range, but this memory controller does not have any more memory than this amount. +creator: extent +consumer: firmware +firmware notes: firmware uses this to know where the base address of the next centaur should configured to such that there is not any memory gaps</description> + <valueType>uint64</valueType> + <writeable/> + <odmVisable/> + <array>8</array> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_MSS_MEMSIZE_MBA</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>At the MBA level, how much memory is available</description> + <valueType>uint64</valueType> + <writeable/> + <odmVisable/> + <persistRuntime/> +</attribute> + +</attributes> diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index 290af15bd..d87bb65bc 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -31,7 +31,8 @@ SUBDIRS = fapi.d hwp.d plat.d test.d # Source XML files #------------------------------------------------------------------------------ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml -HWP_ATTR_XML_FILES = hwp/fapiHwpAttributeInfo.xml +HWP_ATTR_XML_FILES = hwp/fapiHwpAttributeInfo.xml \ + hwp/memory_attributes.xml #------------------------------------------------------------------------------ # Initfiles diff --git a/src/usr/pnor/pnorrp.C b/src/usr/pnor/pnorrp.C index 3b2e5cc0e..0c11032dd 100644 --- a/src/usr/pnor/pnorrp.C +++ b/src/usr/pnor/pnorrp.C @@ -331,7 +331,7 @@ errlHndl_t PnorRP::readTOC() iv_TOC[PNOR::SIDE_A][PNOR::TOC].size = 8 + 8 + PNOR::NUM_SECTIONS*sizeof(TOCEntry_t); iv_TOC[PNOR::SIDE_A][PNOR::HB_EXT_CODE].size = 700*KILOBYTE; //700K iv_TOC[PNOR::SIDE_A][PNOR::GLOBAL_DATA].size = PAGESIZE; //4K - iv_TOC[PNOR::SIDE_A][PNOR::HB_DATA].size = 128*KILOBYTE; //128K + iv_TOC[PNOR::SIDE_A][PNOR::HB_DATA].size = 512*KILOBYTE; //512K // fake PNOR will look like this: TOC::HB_EXT_CODE:GLOBAL_DATA:HB_DATA // virtual addresses @@ -576,7 +576,7 @@ errlHndl_t PnorRP::writeToDevice( uint64_t i_offset, DEVICE_PNOR_ADDRESS(i_chip,i_offset) ); if( l_errhdl ) { - TRACFCOMP(g_trac_pnor, "PnorRP::readFromDevice> Error from device : RC=%X", l_errhdl->reasonCode() ); + TRACFCOMP(g_trac_pnor, "PnorRP::writeToDevice> Error from device : RC=%X", l_errhdl->reasonCode() ); break; } } while(0); diff --git a/src/usr/pnor/test/pnorrptest.H b/src/usr/pnor/test/pnorrptest.H index 3bd139238..f04b7ecc0 100644 --- a/src/usr/pnor/test/pnorrptest.H +++ b/src/usr/pnor/test/pnorrptest.H @@ -67,7 +67,7 @@ class PnorRpTest : public CxxTest::TestSuite /* GLOBAL_DATA */ { PAGESIZE, 0x800AF690 }, /* SBE_IPL */ { 0, 0 }, /* HB_BASE_CODE */ { 0, 0 }, - /* HB_DATA */ { 128*KILOBYTE, 0x800B0690 }, + /* HB_DATA */ { 512*KILOBYTE, 0x800B0690 }, /* HB_ERRLOGS */ { 0, 0 }, /* HB_EXT_CODE */ { 0xAF000, 0x80000690 }, /* HB_RUNTIME */ { 0, 0 }, diff --git a/src/usr/targeting/attrrp.C b/src/usr/targeting/attrrp.C index 8c2d43731..5bdf42c41 100644 --- a/src/usr/targeting/attrrp.C +++ b/src/usr/targeting/attrrp.C @@ -133,7 +133,7 @@ namespace TARGETING void* pAddr = reinterpret_cast<void*>(msg->data[1]); TRACFCOMP(g_trac_targeting, INFO_MRK "AttrRP: Message recv'd: " - "%d, %lx %p", msg->type, vAddr, pAddr); + "0x%x, 0x%lx 0x%p", msg->type, vAddr, pAddr); // Locate corresponding attribute section for message. ssize_t section = -1; @@ -329,8 +329,8 @@ namespace TARGETING l_section->sectionOffset; iv_sections[i].size = l_section->sectionSize; - TRACDCOMP(g_trac_targeting, - "Decoded Attribute Section: %d, %lx %lx %d", + TRACFCOMP(g_trac_targeting, + "Decoded Attribute Section: %d, 0x%lx 0x%lx 0x%lx", iv_sections[i].type, iv_sections[i].vmmAddress, iv_sections[i].pnorAddress, diff --git a/src/usr/targeting/target.C b/src/usr/targeting/target.C index d6946e050..714e614bd 100644 --- a/src/usr/targeting/target.C +++ b/src/usr/targeting/target.C @@ -117,6 +117,7 @@ void Target::_getAttrPtr( if ((*iv_pAttrNames)[i] == i_attr) { l_pAttr = (*iv_pAttrValues)[i]; + break; } } o_pAttr = l_pAttr; diff --git a/src/usr/targeting/xmltohb/attribute_types.xml b/src/usr/targeting/xmltohb/attribute_types.xml index b09981b72..d823e291f 100644 --- a/src/usr/targeting/xmltohb/attribute_types.xml +++ b/src/usr/targeting/xmltohb/attribute_types.xml @@ -831,24 +831,6 @@ <writeable/> </attribute> -<attribute> - <id>MSS_EFF_PRIMARY_RANK</id> - <description>The effective rank group on each port (0 to 3) for each group 0-3</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>4, 4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_EFF_PRIMARY_RANK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - <!-- For POD Testing --> <attribute> <id>NUMERIC_POD_TYPE_TEST</id> @@ -1067,5 +1049,1523 @@ <writeable/> </attribute> -</attributes> +<attribute> + <id>MSS_VOLT</id> + <description>DRAM Voltage. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_VOLT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_FREQ</id> + <description>Frequency of memory channel in MHz. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_FREQ</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_DIMM_MFG_ID_CODE</id> + <description>DIMM Manufacturer ID Code. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_DIMM_MFG_ID_CODE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_RANKS_CONFIGED</id> + <description>DIMM ranks configured. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_RANKS_CONFIGED</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_NUM_RANKS_PER_DIMM</id> + <description>Number of ranks per DIMM. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_NUM_RANKS_PER_DIMM</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_TYPE</id> + <description>Type of DIMM. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_TYPE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_WIDTH</id> + <description>DRAM Device Width. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_WIDTH</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_GEN</id> + <description>DRAM Generation. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_GEN</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_PRIMARY_RANK_GROUP0</id> + <description>Primary RankGroup0. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_PRIMARY_RANK_GROUP0</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_PRIMARY_RANK_GROUP1</id> + <description>Primary RankGroup1. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_PRIMARY_RANK_GROUP1</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_PRIMARY_RANK_GROUP2</id> + <description>Primary RankGroup2. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_PRIMARY_RANK_GROUP2</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> +<attribute> + <id>EFF_PRIMARY_RANK_GROUP3</id> + <description>Primary RankGroup3. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_PRIMARY_RANK_GROUP3</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_SECONDARY_RANK_GROUP0</id> + <description>Secondary RankGroup0. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_SECONDARY_RANK_GROUP0</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_SECONDARY_RANK_GROUP1</id> + <description>Secondary RankGroup1. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_SECONDARY_RANK_GROUP1</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_SECONDARY_RANK_GROUP2</id> + <description>Secondary RankGroup2. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_SECONDARY_RANK_GROUP2</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_SECONDARY_RANK_GROUP3</id> + <description>Secondary RankGroup3. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_SECONDARY_RANK_GROUP3</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_TERTIARY_RANK_GROUP0</id> + <description>Tertiary RankGroup0. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_TERTIARY_RANK_GROUP0</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_TERTIARY_RANK_GROUP1</id> + <description>Tertiary RankGroup1. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_TERTIARY_RANK_GROUP1</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_TERTIARY_RANK_GROUP2</id> + <description>Tertiary RankGroup2. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_TERTIARY_RANK_GROUP2</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_TERTIARY_RANK_GROUP3</id> + <description>Tertiary RankGroup3. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_TERTIARY_RANK_GROUP3</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_QUATERNARY_RANK_GROUP0</id> + <description>Quaternary RankGroup0. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_QUATERNARY_RANK_GROUP0</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_QUATERNARY_RANK_GROUP1</id> + <description>Quaternary RankGroup1. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_QUATERNARY_RANK_GROUP1</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_QUATERNARY_RANK_GROUP2</id> + <description>Quaternary RankGroup2. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_QUATERNARY_RANK_GROUP2</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_QUATERNARY_RANK_GROUP3</id> + <description>Quaternary RankGroup3. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_QUATERNARY_RANK_GROUP3</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_ODT_RD</id> + <description>Rank Read ODT. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2,4</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_ODT_RD</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_ODT_WR</id> + <description>Rank Write ODT. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2,4</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_ODT_WR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_RON</id> + <description>DRAM Ron. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_RON</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_RTT_NOM</id> + <description>DRAM Rtt_Nom. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2,4</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_RTT_NOM</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_RTT_WR</id> + <description>DRAM Rtt_WR. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2,4</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_RTT_WR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_WR_VREF</id> + <description>DRAM Write Vref. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_WR_VREF</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CEN_DRV_IMP_DQ_DQS</id> + <description>Centaur DQ and DQS Drive Impedance. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CEN_DRV_IMP_DQ_DQS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CEN_DRV_IMP_CMD</id> + <description>Centaur Command Drive Impedance. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CEN_DRV_IMP_CMD</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CEN_DRV_IMP_CNTL</id> + <description>Centaur Control Drive Impedance. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CEN_DRV_IMP_CNTL</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CEN_RCV_IMP_DQ_DQS</id> + <description>Centaur DQ and DQS Receiver Impedance. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CEN_RCV_IMP_DQ_DQS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CEN_SLEW_RATE_DQ</id> + <description>Centaur DQ Slew Rate. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CEN_SLEW_RATE_DQ</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CEN_SLEW_RATE_DQS</id> + <description>Centaur DQS Slew Rate. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CEN_SLEW_RATE_DQS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CEN_SLEW_RATE_CMD</id> + <description>Centaur Command Slew Rate. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CEN_SLEW_RATE_CMD</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CEN_SLEW_RATE_CNTL</id> + <description>Centaur Control Slew Rate. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CEN_SLEW_RATE_CNTL</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CEN_RD_VREF</id> + <description>Centaur Read Vref. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CEN_RD_VREF</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_SIZE</id> + <description>DIMM Size. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_SIZE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_BANKS</id> + <description>Number of DRAM banks. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_BANKS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_ROWS</id> + <description>Number of DRAM rows. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_ROWS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_COLS</id> + <description>Number of DRAM columns. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_COLS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_DENSITY</id> + <description>DRAM Density. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_DENSITY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_TRCD</id> + <description>DRAM RAS to CAS Delay. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_TRCD</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_TRRD</id> + <description>DRAM Row ACT to Row ACT Delay. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_TRRD</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_TRP</id> + <description>DRAM Row Precharge Delay. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_TRP</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_TRAS</id> + <description>DRAM ACT to Precharge Delay. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_TRAS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_TRC</id> + <description>DRAM ACT to ACT/Refresh Delay. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_TRC</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_TRFC</id> + <description>DRAM Refresh Recovery Delay. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_TRFC</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_TWTR</id> + <description>DRAM Internal Write to Read Delay. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_TWTR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_TRTP</id> + <description>DRAM Internal Read to Precharge Delay. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_TRTP</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_TFAW</id> + <description>DRAM Four ACT Window Delay. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_TFAW</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_BL</id> + <description>DRAM Burst Length. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_BL</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_CL</id> + <description>DRAM CAS Latency. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_CL</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_AL</id> + <description>DRAM Additive Latency. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_AL</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_CWL</id> + <description>DRAM CAS Write Latency. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_CWL</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_RBT</id> + <description>DRAM Read Burst Type. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_RBT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_TM</id> + <description>DRAM Test Mode. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_TM</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_DLL_RESET</id> + <description>DRAM DLL Reset. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_DLL_RESET</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_WR</id> + <description>DRAM Write Recovery. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_WR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_DLL_PPD</id> + <description>DRAM DLL Precharge PD. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_DLL_PPD</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_DLL_ENABLE</id> + <description>DRAM DLL Enable. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_DLL_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_TDQS</id> + <description>DRAM TDQS. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_TDQS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_WR_LVL_ENABLE</id> + <description>DRAM Write Level Enable. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_WR_LVL_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_OUTPUT_BUFFER</id> + <description>DRAM output buffer. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_OUTPUT_BUFFER</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_PASR</id> + <description>DRAM Partial Array Self-Refresh. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_PASR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_ASR</id> + <description>DRAM Auto Self-Refresh. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_ASR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_SRT</id> + <description>DRAM Self-Refresh Temperature Range. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_SRT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_MPR_LOC</id> + <description>Multi Purpose Register Location. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_MPR_LOC</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_MPR_MODE</id> + <description>Multi Purpose Register Mode. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_MPR_MODE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_RCD_CNTL_WORD_0_15</id> + <description>DIMM RCD Control Word. Initialized and used by HWPs.</description> + <simpleType> + <uint64_t> + <default>0</default> + </uint64_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_THROTTLE_NUMERATOR</id> + <description>DIMM throttle numerator. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_THROTTLE_NUMERATOR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_THROTTLE_DENOMINATOR</id> + <description>DIMM throttle denominator. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_THROTTLE_DENOMINATOR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_THROTTLE_CHANNEL_NUMERATOR</id> + <description>Channel throttle numerator. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_THROTTLE_CHANNEL_NUMERATOR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_THROTTLE_CHANNEL_DENOMINATOR</id> + <description>Channel throttle denominator. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_THROTTLE_CHANNEL_DENOMINATOR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_WATT_TARGET</id> + <description>Channel total memory watts. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_WATT_TARGET</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_POWER_SLOPE</id> + <description>DIMM Power slope value. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_POWER_SLOPE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_POWER_INT</id> + <description>DIMM Power intercept value. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_POWER_INT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_DIMM_MAXBANDWIDTH_GBS</id> + <description>DIMM Max Bandwidth in GBs. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_DIMM_MAXBANDWIDTH_GBS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_DIMM_MAXBANDWIDTH_MRS</id> + <description>DIMM Max Bandwidth in MRs. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_DIMM_MAXBANDWIDTH_MRS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_CHANNEL_MAXBANDWIDTH_GBS</id> + <description>Channel Max Bandwidth in GBs. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_CHANNEL_MAXBANDWIDTH_GBS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_CHANNEL_MAXBANDWIDTH_MRS</id> + <description>Channel Max Bandwidth MRs. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_CHANNEL_MAXBANDWIDTH_MRS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_DIMM_MAXPOWER</id> + <description>DIMM Max Power output. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_DIMM_MAXPOWER</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_CHANNEL_MAXPOWER</id> + <description>Channel Max Power output. Initialized and used by HWPs.</description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_CHANNEL_MAXPOWER</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_MEMSIZE</id> + <description>The amount of memory to set aside for this memory controller. Initialized by HWP.</description> + <simpleType> + <uint64_t> + <default>0</default> + </uint64_t> + <array>8</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_MEMSIZE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_MEMSIZE_MBA</id> + <description>At the MBA level, how much memory is available. Initialized by HWP.</description> + <simpleType> + <uint64_t> + <default>0</default> + </uint64_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_MEMSIZE_MBA</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +</attributes> diff --git a/src/usr/targeting/xmltohb/makefile b/src/usr/targeting/xmltohb/makefile index b6234fc60..4e61e142f 100644 --- a/src/usr/targeting/xmltohb/makefile +++ b/src/usr/targeting/xmltohb/makefile @@ -46,7 +46,8 @@ XMLTOHB_TARGETS = \ XMLTOHB_GENERIC_SOURCES = attribute_types.xml target_types.xml XMLTOHB_FAPIATTR_SOURCES = \ - ${ROOTPATH}/src/usr/hwpf/hwp/fapiHwpAttributeInfo.xml + ${ROOTPATH}/src/usr/hwpf/hwp/fapiHwpAttributeInfo.xml \ + ${ROOTPATH}/src/usr/hwpf/hwp/memory_attributes.xml VMM_CONSTS_FILE = \ ${ROOTPATH}/src/include/usr/vmmconst.h @@ -57,7 +58,7 @@ EXTRA_PARTS = $(addprefix $(IMGDIR)/, $(XMLTOHB_SYSTEM_BINARIES)) EXTRA_CLEAN = $(addprefix $(GENDIR)/, ${XMLTOHB_SYSTEM_BINARIES}) \ $(addprefix $(GENDIR)/, ${XMLTOHB_SYSTEM_BINARIES:.bin=.xml}) \ - ${GENDIR}/generic.xml + ${GENDIR}/generic.xml ${GENDIR}/fapiattrs.xml include ${ROOTPATH}/config.mk @@ -71,12 +72,15 @@ ${EXTRA_PARTS}: ${IMGDIR}/% : ${GENDIR}/% ${GENDIR}/generic.xml: ${XMLTOHB_GENERIC_SOURCES} ./mergexml.sh $^ > $@ +# merge all FAPI attribute files into one +${GENDIR}/fapiattrs.xml: ${XMLTOHB_FAPIATTR_SOURCES} + ./mergexml.sh $^ > $@ + # create the header files, only needs generic xml $(call GENTARGET,$(XMLTOHB_TARGETS)) : \ - xmltohb.pl ${GENDIR}/generic.xml ${XMLTOHB_FAPIATTR_SOURCES} + xmltohb.pl ${GENDIR}/generic.xml ${GENDIR}/fapiattrs.xml ./$< $(addprefix --hb-xml-file=,${GENDIR}/generic.xml) \ - $(addprefix --fapi-attributes-xml-file=,\ - ${XMLTOHB_FAPIATTR_SOURCES}) \ + $(addprefix --fapi-attributes-xml-file=,${GENDIR}/fapiattrs.xml) \ --src-output-dir=$(dir $@) --img-output-dir=none \ --img-output-file=none @@ -85,14 +89,10 @@ ${GENDIR}/%.hb.xml: %.system.xml ${XMLTOHB_GENERIC_SOURCES} ./mergexml.sh $^ > $@ # create the binary files -${GENDIR}/%_targeting.bin: xmltohb.pl ${GENDIR}/%.hb.xml ${XMLTOHB_FAPIATTR_SOURCES} ${VMM_CONSTS_FILE} +${GENDIR}/%_targeting.bin: xmltohb.pl ${GENDIR}/%.hb.xml ${GENDIR}/fapiattrs.xml ${VMM_CONSTS_FILE} ./$< $(addprefix --hb-xml-file=,${GENDIR}/$*.hb.xml) \ - $(addprefix --fapi-attributes-xml-file=,\ - ${XMLTOHB_FAPIATTR_SOURCES}) \ + $(addprefix --fapi-attributes-xml-file=,${GENDIR}/fapiattrs.xml) \ --src-output-dir=none --img-output-dir=$(dir $@) \ --img-output-file=$(notdir $@) \ --vmm-consts-file=$(VMM_CONSTS_FILE) - - - diff --git a/src/usr/targeting/xmltohb/mergexml.sh b/src/usr/targeting/xmltohb/mergexml.sh index acb2f08a2..2d73d0d6b 100755 --- a/src/usr/targeting/xmltohb/mergexml.sh +++ b/src/usr/targeting/xmltohb/mergexml.sh @@ -22,5 +22,5 @@ # # IBM_PROLOG_END echo "<attributes>" -cat $* | grep -v "attributes" | grep -v "</attributes>" +cat $* | grep -v "<attributes>" | grep -v "</attributes>" echo "</attributes>" diff --git a/src/usr/targeting/xmltohb/target_types.xml b/src/usr/targeting/xmltohb/target_types.xml index 808637f05..83839d509 100644 --- a/src/usr/targeting/xmltohb/target_types.xml +++ b/src/usr/targeting/xmltohb/target_types.xml @@ -423,7 +423,90 @@ <id>TYPE</id> <default>MBA</default> </attribute> - <attribute><id>MSS_EFF_PRIMARY_RANK</id></attribute> + <attribute><id>MSS_DIMM_MFG_ID_CODE</id></attribute> + <attribute><id>EFF_DIMM_RANKS_CONFIGED</id></attribute> + <attribute><id>EFF_NUM_RANKS_PER_DIMM</id></attribute> + <attribute><id>EFF_DIMM_TYPE</id></attribute> + <attribute><id>EFF_DRAM_WIDTH</id></attribute> + <attribute><id>EFF_DRAM_GEN</id></attribute> + <attribute><id>EFF_PRIMARY_RANK_GROUP0</id></attribute> + <attribute><id>EFF_PRIMARY_RANK_GROUP1</id></attribute> + <attribute><id>EFF_PRIMARY_RANK_GROUP2</id></attribute> + <attribute><id>EFF_PRIMARY_RANK_GROUP3</id></attribute> + <attribute><id>EFF_SECONDARY_RANK_GROUP0</id></attribute> + <attribute><id>EFF_SECONDARY_RANK_GROUP1</id></attribute> + <attribute><id>EFF_SECONDARY_RANK_GROUP2</id></attribute> + <attribute><id>EFF_SECONDARY_RANK_GROUP3</id></attribute> + <attribute><id>EFF_TERTIARY_RANK_GROUP0</id></attribute> + <attribute><id>EFF_TERTIARY_RANK_GROUP1</id></attribute> + <attribute><id>EFF_TERTIARY_RANK_GROUP2</id></attribute> + <attribute><id>EFF_TERTIARY_RANK_GROUP3</id></attribute> + <attribute><id>EFF_QUATERNARY_RANK_GROUP0</id></attribute> + <attribute><id>EFF_QUATERNARY_RANK_GROUP1</id></attribute> + <attribute><id>EFF_QUATERNARY_RANK_GROUP2</id></attribute> + <attribute><id>EFF_QUATERNARY_RANK_GROUP3</id></attribute> + <attribute><id>EFF_ODT_RD</id></attribute> + <attribute><id>EFF_ODT_WR</id></attribute> + <attribute><id>EFF_DRAM_RON</id></attribute> + <attribute><id>EFF_DRAM_RTT_NOM</id></attribute> + <attribute><id>EFF_DRAM_RTT_WR</id></attribute> + <attribute><id>EFF_DRAM_WR_VREF</id></attribute> + <attribute><id>EFF_CEN_DRV_IMP_DQ_DQS</id></attribute> + <attribute><id>EFF_CEN_DRV_IMP_CMD</id></attribute> + <attribute><id>EFF_CEN_DRV_IMP_CNTL</id></attribute> + <attribute><id>EFF_CEN_RCV_IMP_DQ_DQS</id></attribute> + <attribute><id>EFF_CEN_SLEW_RATE_DQ</id></attribute> + <attribute><id>EFF_CEN_SLEW_RATE_DQS</id></attribute> + <attribute><id>EFF_CEN_SLEW_RATE_CMD</id></attribute> + <attribute><id>EFF_CEN_SLEW_RATE_CNTL</id></attribute> + <attribute><id>EFF_CEN_RD_VREF</id></attribute> + <attribute><id>EFF_DIMM_SIZE</id></attribute> + <attribute><id>EFF_DRAM_BANKS</id></attribute> + <attribute><id>EFF_DRAM_ROWS</id></attribute> + <attribute><id>EFF_DRAM_COLS</id></attribute> + <attribute><id>EFF_DRAM_DENSITY</id></attribute> + <attribute><id>EFF_DRAM_TRCD</id></attribute> + <attribute><id>EFF_DRAM_TRRD</id></attribute> + <attribute><id>EFF_DRAM_TRP</id></attribute> + <attribute><id>EFF_DRAM_TRAS</id></attribute> + <attribute><id>EFF_DRAM_TRC</id></attribute> + <attribute><id>EFF_DRAM_TRFC</id></attribute> + <attribute><id>EFF_DRAM_TWTR</id></attribute> + <attribute><id>EFF_DRAM_TRTP</id></attribute> + <attribute><id>EFF_DRAM_TFAW</id></attribute> + <attribute><id>EFF_DRAM_BL</id></attribute> + <attribute><id>EFF_DRAM_CL</id></attribute> + <attribute><id>EFF_DRAM_AL</id></attribute> + <attribute><id>EFF_DRAM_CWL</id></attribute> + <attribute><id>EFF_DRAM_RBT</id></attribute> + <attribute><id>EFF_DRAM_TM</id></attribute> + <attribute><id>EFF_DRAM_DLL_RESET</id></attribute> + <attribute><id>EFF_DRAM_WR</id></attribute> + <attribute><id>EFF_DRAM_DLL_PPD</id></attribute> + <attribute><id>EFF_DRAM_DLL_ENABLE</id></attribute> + <attribute><id>EFF_DRAM_TDQS</id></attribute> + <attribute><id>EFF_DRAM_WR_LVL_ENABLE</id></attribute> + <attribute><id>EFF_DRAM_OUTPUT_BUFFER</id></attribute> + <attribute><id>EFF_DRAM_PASR</id></attribute> + <attribute><id>EFF_DRAM_ASR</id></attribute> + <attribute><id>EFF_DRAM_SRT</id></attribute> + <attribute><id>EFF_MPR_LOC</id></attribute> + <attribute><id>EFF_MPR_MODE</id></attribute> + <attribute><id>EFF_DIMM_RCD_CNTL_WORD_0_15</id></attribute> + <attribute><id>MSS_THROTTLE_NUMERATOR</id></attribute> + <attribute><id>MSS_THROTTLE_DENOMINATOR</id></attribute> + <attribute><id>MSS_THROTTLE_CHANNEL_NUMERATOR</id></attribute> + <attribute><id>MSS_THROTTLE_CHANNEL_DENOMINATOR</id></attribute> + <attribute><id>MSS_WATT_TARGET</id></attribute> + <attribute><id>MSS_POWER_SLOPE</id></attribute> + <attribute><id>MSS_POWER_INT</id></attribute> + <attribute><id>MSS_DIMM_MAXBANDWIDTH_GBS</id></attribute> + <attribute><id>MSS_DIMM_MAXBANDWIDTH_MRS</id></attribute> + <attribute><id>MSS_CHANNEL_MAXBANDWIDTH_GBS</id></attribute> + <attribute><id>MSS_CHANNEL_MAXBANDWIDTH_MRS</id></attribute> + <attribute><id>MSS_DIMM_MAXPOWER</id></attribute> + <attribute><id>MSS_CHANNEL_MAXPOWER</id></attribute> + <attribute><id>MSS_MEMSIZE_MBA</id></attribute> </targetType> <targetType> @@ -433,6 +516,7 @@ <id>TYPE</id> <default>MCS</default> </attribute> + <attribute><id>MSS_MEMSIZE</id></attribute> </targetType> <targetType> @@ -560,6 +644,8 @@ <field><id>engine</id><value>0</value></field> </default> </attribute> + <attribute><id>MSS_VOLT</id></attribute> + <attribute><id>MSS_FREQ</id></attribute> </targetType> <!-- Centaur MBS --> diff --git a/src/usr/targeting/xmltohb/xmltohb.pl b/src/usr/targeting/xmltohb/xmltohb.pl index c4443b0bb..e071858f5 100755 --- a/src/usr/targeting/xmltohb/xmltohb.pl +++ b/src/usr/targeting/xmltohb/xmltohb.pl @@ -230,7 +230,7 @@ sub validateSubElements { # print keys %{$element} . "\n"; - for my $subElementName (keys %{$element}) + for my $subElementName (sort(keys %{$element})) { if(!exists $criteria->{$subElementName}) { @@ -239,7 +239,7 @@ sub validateSubElements { } } - for my $subElementName (keys %{$criteria}) + for my $subElementName (sort(keys %{$criteria})) { if( ($criteria->{$subElementName}{required} == 1) && (!exists $element->{$subElementName})) @@ -1184,7 +1184,7 @@ sub writeTraitFileTraits { { my $simpleType = $attribute->{simpleType}; my $simpleTypeProperties = simpleTypeProperties(); - for my $typeName (keys %{$simpleType}) + for my $typeName (sort(keys %{$simpleType})) { if(exists $simpleTypeProperties->{$typeName}) { @@ -1215,7 +1215,7 @@ sub writeTraitFileTraits { { fatal("Unsupported simpleType child element for " . "attribute $attribute->{id}. Keys are (" - . join(',',keys %{$simpleType}) . ")"); + . join(',',sort(keys %{$simpleType})) . ")"); } } elsif(exists $attribute->{nativeType}) @@ -1540,7 +1540,7 @@ sub getAttributeDefault { { if(exists $attribute->{simpleType}) { - for my $type (keys %{$simpleTypeProperties}) + for my $type (sort(keys %{$simpleTypeProperties})) { # Note: must check for 'type' before 'default', otherwise # might add value to the hash @@ -2006,7 +2006,7 @@ sub packAttribute { my $simpleType = $attribute->{simpleType}; my $simpleTypeProperties = simpleTypeProperties(); - for my $typeName (keys %{$simpleType}) + for my $typeName (sort(keys %{$simpleType})) { if(exists $simpleTypeProperties->{$typeName}) { @@ -2068,7 +2068,7 @@ sub packAttribute { if( (length $binaryData) < 1) { fatal("Error requested simple type not supported. Keys are (" - . join(',',keys %{$simpleType}) . ")"); + . join(',',sort(keys %{$simpleType})) . ")"); } } elsif(exists $attribute->{complexType}) @@ -2188,7 +2188,7 @@ sub writeTargetingImage { # Serialize per target type attribute list my $perTargetTypeAttrBinData; - for my $attributeId (keys %attrhash) + for my $attributeId (sort(keys %attrhash)) { $perTargetTypeAttrBinData .= packEnumeration( $attributeIdEnumeration, @@ -2318,7 +2318,7 @@ sub writeTargetingImage { } } - for my $attributeId (keys %attrhash) + for my $attributeId (sort(keys %attrhash)) { foreach my $attributeDef (@{$attributes->{attribute}}) { @@ -2533,15 +2533,6 @@ sub writeTargetingImage { print $outFile $heapPnorInitBinData; print $outFile pack("@".($sectionHoH{heapPnorInit}{size} - $heapPnorInitOffset)); - - # Serialize 0 initiated heap section to multiple of 4k page size (pad if - # necessary) - #@TODO: Once host boot support 0 initialization of heap pages for targeting, - # remove the contents of this section, since it will be a "virtual" section. - # Until then, zero out the section and map it into memory - print $outFile pack("@".(length $heapZeroInitBinData)); - print $outFile pack("@".($sectionHoH{heapZeroInit}{size} - - $heapZeroInitOffset)); } __END__ |
