diff options
| -rwxr-xr-x | src/build/citest/etc/workarounds.presimsetup | 13 | ||||
| -rw-r--r-- | src/usr/fsi/test/fsiddtest.H | 5 | ||||
| -rw-r--r-- | src/usr/scom/test/scomtest.H | 326 |
3 files changed, 235 insertions, 109 deletions
diff --git a/src/build/citest/etc/workarounds.presimsetup b/src/build/citest/etc/workarounds.presimsetup index c93cbf311..4dd47b267 100755 --- a/src/build/citest/etc/workarounds.presimsetup +++ b/src/build/citest/etc/workarounds.presimsetup @@ -41,11 +41,22 @@ sed -i -e's/SETENV GFW_P8_VENICE_L3_MB_SIZE.*/SETENV GFW_P8_VENICE_L3_MB_SIZE 8/ # Backing build already contains 910431. Leave this workaround here for future scomdef files #sed -i -e's/SETENV GFW_P8_VENICE_MODEL_EC.*/SETENV GFW_P8_VENICE_MODEL_EC 910431/' $sb/simu/configs/P8_VENICE.config -echo "+++ Update Chip EC levels." +echo "+++ Update Chip EC levels (SW106529)." sed -i -e's/SETENV GFW_P8_VENICE_PROC_EC.*/SETENV GFW_P8_VENICE_PROC_EC 10/' $sb/simu/configs/P8_VENICE.config sed -i -e's/SETENV GFW_P8_VENICE_CENTAUR_EC.*/SETENV GFW_P8_VENICE_CENTAUR_EC 10/' $sb/simu/configs/P8_VENICE.config sed -i -e's/SETENV GFW_P8_SALERNO_PROC_EC.*/SETENV GFW_P8_SALERNO_PROC_EC 10/' $sb/simu/configs/P8_SALERNO.config +echo "+++ Add some scom regs to centaur.chip (SW106529)." +mkdir -p $sb/simu/data/cec-chip/ +cp --update $BACKING_BUILD/src/simu/data/cec-chip/centaur.chip $sb/simu/data/cec-chip/centaur.chip.orig +grep -v DONE $sb/simu/data/cec-chip/centaur.chip.orig > $sb/simu/data/cec-chip/centaur.chip +echo "SCOMREGS # List all scom registers" >> $sb/simu/data/cec-chip/centaur.chip +echo " 0x00012345 #fake register for testing" >> $sb/simu/data/cec-chip/centaur.chip +echo " 0x0FFFFFFF #fake register for testing" >> $sb/simu/data/cec-chip/centaur.chip +echo " 0x02011672 #MBU.MBS.MCBISTS01.SCOMFIR.MCBCMA1Q" >> $sb/simu/data/cec-chip/centaur.chip +echo " 0x02011403 #MBU.MBS.MBS_FIR_MASK_REG" >> $sb/simu/data/cec-chip/centaur.chip +echo "END" >> $sb/simu/data/cec-chip/centaur.chip +echo "DONE" >> $sb/simu/data/cec-chip/centaur.chip echo "+++ Update to new simics build." mkdir -p $sb/simu/data diff --git a/src/usr/fsi/test/fsiddtest.H b/src/usr/fsi/test/fsiddtest.H index 732fb5eb0..50750df6f 100644 --- a/src/usr/fsi/test/fsiddtest.H +++ b/src/usr/fsi/test/fsiddtest.H @@ -52,8 +52,8 @@ class FsiDDTest : public CxxTest::TestSuite */ void test_init(void) { +#if 0 //istep is calling this now TRACFCOMP( g_trac_fsi, "FsiDDTest::test_init> Start" ); - return; //istep is calling this now uint64_t fails = 0; uint64_t total = 0; errlHndl_t l_err = NULL; @@ -70,12 +70,14 @@ class FsiDDTest : public CxxTest::TestSuite } TRACFCOMP( g_trac_fsi, "FsiDDTest::test_init> %d/%d fails", fails, total ); +#endif }; //testcode for Simics verification void test_blah(void) { +#if 0 return; errlHndl_t l_err = NULL; TARGETING::Target* fsi_target = NULL; @@ -104,6 +106,7 @@ class FsiDDTest : public CxxTest::TestSuite delete l_err; } } +#endif }; /** diff --git a/src/usr/scom/test/scomtest.H b/src/usr/scom/test/scomtest.H index 3d7067c50..f08fd7851 100644 --- a/src/usr/scom/test/scomtest.H +++ b/src/usr/scom/test/scomtest.H @@ -45,113 +45,225 @@ class ScomTest: public CxxTest::TestSuite { public: - /** - * @brief SCOM test via FSISCOM - * - */ - void test_FSISCOMreadWrite(void) - { - TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite> Start" ); - - uint64_t fails = 0; - uint64_t total = 0; - errlHndl_t l_err = NULL; - - TARGETING::Target* fsi_target = NULL; - - // Target Proc 1 - the FSI wrap-back connection in simics - TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL); - epath.addLast(TARGETING::TYPE_SYS,0); - epath.addLast(TARGETING::TYPE_NODE,0); - epath.addLast(TARGETING::TYPE_PROC,9); - fsi_target = TARGETING::targetService().toTarget(epath); - - //only run if the target exists and has FSI enabled. - if(fsi_target == NULL) - { - TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite> FSI Target not found, exiting test" ); - return; - } - else if((TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL == fsi_target) || - (fsi_target->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom)) - { - TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite> Target is the MASTER Sentinal or is set to use Xscom, exiting test" ); - return; - } - else if(0 == fsi_target->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom) - { - TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite> useFsiScom set to zero, exiting test" ); - return; - } - - // scratch data to use - //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid - // corrupting the HW. - struct { - uint64_t addr; - uint64_t data; - } test_data[] = { - { 0x120F0000 ,0xFEEDB0B000001234}, - { 0x120F0166, 0xFEDCBA9876543210}, - { 0x00040005, 0x0000000000000000}, - { 0x02040004, 0xFFFFFFFFFFFFFFFF}, - - }; - const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]); - - // allocate space for read data - uint64_t read_data[NUM_ADDRS]; - size_t op_size = sizeof(uint32_t); - - // write all the test registers - for( uint64_t x = 0; x < NUM_ADDRS; x++ ) - { - op_size = sizeof(uint64_t); - - total++; - l_err = deviceWrite( fsi_target, - &(test_data[x].data), - op_size, - DEVICE_SCOM_ADDRESS(test_data[x].addr) ); - if( l_err ) - { - TRACFCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite> Write: Error from device : addr=0x%X, RC=%X", test_data[x].addr, l_err->reasonCode() ); - TS_FAIL( "ScomTest::test_FSISCOMreadWrite> ERROR : Unexpected error log from write1" ); - fails++; - errlCommit(l_err,SCOM_COMP_ID); - delete l_err; - } - } - - // read all the test registers - for( uint64_t x = 0; x < NUM_ADDRS; x++ ) - { - op_size = sizeof(uint64_t); - - total++; - l_err = deviceRead( fsi_target, - &(read_data[x]), - op_size, - DEVICE_SCOM_ADDRESS(test_data[x].addr) ); - if( l_err ) - { - TRACFCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite> read: Error from device : addr=0x%X, RC=%X", test_data[x].addr, l_err->reasonCode() ); - TS_FAIL( "ScomTest::test_FSISCOMreadWrite> ERROR : Unexpected error log from write1" ); - fails++; - errlCommit(l_err,SCOM_COMP_ID); - delete l_err; - } - else if(read_data[x] != test_data[x].data) - { - TRACFCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite> read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", test_data[x].addr, read_data[x], test_data[x].data); - TS_FAIL( "ScomTest::test_FSISCOMreadWrite> ERROR : Data miss-match between read and expected data" ); - fails++; - } - } - - TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite> %d/%d fails", fails, total ); - - } + /** + * @brief SCOM test via FSISCOM to Venice + * + */ + void test_FSISCOMreadWrite_proc(void) + { + + TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> Start" ); + + uint64_t fails = 0; + uint64_t total = 0; + errlHndl_t l_err = NULL; + + TARGETING::Target* scom_target = NULL; + + // Target Proc 1 - the FSI wrap-back connection in simics + TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL); + epath.addLast(TARGETING::TYPE_SYS,0); + epath.addLast(TARGETING::TYPE_NODE,0); + epath.addLast(TARGETING::TYPE_PROC,9); + scom_target = TARGETING::targetService().toTarget(epath); + + //only run if the target exists and has FSI enabled. + if(scom_target == NULL) + { + TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> FSI Target not found, exiting test" ); + return; + } + else if((TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL == scom_target) || + (scom_target->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom)) + { + TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> Target is the MASTER Sentinal or is set to use Xscom, exiting test" ); + return; + } + else if(0 == scom_target->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom) + { + TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> useFsiScom set to zero, exiting test" ); + return; + } + + // scratch data to use + //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid + // corrupting the HW. + struct { + uint64_t addr; + uint64_t data; + } test_data[] = { + { 0x120F0000 ,0xFEEDB0B000001234}, + { 0x120F0166, 0xFEDCBA9876543210}, + { 0x00040005, 0x0000000000000000}, + { 0x02040004, 0xFFFFFFFFFFFFFFFF}, + + }; + const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]); + + // allocate space for read data + uint64_t read_data[NUM_ADDRS]; + size_t op_size = sizeof(uint32_t); + + // write all the test registers + for( uint64_t x = 0; x < NUM_ADDRS; x++ ) + { + op_size = sizeof(uint64_t); + + total++; + l_err = deviceWrite( scom_target, + &(test_data[x].data), + op_size, + DEVICE_SCOM_ADDRESS(test_data[x].addr) ); + if( l_err ) + { + TRACFCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> Write: Error from device : addr=0x%X, RC=%X", test_data[x].addr, l_err->reasonCode() ); + TS_FAIL( "ScomTest::test_FSISCOMreadWrite_proc> ERROR : Unexpected error log from write1" ); + fails++; + errlCommit(l_err,SCOM_COMP_ID); + delete l_err; + } + } + + // read all the test registers + for( uint64_t x = 0; x < NUM_ADDRS; x++ ) + { + op_size = sizeof(uint64_t); + + total++; + l_err = deviceRead( scom_target, + &(read_data[x]), + op_size, + DEVICE_SCOM_ADDRESS(test_data[x].addr) ); + if( l_err ) + { + TRACFCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> read: Error from device : addr=0x%X, RC=%X", test_data[x].addr, l_err->reasonCode() ); + TS_FAIL( "ScomTest::test_FSISCOMreadWrite_proc> ERROR : Unexpected error log from write1" ); + fails++; + errlCommit(l_err,SCOM_COMP_ID); + delete l_err; + } + else if(read_data[x] != test_data[x].data) + { + TRACFCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", test_data[x].addr, read_data[x], test_data[x].data); + TS_FAIL( "ScomTest::test_FSISCOMreadWrite_proc> ERROR : Data miss-match between read and expected data" ); + fails++; + } + } + + TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> %d/%d fails", fails, total ); + + } + + /** + * @brief SCOM test via FSISCOM to Centaur + * + */ + void test_FSISCOMreadWrite_centaur(void) + { + + TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> Start" ); + + uint64_t fails = 0; + uint64_t total = 0; + errlHndl_t l_err = NULL; + + TARGETING::Target* scom_target = NULL; + + // Target Centaur0 - the local centaur + TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL); + epath.addLast(TARGETING::TYPE_SYS,0); + epath.addLast(TARGETING::TYPE_NODE,0); + epath.addLast(TARGETING::TYPE_MEMBUF,0); + scom_target = TARGETING::targetService().toTarget(epath); + + //only run if the target exists and has FSI enabled. + if(scom_target == NULL) + { + TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> FSI Target not found, exiting test" ); + return; + } + else if((TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL == scom_target) || + (scom_target->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom) || + (scom_target->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useInbandScom)) + { + TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> Target is the MASTER Sentinal or is set to use Xscom or Inband Scom, exiting test" ); + return; + } + else if(0 == scom_target->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom) + { + TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> useFsiScom set to zero, exiting test" ); + return; + } + + // scratch data to use + //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid + // corrupting the HW. + struct { + uint64_t addr; + uint64_t data; + } test_data[] = { + { 0x00012345 , 0x1111222233334444 }, + /* Simics is chopping off the upper nibble... SW108655 + { 0x02011403 , 0x123456789ABCDEF0 }, + { 0x02011672 , 0x1122334455667788 }, + */ + + }; + const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]); + + // allocate space for read data + uint64_t read_data[NUM_ADDRS]; + size_t op_size = sizeof(uint32_t); + + // write all the test registers + for( uint64_t x = 0; x < NUM_ADDRS; x++ ) + { + op_size = sizeof(uint64_t); + + total++; + l_err = deviceWrite( scom_target, + &(test_data[x].data), + op_size, + DEVICE_SCOM_ADDRESS(test_data[x].addr) ); + if( l_err ) + { + TRACFCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> Write: Error from device : addr=0x%X, RC=%X", test_data[x].addr, l_err->reasonCode() ); + TS_FAIL( "ScomTest::test_FSISCOMreadWrite_centaur> ERROR : Unexpected error log from write1" ); + fails++; + errlCommit(l_err,SCOM_COMP_ID); + delete l_err; + } + } + + // read all the test registers + for( uint64_t x = 0; x < NUM_ADDRS; x++ ) + { + op_size = sizeof(uint64_t); + + total++; + l_err = deviceRead( scom_target, + &(read_data[x]), + op_size, + DEVICE_SCOM_ADDRESS(test_data[x].addr) ); + if( l_err ) + { + TRACFCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> read: Error from device : addr=0x%X, RC=%X", test_data[x].addr, l_err->reasonCode() ); + TS_FAIL( "ScomTest::test_FSISCOMreadWrite_centaur> ERROR : Unexpected error log from write1" ); + fails++; + errlCommit(l_err,SCOM_COMP_ID); + delete l_err; + } + else if(read_data[x] != test_data[x].data) + { + TRACFCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", test_data[x].addr, read_data[x], test_data[x].data); + TS_FAIL( "ScomTest::test_FSISCOMreadWrite_centaur> ERROR : Data miss-match between read and expected data" ); + fails++; + } + } + + TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> %d/%d fails", fails, total ); + + } //@todo - write tests to verify connection between XSCOM and FSISCOM |
