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-rw-r--r--src/usr/diag/prdf/common/plat/cen/cen_centaur.rule2179
-rw-r--r--src/usr/diag/prdf/common/plat/cen/cen_common_actions.rule131
-rw-r--r--src/usr/diag/prdf/common/plat/cen/cen_mba.rule661
-rw-r--r--src/usr/diag/prdf/common/plat/p9/prdfCommonPlugins.C2
-rwxr-xr-xsrc/usr/diag/prdf/common/plat/p9/prdfP9Configurator.C16
-rwxr-xr-xsrc/usr/diag/prdf/common/rule/prdfRuleFiles.C6
-rwxr-xr-xsrc/usr/diag/prdf/common/rule/prdfRuleFiles.H6
-rw-r--r--src/usr/diag/prdf/common/rule/prdf_rule.mk2
8 files changed, 2997 insertions, 6 deletions
diff --git a/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule b/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule
new file mode 100644
index 000000000..eff545ead
--- /dev/null
+++ b/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule
@@ -0,0 +1,2179 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/usr/diag/prdf/common/plat/cen/cen_centaur.rule $
+#
+# OpenPOWER HostBoot Project
+#
+# Contributors Listed Below - COPYRIGHT 2016,2017
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+chip cen_centaur
+{
+ name "Centaur chip";
+ targettype TYPE_MEMBUF;
+ sigoff 0x9000;
+ dump DUMP_CONTENT_HW;
+ scomlen 64;
+
+ #############################################################################
+ # #
+ # ###### #
+ # # # ###### #### ### #### ##### ###### ##### #### #
+ # # # # # # # # # # # # # #
+ # ###### ##### # # #### # ##### # # #### #
+ # # # # # ### # # # # ##### # #
+ # # # # # # # # # # # # # # # #
+ # # # ###### #### ### #### # ###### # # #### #
+ # #
+ #############################################################################
+
+ ############################################################################
+ # Global Attention FIR
+ ############################################################################
+
+ register GLOBAL_CS_FIR
+ {
+ name "Global Checkstop Attention FIR";
+ scomaddr 0x500F001C;
+ capture group default;
+ };
+
+ register GLOBAL_RE_FIR
+ {
+ name "Global Recoverable Attention FIR";
+ scomaddr 0x500F001B;
+ capture group default;
+ };
+
+ ############################################################################
+ # Global Special Attention FIR
+ ############################################################################
+
+ register GLOBAL_SPA_FIR
+ {
+ name "Global Special Attention FIR";
+ scomaddr 0x500F001A;
+ capture group default;
+ };
+
+ ############################################################################
+ # TP Chiplet FIR
+ ############################################################################
+
+ register TP_CHIPLET_CS_FIR
+ {
+ name "TP Chiplet Checkstop FIR";
+ scomaddr 0x01040000;
+ capture group default;
+ };
+
+ register TP_CHIPLET_RE_FIR
+ {
+ name "TP Chiplet Recoverable FIR";
+ scomaddr 0x01040001;
+ capture group default;
+ };
+
+ register TP_CHIPLET_FIR_MASK
+ {
+ name "TP Chiplet FIR MASK";
+ scomaddr 0x01040002;
+ capture group default;
+ };
+
+ ############################################################################
+ # TP chiplet pervasive FIR
+ ############################################################################
+
+ register TP_LFIR
+ {
+ name "TP chiplet pervasive FIR";
+ scomaddr 0x0104000A;
+ reset (&, 0x0104000B);
+ mask (|, 0x0104000F);
+ capture group default;
+ };
+
+ register TP_LFIR_MASK
+ {
+ name "TP chiplet pervasive FIR MASK";
+ scomaddr 0x0104000D;
+ capture group default;
+ };
+
+ register TP_LFIR_ACT0
+ {
+ name "TP chiplet pervasive FIR ACT0";
+ scomaddr 0x01040010;
+ capture group default;
+ capture req nonzero("TP_LFIR");
+ };
+
+ register TP_LFIR_ACT1
+ {
+ name "TP chiplet pervasive FIR ACT1";
+ scomaddr 0x01040011;
+ capture group default;
+ capture req nonzero("TP_LFIR");
+ };
+
+ ############################################################################
+ # NEST Chiplet FIR
+ ############################################################################
+
+ register NEST_CHIPLET_CS_FIR
+ {
+ name "NEST Chiplet Checkstop FIR";
+ scomaddr 0x02040000;
+ capture group default;
+ };
+
+ register NEST_CHIPLET_RE_FIR
+ {
+ name "NEST Chiplet Recoverable FIR";
+ scomaddr 0x02040001;
+ capture group default;
+ };
+
+ register NEST_CHIPLET_FIR_MASK
+ {
+ name "NEST Chiplet FIR MASK";
+ scomaddr 0x02040002;
+ capture group default;
+ };
+
+ ############################################################################
+ # NEST chiplet pervasive FIR
+ ############################################################################
+
+ register NEST_LFIR
+ {
+ name "NEST chiplet pervasive FIR";
+ scomaddr 0x0204000A;
+ reset (&, 0x0204000B);
+ mask (|, 0x0204000F);
+ capture group default;
+ };
+
+ register NEST_LFIR_MASK
+ {
+ name "NEST chiplet pervasive FIR MASK";
+ scomaddr 0x0204000D;
+ capture group default;
+ };
+
+ register NEST_LFIR_ACT0
+ {
+ name "NEST chiplet pervasive FIR ACT0";
+ scomaddr 0x02040010;
+ capture group default;
+ capture req nonzero("NEST_LFIR");
+ };
+
+ register NEST_LFIR_ACT1
+ {
+ name "NEST chiplet pervasive FIR ACT1";
+ scomaddr 0x02040011;
+ capture group default;
+ capture req nonzero("NEST_LFIR");
+ };
+
+ ############################################################################
+ # Memory Buffer DMI FIR
+ ############################################################################
+
+ register DMIFIR
+ {
+ name "Memory Buffer DMI FIR";
+ scomaddr 0x02010400;
+ reset (&, 0x02010401);
+ mask (|, 0x02010405);
+ capture group default;
+ };
+
+ register DMIFIR_MASK
+ {
+ name "Memory Buffer DMI FIR MASK";
+ scomaddr 0x02010403;
+ capture group default;
+ };
+
+ register DMIFIR_ACT0
+ {
+ name "Memory Buffer DMI FIR ACT0";
+ scomaddr 0x02010406;
+ capture group default;
+ capture req nonzero("DMIFIR");
+ };
+
+ register DMIFIR_ACT1
+ {
+ name "Memory Buffer DMI FIR ACT1";
+ scomaddr 0x02010407;
+ capture group default;
+ capture req nonzero("DMIFIR");
+ };
+
+ ############################################################################
+ # Memory Buffer MBI FIR
+ ############################################################################
+
+ register MBIFIR
+ {
+ name "Memory Buffer MBI FIR";
+ scomaddr 0x02010800;
+ reset (&, 0x02010801);
+ mask (|, 0x02010805);
+ capture group default;
+ };
+
+ register MBIFIR_MASK
+ {
+ name "Memory Buffer MBI FIR MASK";
+ scomaddr 0x02010803;
+ capture group default;
+ };
+
+ register MBIFIR_ACT0
+ {
+ name "Memory Buffer MBI FIR ACT0";
+ scomaddr 0x02010806;
+ capture group default;
+ capture req nonzero("MBIFIR");
+ };
+
+ register MBIFIR_ACT1
+ {
+ name "Memory Buffer MBI FIR ACT1";
+ scomaddr 0x02010807;
+ capture group default;
+ capture req nonzero("MBIFIR");
+ };
+
+ ############################################################################
+ # Memory Buffer MBS FIR
+ ############################################################################
+
+ register MBSFIR
+ {
+ name "Memory Buffer MBS FIR";
+ scomaddr 0x02011400;
+ reset (&, 0x02011401);
+ mask (|, 0x02011405);
+ capture group default;
+ };
+
+ register MBSFIR_MASK
+ {
+ name "Memory Buffer MBS FIR MASK";
+ scomaddr 0x02011403;
+ capture group default;
+ };
+
+ register MBSFIR_ACT0
+ {
+ name "Memory Buffer MBS FIR ACT0";
+ scomaddr 0x02011406;
+ capture group default;
+ capture req nonzero("MBSFIR");
+ };
+
+ register MBSFIR_ACT1
+ {
+ name "Memory Buffer MBS FIR ACT1";
+ scomaddr 0x02011407;
+ capture group default;
+ capture req nonzero("MBSFIR");
+ };
+
+ ############################################################################
+ # Memory Buffer MBS SECURE FIR
+ ############################################################################
+
+ # This register is hardwired to channel failure (checkstop) and we cannot
+ # mask or change the state of the action registers.
+ register MBSSECUREFIR
+ {
+ name "Memory Buffer MBS SECURE FIR";
+ scomaddr 0x0201141e;
+ reset (&, 0x0201141f);
+ capture group default;
+ };
+
+ ############################################################################
+ # Memory Buffer MBS ECC FIR 0
+ ############################################################################
+
+ register MBSECCFIR_0
+ {
+ name "Memory Buffer MBS ECC FIR 0";
+ scomaddr 0x02011440;
+ reset (&, 0x02011441);
+ mask (|, 0x02011445);
+ capture group default;
+ };
+
+ register MBSECCFIR_0_MASK
+ {
+ name "Memory Buffer MBS ECC FIR 0 MASK";
+ scomaddr 0x02011443;
+ capture group default;
+ };
+
+ register MBSECCFIR_0_ACT0
+ {
+ name "Memory Buffer MBS ECC FIR 0 ACT0";
+ scomaddr 0x02011446;
+ capture group default;
+ capture req nonzero("MBSECCFIR_0");
+ };
+
+ register MBSECCFIR_0_ACT1
+ {
+ name "Memory Buffer MBS ECC FIR 0 ACT1";
+ scomaddr 0x02011447;
+ capture group default;
+ capture req nonzero("MBSECCFIR_0");
+ };
+
+ ############################################################################
+ # Memory Buffer MBS ECC FIR 1
+ ############################################################################
+
+ register MBSECCFIR_1
+ {
+ name "Memory Buffer MBS ECC FIR 1";
+ scomaddr 0x02011480;
+ reset (&, 0x02011481);
+ mask (|, 0x02011485);
+ capture group default;
+ };
+
+ register MBSECCFIR_1_MASK
+ {
+ name "Memory Buffer MBS ECC FIR 1 MASK";
+ scomaddr 0x02011483;
+ capture group default;
+ };
+
+ register MBSECCFIR_1_ACT0
+ {
+ name "Memory Buffer MBS ECC FIR 1 ACT0";
+ scomaddr 0x02011486;
+ capture group default;
+ capture req nonzero("MBSECCFIR_1");
+ };
+
+ register MBSECCFIR_1_ACT1
+ {
+ name "Memory Buffer MBS ECC FIR 1 ACT1";
+ scomaddr 0x02011487;
+ capture group default;
+ capture req nonzero("MBSECCFIR_1");
+ };
+
+ ############################################################################
+ # Memory Buffer SCAC FIR
+ ############################################################################
+
+ register SCACFIR
+ {
+ name "Memory Buffer SCAC FIR";
+ scomaddr 0x020115c0;
+ reset (&, 0x020115c1);
+ mask (|, 0x020115c5);
+ capture group default;
+ };
+
+ register SCACFIR_MASK
+ {
+ name "Memory Buffer SCAC FIR MASK";
+ scomaddr 0x020115c3;
+ capture group default;
+ };
+
+ register SCACFIR_ACT0
+ {
+ name "Memory Buffer SCAC FIR ACT0";
+ scomaddr 0x020115c6;
+ capture group default;
+ capture req nonzero("SCACFIR");
+ };
+
+ register SCACFIR_ACT1
+ {
+ name "Memory Buffer SCAC FIR ACT1";
+ scomaddr 0x020115c7;
+ capture group default;
+ capture req nonzero("SCACFIR");
+ };
+
+ ############################################################################
+ # Memory Buffer MCBIST FIR 0
+ ############################################################################
+
+ register MCBISTFIR_0
+ {
+ name "Memory Buffer MCBIST FIR 0";
+ scomaddr 0x02011600;
+ reset (&, 0x02011601);
+ mask (|, 0x02011605);
+ capture group default;
+ };
+
+ register MCBISTFIR_0_MASK
+ {
+ name "Memory Buffer MCBIST FIR 0 MASK";
+ scomaddr 0x02011603;
+ capture group default;
+ };
+
+ register MCBISTFIR_0_ACT0
+ {
+ name "Memory Buffer MCBIST FIR 0 ACT0";
+ scomaddr 0x02011606;
+ capture group default;
+ capture req nonzero("MCBISTFIR_0");
+ };
+
+ register MCBISTFIR_0_ACT1
+ {
+ name "Memory Buffer MCBIST FIR 0 ACT1";
+ scomaddr 0x02011607;
+ capture group default;
+ capture req nonzero("MCBISTFIR_0");
+ };
+
+ ############################################################################
+ # Memory Buffer MCBIST FIR 1
+ ############################################################################
+
+ register MCBISTFIR_1
+ {
+ name "Memory Buffer MCBIST FIR 1";
+ scomaddr 0x02011700;
+ reset (&, 0x02011701);
+ mask (|, 0x02011705);
+ capture group default;
+ };
+
+ register MCBISTFIR_1_MASK
+ {
+ name "Memory Buffer MCBIST FIR 1 MASK";
+ scomaddr 0x02011703;
+ capture group default;
+ };
+
+ register MCBISTFIR_1_ACT0
+ {
+ name "Memory Buffer MCBIST FIR 1 ACT0";
+ scomaddr 0x02011706;
+ capture group default;
+ capture req nonzero("MCBISTFIR_1");
+ };
+
+ register MCBISTFIR_1_ACT1
+ {
+ name "Memory Buffer MCBIST FIR 1 ACT1";
+ scomaddr 0x02011707;
+ capture group default;
+ capture req nonzero("MCBISTFIR_1");
+ };
+
+ ############################################################################
+ # MEM Chiplet FIR
+ ############################################################################
+
+ register MEM_CHIPLET_CS_FIR
+ {
+ name "MEM Chiplet Checkstop FIR";
+ scomaddr 0x03040000;
+ capture group default;
+ };
+
+ register MEM_CHIPLET_RE_FIR
+ {
+ name "MEM Chiplet Recoverable FIR";
+ scomaddr 0x03040001;
+ capture group default;
+ };
+
+ register MEM_CHIPLET_FIR_MASK
+ {
+ name "MEM Chiplet FIR MASK";
+ scomaddr 0x03040002;
+ capture group default;
+ };
+
+ ############################################################################
+ # MEM Chiplet Special Attention FIR
+ ############################################################################
+
+ register MEM_CHIPLET_SPA_FIR
+ {
+ name "MEM Chiplet Special Attention FIR";
+ scomaddr 0x03040004;
+ capture group default;
+ };
+
+ register MEM_CHIPLET_SPA_FIR_MASK
+ {
+ name "MEM Chiplet Special Attention FIR MASK";
+ scomaddr 0x03040007;
+ capture group default;
+ };
+
+ ############################################################################
+ # MEM chiplet pervasive FIR
+ ############################################################################
+
+ register MEM_LFIR
+ {
+ name "MEM chiplet pervasive FIR";
+ scomaddr 0x0304000A;
+ reset (&, 0x0304000B);
+ mask (|, 0x0304000F);
+ capture group default;
+ };
+
+ register MEM_LFIR_MASK
+ {
+ name "MEM chiplet pervasive FIR MASK";
+ scomaddr 0x0304000D;
+ capture group default;
+ };
+
+ register MEM_LFIR_ACT0
+ {
+ name "MEM chiplet pervasive FIR ACT0";
+ scomaddr 0x03040010;
+ capture group default;
+ capture req nonzero("MEM_LFIR");
+ };
+
+ register MEM_LFIR_ACT1
+ {
+ name "MEM chiplet pervasive FIR ACT1";
+ scomaddr 0x03040011;
+ capture group default;
+ capture req nonzero("MEM_LFIR");
+ };
+
+
+# Include registers not defined by the xml
+.include "cen_centaur_regs.rule";
+
+};
+
+ ##############################################################################
+ # #
+ # #### # #
+ # # # # # # ##### ### # # # ## ##### ### ### # # ### #
+ # # # # # # # # # # # # # # # # # ## # # #
+ # #### # # # #### ### # ####### # # # # # # # # ### #
+ # # # # # # # # # # # # # # # # # # ## # #
+ # # # ### #### ##### ### # # # ## # ### ### # # ### #
+ # #
+ ##############################################################################
+
+################################################################################
+# Global Attention FIR
+################################################################################
+
+rule rGLOBAL_FIR
+{
+ UNIT_CS:
+ GLOBAL_CS_FIR;
+ RECOVERABLE:
+ GLOBAL_RE_FIR;
+};
+
+group gGLOBAL_FIR attntype UNIT_CS, RECOVERABLE filter singlebit
+{
+ /** GLOBAL_FIR[1]
+ * Attention from TP chiplet
+ */
+ (rGLOBAL_FIR, bit(1)) ? analyze(gTP_CHIPLET_FIR);
+
+ /** GLOBAL_FIR[2]
+ * Attention from NEST chiplet
+ */
+ (rGLOBAL_FIR, bit(2)) ? analyze(gNEST_CHIPLET_FIR);
+
+ /** GLOBAL_FIR[3]
+ * Attention from MEM chiplet
+ */
+ (rGLOBAL_FIR, bit(3)) ? analyze(gMEM_CHIPLET_FIR);
+
+};
+
+################################################################################
+# Global Special Attention FIR
+################################################################################
+
+rule rGLOBAL_SPA_FIR
+{
+ HOST_ATTN:
+ GLOBAL_SPA_FIR;
+};
+
+group gGLOBAL_SPA_FIR attntype HOST_ATTN filter singlebit
+{
+ /** GLOBAL_SPA_FIR[3]
+ * Attention from MEM chiplet
+ */
+ (rGLOBAL_SPA_FIR, bit(3)) ? analyze(gMEM_CHIPLET_SPA_FIR);
+
+};
+
+################################################################################
+# TP Chiplet FIR
+################################################################################
+
+rule rTP_CHIPLET_FIR
+{
+ UNIT_CS:
+ TP_CHIPLET_CS_FIR & ~TP_CHIPLET_FIR_MASK & `1fffffffffffffff`;
+ RECOVERABLE:
+ (TP_CHIPLET_RE_FIR >> 2) & ~TP_CHIPLET_FIR_MASK & `1fffffffffffffff`;
+};
+
+group gTP_CHIPLET_FIR filter singlebit
+{
+ /** TP_CHIPLET_FIR[3]
+ * Attention from TP_LFIR
+ */
+ (rTP_CHIPLET_FIR, bit(3)) ? analyze(gTP_LFIR);
+
+};
+
+################################################################################
+# TP chiplet pervasive FIR
+################################################################################
+
+rule rTP_LFIR
+{
+ UNIT_CS:
+ TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & ~TP_LFIR_ACT1;
+ RECOVERABLE:
+ TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & TP_LFIR_ACT1;
+};
+
+group gTP_LFIR filter singlebit
+{
+ /** TP_LFIR[0]
+ * CFIR internal parity error
+ */
+ (rTP_LFIR, bit(0)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[1]
+ * GPIO (PCB error)
+ */
+ (rTP_LFIR, bit(1)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[2]
+ * CC (PCB error)
+ */
+ (rTP_LFIR, bit(2)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[3]
+ * CC (OPCG, parity, scan collision, ...)
+ */
+ (rTP_LFIR, bit(3)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[4]
+ * PSC (PCB error)
+ */
+ (rTP_LFIR, bit(4)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[5]
+ * PSC (parity error)
+ */
+ (rTP_LFIR, bit(5)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[6]
+ * Thermal (parity error)
+ */
+ (rTP_LFIR, bit(6)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[7]
+ * Thermal (PCB error)
+ */
+ (rTP_LFIR, bit(7)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[8]
+ * Thermal (critical trip error)
+ */
+ (rTP_LFIR, bit(8)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[9]
+ * Thermal (fatal trip error)
+ */
+ (rTP_LFIR, bit(9)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[10]
+ * Thermal (voltage trip error)
+ */
+ (rTP_LFIR, bit(10)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[11:12]
+ * Trace Array ( error)
+ */
+ (rTP_LFIR, bit(11|12)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[13:14]
+ * ITR
+ */
+ (rTP_LFIR, bit(13|14)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[15]
+ * ITR (itr_tc_pcbsl_slave_fir_err)
+ */
+ (rTP_LFIR, bit(15)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[16:18]
+ * PIB
+ */
+ (rTP_LFIR, bit(16|17|18)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[19]
+ * NEST PLLlock
+ */
+ (rTP_LFIR, bit(19)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[20]
+ * MEM PLLlock
+ */
+ (rTP_LFIR, bit(20)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[21:39]
+ * Reserved
+ */
+ (rTP_LFIR, bit(21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? TBDDefaultCallout;
+
+ /** TP_LFIR[40]
+ * malfunction alert (local xstop in another chiplet)
+ */
+ (rTP_LFIR, bit(40)) ? TBDDefaultCallout;
+
+};
+
+################################################################################
+# NEST Chiplet FIR
+################################################################################
+
+rule rNEST_CHIPLET_FIR
+{
+ UNIT_CS:
+ NEST_CHIPLET_CS_FIR & ~NEST_CHIPLET_FIR_MASK & `1fffffffffffffff`;
+ RECOVERABLE:
+ (NEST_CHIPLET_RE_FIR >> 2) & ~NEST_CHIPLET_FIR_MASK & `1fffffffffffffff`;
+};
+
+group gNEST_CHIPLET_FIR filter singlebit
+{
+ /** NEST_CHIPLET_FIR[3]
+ * Attention from NEST_LFIR
+ */
+ (rNEST_CHIPLET_FIR, bit(3)) ? analyze(gNEST_LFIR);
+
+ /** NEST_CHIPLET_FIR[5]
+ * Attention from DMIFIR
+ */
+ (rNEST_CHIPLET_FIR, bit(5)) ? analyze(gDMIFIR);
+
+ /** NEST_CHIPLET_FIR[6]
+ * Attention from MBIFIR
+ */
+ (rNEST_CHIPLET_FIR, bit(6)) ? analyze(gMBIFIR);
+
+ /** NEST_CHIPLET_FIR[7]
+ * Attention from MBSFIR
+ */
+ (rNEST_CHIPLET_FIR, bit(7)) ? analyze(gMBSFIR);
+
+ /** NEST_CHIPLET_FIR[8]
+ * Attention from MCBISTFIR
+ */
+ (rNEST_CHIPLET_FIR, bit(8)) ? analyze(gMCBISTFIR_0);
+
+ /** NEST_CHIPLET_FIR[9]
+ * Attention from MCBISTFIR
+ */
+ (rNEST_CHIPLET_FIR, bit(9)) ? analyze(gMCBISTFIR_1);
+
+ /** NEST_CHIPLET_FIR[10]
+ * Attention from MBSECCFIR
+ */
+ (rNEST_CHIPLET_FIR, bit(10)) ? analyze(gMBSECCFIR_0);
+
+ /** NEST_CHIPLET_FIR[11]
+ * Attention from MBSECCFIR
+ */
+ (rNEST_CHIPLET_FIR, bit(11)) ? analyze(gMBSECCFIR_1);
+
+ /** NEST_CHIPLET_FIR[13]
+ * Attention from SCACFIR
+ */
+ (rNEST_CHIPLET_FIR, bit(13)) ? analyze(gSCACFIR);
+
+ /** NEST_CHIPLET_FIR[14]
+ * Attention from MBSSECUREFIR
+ */
+ (rNEST_CHIPLET_FIR, bit(14)) ? analyze(gMBSSECUREFIR);
+
+};
+
+################################################################################
+# NEST chiplet pervasive FIR
+################################################################################
+
+rule rNEST_LFIR
+{
+ UNIT_CS:
+ NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 & ~NEST_LFIR_ACT1;
+ RECOVERABLE:
+ NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 & NEST_LFIR_ACT1;
+};
+
+group gNEST_LFIR filter singlebit
+{
+ /** NEST_LFIR[0]
+ * CFIR internal parity error
+ */
+ (rNEST_LFIR, bit(0)) ? TBDDefaultCallout;
+
+ /** NEST_LFIR[1]
+ * GPIO (PCB error)
+ */
+ (rNEST_LFIR, bit(1)) ? TBDDefaultCallout;
+
+ /** NEST_LFIR[2]
+ * CC (PCB error)
+ */
+ (rNEST_LFIR, bit(2)) ? TBDDefaultCallout;
+
+ /** NEST_LFIR[3]
+ * CC (OPCG, parity, scan collision, ...)
+ */
+ (rNEST_LFIR, bit(3)) ? TBDDefaultCallout;
+
+ /** NEST_LFIR[4]
+ * PSC (PCB error)
+ */
+ (rNEST_LFIR, bit(4)) ? TBDDefaultCallout;
+
+ /** NEST_LFIR[5]
+ * PSC (parity error)
+ */
+ (rNEST_LFIR, bit(5)) ? TBDDefaultCallout;
+
+ /** NEST_LFIR[6]
+ * Thermal (parity error)
+ */
+ (rNEST_LFIR, bit(6)) ? TBDDefaultCallout;
+
+ /** NEST_LFIR[7]
+ * Thermal (PCB error)
+ */
+ (rNEST_LFIR, bit(7)) ? TBDDefaultCallout;
+
+ /** NEST_LFIR[8]
+ * Thermal (critical trip error)
+ */
+ (rNEST_LFIR, bit(8)) ? TBDDefaultCallout;
+
+ /** NEST_LFIR[9]
+ * Thermal (fatal trip error)
+ */
+ (rNEST_LFIR, bit(9)) ? TBDDefaultCallout;
+
+ /** NEST_LFIR[10]
+ * Thermal (voltage trip error)
+ */
+ (rNEST_LFIR, bit(10)) ? TBDDefaultCallout;
+
+ /** NEST_LFIR[11:12]
+ * Trace Array ( error)
+ */
+ (rNEST_LFIR, bit(11|12)) ? TBDDefaultCallout;
+
+ /** NEST_LFIR[13:39]
+ * Reserved
+ */
+ (rNEST_LFIR, bit(13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? TBDDefaultCallout;
+
+ /** NEST_LFIR[40]
+ * malfunction alert (local xstop in another chiplet)
+ */
+ (rNEST_LFIR, bit(40)) ? TBDDefaultCallout;
+
+};
+
+################################################################################
+# Memory Buffer DMI FIR
+################################################################################
+
+rule rDMIFIR
+{
+ UNIT_CS:
+ DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & ~DMIFIR_ACT1;
+ RECOVERABLE:
+ DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & DMIFIR_ACT1;
+};
+
+group gDMIFIR filter singlebit
+{
+ /** DMIFIR[0]
+ * RX invalid state or parity error
+ */
+ (rDMIFIR, bit(0)) ? TBDDefaultCallout;
+
+ /** DMIFIR[1]
+ * TX invalid state or parity error
+ */
+ (rDMIFIR, bit(1)) ? TBDDefaultCallout;
+
+ /** DMIFIR[2]
+ * GCR hang error
+ */
+ (rDMIFIR, bit(2)) ? TBDDefaultCallout;
+
+ /** DMIFIR[3:7]
+ * Reserved
+ */
+ (rDMIFIR, bit(3|4|5|6|7)) ? TBDDefaultCallout;
+
+ /** DMIFIR[8]
+ * Training error
+ */
+ (rDMIFIR, bit(8)) ? TBDDefaultCallout;
+
+ /** DMIFIR[9]
+ * Spare lane deployed
+ */
+ (rDMIFIR, bit(9)) ? TBDDefaultCallout;
+
+ /** DMIFIR[10]
+ * Max spares exceeded
+ */
+ (rDMIFIR, bit(10)) ? TBDDefaultCallout;
+
+ /** DMIFIR[11]
+ * Recal or dynamic repair error
+ */
+ (rDMIFIR, bit(11)) ? TBDDefaultCallout;
+
+ /** DMIFIR[12]
+ * Too many bus errors
+ */
+ (rDMIFIR, bit(12)) ? TBDDefaultCallout;
+
+ /** DMIFIR[13:47]
+ * Reserved
+ */
+ (rDMIFIR, bit(13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40|41|42|43|44|45|46|47)) ? TBDDefaultCallout;
+
+ /** DMIFIR[48]
+ * SCOM FIR error
+ */
+ (rDMIFIR, bit(48)) ? TBDDefaultCallout;
+
+ /** DMIFIR[49]
+ * SCOM FIR error clone
+ */
+ (rDMIFIR, bit(49)) ? TBDDefaultCallout;
+
+};
+
+################################################################################
+# Memory Buffer MBI FIR
+################################################################################
+
+rule rMBIFIR
+{
+ UNIT_CS:
+ MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & ~MBIFIR_ACT1;
+ RECOVERABLE:
+ MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & MBIFIR_ACT1;
+};
+
+group gMBIFIR filter singlebit
+{
+ /** MBIFIR[0]
+ * Replay Timeout
+ */
+ (rMBIFIR, bit(0)) ? TBDDefaultCallout;
+
+ /** MBIFIR[1]
+ * CHANNEL_FAIL
+ */
+ (rMBIFIR, bit(1)) ? TBDDefaultCallout;
+
+ /** MBIFIR[2]
+ * CRC_ERROR
+ */
+ (rMBIFIR, bit(2)) ? TBDDefaultCallout;
+
+ /** MBIFIR[3]
+ * FRAME_NOACK
+ */
+ (rMBIFIR, bit(3)) ? TBDDefaultCallout;
+
+ /** MBIFIR[4]
+ * SEQID_OUT_OF_ORDER
+ */
+ (rMBIFIR, bit(4)) ? TBDDefaultCallout;
+
+ /** MBIFIR[5]
+ * REPLAY_BUFFER_ECC_CE
+ */
+ (rMBIFIR, bit(5)) ? TBDDefaultCallout;
+
+ /** MBIFIR[6]
+ * REPLAY_BUFFER_ECC_UE
+ */
+ (rMBIFIR, bit(6)) ? TBDDefaultCallout;
+
+ /** MBIFIR[7]
+ * MBI_STATE_MACHINE_TIMEOUT
+ */
+ (rMBIFIR, bit(7)) ? TBDDefaultCallout;
+
+ /** MBIFIR[8]
+ * MBI_INTERNAL_CONTROL_PARITY_ERROR
+ */
+ (rMBIFIR, bit(8)) ? TBDDefaultCallout;
+
+ /** MBIFIR[9]
+ * MBI_DATA_FLOW_PARITY_ERROR
+ */
+ (rMBIFIR, bit(9)) ? TBDDefaultCallout;
+
+ /** MBIFIR[10]
+ * CRC_PERFORMANCE_DEGRADATION
+ */
+ (rMBIFIR, bit(10)) ? TBDDefaultCallout;
+
+ /** MBIFIR[11]
+ * HOST_MC_GLOBAL_CHECKSTOP
+ */
+ (rMBIFIR, bit(11)) ? TBDDefaultCallout;
+
+ /** MBIFIR[12]
+ * HOST_MC_TRACESTOP
+ */
+ (rMBIFIR, bit(12)) ? TBDDefaultCallout;
+
+ /** MBIFIR[13]
+ * CHANNEL_INTERLOCK_FAIL
+ */
+ (rMBIFIR, bit(13)) ? TBDDefaultCallout;
+
+ /** MBIFIR[14]
+ * HOST_MC_LOCAL_CHECKSTOP
+ */
+ (rMBIFIR, bit(14)) ? TBDDefaultCallout;
+
+ /** MBIFIR[15]
+ * FRTL_COuNTER_OVERFLOW
+ */
+ (rMBIFIR, bit(15)) ? TBDDefaultCallout;
+
+ /** MBIFIR[16]
+ * SCOM_REGISTER_PARITY_ERROR
+ */
+ (rMBIFIR, bit(16)) ? TBDDefaultCallout;
+
+ /** MBIFIR[17]
+ * IO_FAULT: IO to MBI
+ */
+ (rMBIFIR, bit(17)) ? TBDDefaultCallout;
+
+ /** MBIFIR[18]
+ * MULTIPLE_REPLAY
+ */
+ (rMBIFIR, bit(18)) ? TBDDefaultCallout;
+
+ /** MBIFIR[19]
+ * MBICFG_PARITY_SCOM_ERROR
+ */
+ (rMBIFIR, bit(19)) ? TBDDefaultCallout;
+
+ /** MBIFIR[20]
+ * BUFFER_OVERRUN_ERROR
+ */
+ (rMBIFIR, bit(20)) ? TBDDefaultCallout;
+
+ /** MBIFIR[21]
+ * WAT_ERROR
+ */
+ (rMBIFIR, bit(21)) ? TBDDefaultCallout;
+
+ /** MBIFIR[22:24]
+ * Reserved
+ */
+ (rMBIFIR, bit(22|23|24)) ? TBDDefaultCallout;
+
+ /** MBIFIR[25]
+ * SCOM FIR error
+ */
+ (rMBIFIR, bit(25)) ? TBDDefaultCallout;
+
+ /** MBIFIR[26]
+ * SCOM FIR error clone
+ */
+ (rMBIFIR, bit(26)) ? TBDDefaultCallout;
+
+};
+
+################################################################################
+# Memory Buffer MBS FIR
+################################################################################
+
+rule rMBSFIR
+{
+ UNIT_CS:
+ MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 & ~MBSFIR_ACT1;
+ RECOVERABLE:
+ MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 & MBSFIR_ACT1;
+};
+
+group gMBSFIR filter singlebit
+{
+ /** MBSFIR[0]
+ * INT_PROTOCOL_ERROR
+ */
+ (rMBSFIR, bit(0)) ? TBDDefaultCallout;
+
+ /** MBSFIR[1]
+ * INVALID_ADDRESS_ERROR
+ */
+ (rMBSFIR, bit(1)) ? TBDDefaultCallout;
+
+ /** MBSFIR[2]
+ * INVALID_ADDRESS_ERROR
+ */
+ (rMBSFIR, bit(2)) ? TBDDefaultCallout;
+
+ /** MBSFIR[3]
+ * EXTERNAL_TIMEOUT
+ */
+ (rMBSFIR, bit(3)) ? TBDDefaultCallout;
+
+ /** MBSFIR[4]
+ * INTERNAL_TIMEOUT
+ */
+ (rMBSFIR, bit(4)) ? TBDDefaultCallout;
+
+ /** MBSFIR[5]
+ * INT_BUFFER_CE
+ */
+ (rMBSFIR, bit(5)) ? TBDDefaultCallout;
+
+ /** MBSFIR[6]
+ * INT_BUFFER_UE
+ */
+ (rMBSFIR, bit(6)) ? TBDDefaultCallout;
+
+ /** MBSFIR[7]
+ * INT_BUFFER_SUE
+ */
+ (rMBSFIR, bit(7)) ? TBDDefaultCallout;
+
+ /** MBSFIR[8]
+ * INT_PARITY_ERROR
+ */
+ (rMBSFIR, bit(8)) ? TBDDefaultCallout;
+
+ /** MBSFIR[9]
+ * CACHE_SRW_CE
+ */
+ (rMBSFIR, bit(9)) ? TBDDefaultCallout;
+
+ /** MBSFIR[10]
+ * CACHE_SRW_UE
+ */
+ (rMBSFIR, bit(10)) ? TBDDefaultCallout;
+
+ /** MBSFIR[11]
+ * CACHE_SRW_SUE
+ */
+ (rMBSFIR, bit(11)) ? TBDDefaultCallout;
+
+ /** MBSFIR[12]
+ * CACHE_CO_CE
+ */
+ (rMBSFIR, bit(12)) ? TBDDefaultCallout;
+
+ /** MBSFIR[13]
+ * CACHE_CO_UE
+ */
+ (rMBSFIR, bit(13)) ? TBDDefaultCallout;
+
+ /** MBSFIR[14]
+ * CACHE_CO_SUE
+ */
+ (rMBSFIR, bit(14)) ? TBDDefaultCallout;
+
+ /** MBSFIR[15]
+ * DIR_CE
+ */
+ (rMBSFIR, bit(15)) ? TBDDefaultCallout;
+
+ /** MBSFIR[16]
+ * DIR_UE
+ */
+ (rMBSFIR, bit(16)) ? TBDDefaultCallout;
+
+ /** MBSFIR[17]
+ * DIR_MEMBER_DELETED
+ */
+ (rMBSFIR, bit(17)) ? TBDDefaultCallout;
+
+ /** MBSFIR[18]
+ * DIR_ALL_MEMBERS_DELETED
+ */
+ (rMBSFIR, bit(18)) ? TBDDefaultCallout;
+
+ /** MBSFIR[19]
+ * LRU_ERROR
+ */
+ (rMBSFIR, bit(19)) ? TBDDefaultCallout;
+
+ /** MBSFIR[20]
+ * EDRAM_ERROR
+ */
+ (rMBSFIR, bit(20)) ? TBDDefaultCallout;
+
+ /** MBSFIR[21]
+ * EMERGENCY_THROTTLE_SET
+ */
+ (rMBSFIR, bit(21)) ? TBDDefaultCallout;
+
+ /** MBSFIR[22]
+ * HOST_INBAND_READ_ERROR
+ */
+ (rMBSFIR, bit(22)) ? TBDDefaultCallout;
+
+ /** MBSFIR[23]
+ * HOST_INBAND_WRITE_ERROR
+ */
+ (rMBSFIR, bit(23)) ? TBDDefaultCallout;
+
+ /** MBSFIR[24]
+ * OCC_INBAND_READ_ERROR
+ */
+ (rMBSFIR, bit(24)) ? TBDDefaultCallout;
+
+ /** MBSFIR[25]
+ * OCC_INBAND_WRITE_ERROR
+ */
+ (rMBSFIR, bit(25)) ? TBDDefaultCallout;
+
+ /** MBSFIR[26]
+ * SRB_BUFFER_CE
+ */
+ (rMBSFIR, bit(26)) ? TBDDefaultCallout;
+
+ /** MBSFIR[27]
+ * SRB_BUFFER_UE
+ */
+ (rMBSFIR, bit(27)) ? TBDDefaultCallout;
+
+ /** MBSFIR[28]
+ * SRB_BUFFER_SUE
+ */
+ (rMBSFIR, bit(28)) ? TBDDefaultCallout;
+
+ /** MBSFIR[29]
+ * SCOM FIR error
+ */
+ (rMBSFIR, bit(29)) ? TBDDefaultCallout; # CENTAUR_10
+
+ /** MBSFIR[30]
+ * PROXIMAL_CE_UE
+ */
+ (rMBSFIR, bit(30)) ? TBDDefaultCallout;
+
+ /** MBSFIR[31:32]
+ * Spare
+ */
+ (rMBSFIR, bit(31|32)) ? TBDDefaultCallout;
+
+ /** MBSFIR[33]
+ * SCOM FIR error
+ */
+ (rMBSFIR, bit(33)) ? TBDDefaultCallout;
+
+ /** MBSFIR[34]
+ * SCOM FIR error clone
+ */
+ (rMBSFIR, bit(34)) ? TBDDefaultCallout;
+
+};
+
+################################################################################
+# Memory Buffer MBS SECURE FIR
+################################################################################
+
+rule rMBSSECUREFIR
+{
+ UNIT_CS:
+ MBSSECUREFIR;
+};
+
+group gMBSSECUREFIR filter singlebit
+{
+ /** MBSSECUREFIR[0]
+ * INVALID_MBSXCR_ACCESS
+ */
+ (rMBSSECUREFIR, bit(0)) ? TBDDefaultCallout;
+
+ /** MBSSECUREFIR[1]
+ * INVALID_MBAXCR01_ACCESS
+ */
+ (rMBSSECUREFIR, bit(1)) ? TBDDefaultCallout;
+
+ /** MBSSECUREFIR[2]
+ * INVALID_MBAXCR23_ACCESS
+ */
+ (rMBSSECUREFIR, bit(2)) ? TBDDefaultCallout;
+
+ /** MBSSECUREFIR[3]
+ * INVALID_MBAXCRMS_ACCRESS
+ */
+ (rMBSSECUREFIR, bit(3)) ? TBDDefaultCallout;
+
+ /** MBSSECUREFIR[4]
+ * Spare
+ */
+ (rMBSSECUREFIR, bit(4)) ? TBDDefaultCallout;
+
+ /** MBSSECUREFIR[5]
+ * INVALID_SIR_MASK_OR_ACTION_REGISTER_ACCESS
+ */
+ (rMBSSECUREFIR, bit(5)) ? TBDDefaultCallout;
+
+};
+
+################################################################################
+# Memory Buffer MBS ECC FIR 0
+################################################################################
+
+rule rMBSECCFIR_0
+{
+ UNIT_CS:
+ MBSECCFIR_0 & ~MBSECCFIR_0_MASK & ~MBSECCFIR_0_ACT0 & ~MBSECCFIR_0_ACT1;
+ RECOVERABLE:
+ MBSECCFIR_0 & ~MBSECCFIR_0_MASK & ~MBSECCFIR_0_ACT0 & MBSECCFIR_0_ACT1;
+};
+
+group gMBSECCFIR_0 filter singlebit
+{
+ /** MBSECCFIR_0[0]
+ * Memory chip mark on rank 0
+ */
+ (rMBSECCFIR_0, bit(0)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[1]
+ * Memory chip mark on rank 1
+ */
+ (rMBSECCFIR_0, bit(1)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[2]
+ * Memory chip mark on rank 2
+ */
+ (rMBSECCFIR_0, bit(2)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[3]
+ * Memory chip mark on rank 3
+ */
+ (rMBSECCFIR_0, bit(3)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[4]
+ * Memory chip mark on rank 4
+ */
+ (rMBSECCFIR_0, bit(4)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[5]
+ * Memory chip mark on rank 5
+ */
+ (rMBSECCFIR_0, bit(5)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[6]
+ * Memory chip mark on rank 6
+ */
+ (rMBSECCFIR_0, bit(6)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[7]
+ * Memory chip mark on rank 7
+ */
+ (rMBSECCFIR_0, bit(7)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[8:15]
+ * Reserved
+ */
+ (rMBSECCFIR_0, bit(8|9|10|11|12|13|14|15)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[16]
+ * Memory NCE
+ */
+ (rMBSECCFIR_0, bit(16)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[17]
+ * Memory RCE
+ */
+ (rMBSECCFIR_0, bit(17)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[18]
+ * Memory SUE
+ */
+ (rMBSECCFIR_0, bit(18)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[19]
+ * Memory UE
+ */
+ (rMBSECCFIR_0, bit(19)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[20:27]
+ * Maintenance chip mark
+ */
+ (rMBSECCFIR_0, bit(20|21|22|23|24|25|26|27)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[28:35]
+ * Reserved
+ */
+ (rMBSECCFIR_0, bit(28|29|30|31|32|33|34|35)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[36]
+ * Maintenance NCE
+ */
+ (rMBSECCFIR_0, bit(36)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[37]
+ * Maintenance SCE
+ */
+ (rMBSECCFIR_0, bit(37)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[38]
+ * Maintenance MCE
+ */
+ (rMBSECCFIR_0, bit(38)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[39]
+ * Maintenance RCE
+ */
+ (rMBSECCFIR_0, bit(39)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[40]
+ * Maintenance SUE
+ */
+ (rMBSECCFIR_0, bit(40)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[41]
+ * Maintenance UE
+ */
+ (rMBSECCFIR_0, bit(41)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[42]
+ * MPE during use maintenance mark mode
+ */
+ (rMBSECCFIR_0, bit(42)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[43]
+ * Prefetch Memory UE
+ */
+ (rMBSECCFIR_0, bit(43)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[44]
+ * Memory RCD parity error
+ */
+ (rMBSECCFIR_0, bit(44)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[45]
+ * Maintenance RCD parity error
+ */
+ (rMBSECCFIR_0, bit(45)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[46]
+ * Recoverable configuration register parity error
+ */
+ (rMBSECCFIR_0, bit(46)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[47]
+ * Unrecoverable configuration register parity error
+ */
+ (rMBSECCFIR_0, bit(47)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[48]
+ * Maskable configuration register parity error
+ */
+ (rMBSECCFIR_0, bit(48)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[49]
+ * ECC datapath parity error
+ */
+ (rMBSECCFIR_0, bit(49)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[50]
+ * Internal Scom Error
+ */
+ (rMBSECCFIR_0, bit(50)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_0[51]
+ * SCOM FIR error clone
+ */
+ (rMBSECCFIR_0, bit(51)) ? TBDDefaultCallout;
+
+};
+
+################################################################################
+# Memory Buffer MBS ECC FIR 1
+################################################################################
+
+rule rMBSECCFIR_1
+{
+ UNIT_CS:
+ MBSECCFIR_1 & ~MBSECCFIR_1_MASK & ~MBSECCFIR_1_ACT0 & ~MBSECCFIR_1_ACT1;
+ RECOVERABLE:
+ MBSECCFIR_1 & ~MBSECCFIR_1_MASK & ~MBSECCFIR_1_ACT0 & MBSECCFIR_1_ACT1;
+};
+
+group gMBSECCFIR_1 filter singlebit
+{
+ /** MBSECCFIR_1[0]
+ * Memory chip mark on rank 0
+ */
+ (rMBSECCFIR_1, bit(0)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[1]
+ * Memory chip mark on rank 1
+ */
+ (rMBSECCFIR_1, bit(1)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[2]
+ * Memory chip mark on rank 2
+ */
+ (rMBSECCFIR_1, bit(2)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[3]
+ * Memory chip mark on rank 3
+ */
+ (rMBSECCFIR_1, bit(3)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[4]
+ * Memory chip mark on rank 4
+ */
+ (rMBSECCFIR_1, bit(4)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[5]
+ * Memory chip mark on rank 5
+ */
+ (rMBSECCFIR_1, bit(5)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[6]
+ * Memory chip mark on rank 6
+ */
+ (rMBSECCFIR_1, bit(6)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[7]
+ * Memory chip mark on rank 7
+ */
+ (rMBSECCFIR_1, bit(7)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[8:15]
+ * Reserved
+ */
+ (rMBSECCFIR_1, bit(8|9|10|11|12|13|14|15)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[16]
+ * Memory NCE
+ */
+ (rMBSECCFIR_1, bit(16)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[17]
+ * Memory RCE
+ */
+ (rMBSECCFIR_1, bit(17)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[18]
+ * Memory SUE
+ */
+ (rMBSECCFIR_1, bit(18)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[19]
+ * Memory UE
+ */
+ (rMBSECCFIR_1, bit(19)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[20:27]
+ * Maintenance chip mark
+ */
+ (rMBSECCFIR_1, bit(20|21|22|23|24|25|26|27)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[28:35]
+ * Reserved
+ */
+ (rMBSECCFIR_1, bit(28|29|30|31|32|33|34|35)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[36]
+ * Maintenance NCE
+ */
+ (rMBSECCFIR_1, bit(36)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[37]
+ * Maintenance SCE
+ */
+ (rMBSECCFIR_1, bit(37)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[38]
+ * Maintenance MCE
+ */
+ (rMBSECCFIR_1, bit(38)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[39]
+ * Maintenance RCE
+ */
+ (rMBSECCFIR_1, bit(39)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[40]
+ * Maintenance SUE
+ */
+ (rMBSECCFIR_1, bit(40)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[41]
+ * Maintenance UE
+ */
+ (rMBSECCFIR_1, bit(41)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[42]
+ * MPE during use maintenance mark mode
+ */
+ (rMBSECCFIR_1, bit(42)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[43]
+ * Prefetch Memory UE
+ */
+ (rMBSECCFIR_1, bit(43)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[44]
+ * Memory RCD parity error
+ */
+ (rMBSECCFIR_1, bit(44)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[45]
+ * Maintenance RCD parity error
+ */
+ (rMBSECCFIR_1, bit(45)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[46]
+ * Recoverable configuration register parity error
+ */
+ (rMBSECCFIR_1, bit(46)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[47]
+ * Unrecoverable configuration register parity error
+ */
+ (rMBSECCFIR_1, bit(47)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[48]
+ * Maskable configuration register parity error
+ */
+ (rMBSECCFIR_1, bit(48)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[49]
+ * ECC datapath parity error
+ */
+ (rMBSECCFIR_1, bit(49)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[50]
+ * Internal Scom Error
+ */
+ (rMBSECCFIR_1, bit(50)) ? TBDDefaultCallout;
+
+ /** MBSECCFIR_1[51]
+ * SCOM FIR error clone
+ */
+ (rMBSECCFIR_1, bit(51)) ? TBDDefaultCallout;
+
+};
+
+################################################################################
+# Memory Buffer SCAC FIR
+################################################################################
+
+rule rSCACFIR
+{
+ UNIT_CS:
+ SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 & ~SCACFIR_ACT1;
+ RECOVERABLE:
+ SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 & SCACFIR_ACT1;
+};
+
+group gSCACFIR filter singlebit
+{
+ /** SCACFIR[0]
+ * I2CM(0) Invalid Address
+ */
+ (rSCACFIR, bit(0)) ? TBDDefaultCallout;
+
+ /** SCACFIR[1]
+ * I2CM(1) Invalid Write
+ */
+ (rSCACFIR, bit(1)) ? TBDDefaultCallout;
+
+ /** SCACFIR[2]
+ * I2CM(2) Invalid Read
+ */
+ (rSCACFIR, bit(2)) ? TBDDefaultCallout;
+
+ /** SCACFIR[3]
+ * I2CM(3) Pib Address Parity Error
+ */
+ (rSCACFIR, bit(3)) ? TBDDefaultCallout;
+
+ /** SCACFIR[4]
+ * I2CM(4) Pib Parity Error
+ */
+ (rSCACFIR, bit(4)) ? TBDDefaultCallout;
+
+ /** SCACFIR[5]
+ * I2CM(5) LB parity error
+ */
+ (rSCACFIR, bit(5)) ? TBDDefaultCallout;
+
+ /** SCACFIR[6:9]
+ * Reserved at 0 for external macro expansion reporting.
+ */
+ (rSCACFIR, bit(6|7|8|9)) ? TBDDefaultCallout;
+
+ /** SCACFIR[10]
+ * I2CM(45) : Invalid Command
+ */
+ (rSCACFIR, bit(10)) ? TBDDefaultCallout;
+
+ /** SCACFIR[11]
+ * I2CM(46) : Parity Error
+ */
+ (rSCACFIR, bit(11)) ? TBDDefaultCallout;
+
+ /** SCACFIR[12]
+ * I2CM(47): Backend Overrun Error
+ */
+ (rSCACFIR, bit(12)) ? TBDDefaultCallout;
+
+ /** SCACFIR[13]
+ * I2CM(48): Backend Access Error
+ */
+ (rSCACFIR, bit(13)) ? TBDDefaultCallout;
+
+ /** SCACFIR[14]
+ * I2CM(49): Arbitration Lost Error
+ */
+ (rSCACFIR, bit(14)) ? TBDDefaultCallout;
+
+ /** SCACFIR[15]
+ * I2CM(50): Nack Received Error
+ */
+ (rSCACFIR, bit(15)) ? TBDDefaultCallout;
+
+ /** SCACFIR[16]
+ * I2CM(53): Stop Error
+ */
+ (rSCACFIR, bit(16)) ? TBDDefaultCallout;
+
+ /** SCACFIR[17]
+ * Local PIB Response code 1
+ */
+ (rSCACFIR, bit(17)) ? TBDDefaultCallout;
+
+ /** SCACFIR[18]
+ * Local PIB Response code 2
+ */
+ (rSCACFIR, bit(18)) ? TBDDefaultCallout;
+
+ /** SCACFIR[19]
+ * Local PIB Response code 3
+ */
+ (rSCACFIR, bit(19)) ? TBDDefaultCallout;
+
+ /** SCACFIR[20]
+ * Local PIB Response code 4
+ */
+ (rSCACFIR, bit(20)) ? TBDDefaultCallout;
+
+ /** SCACFIR[21]
+ * Local PIB Response code 5
+ */
+ (rSCACFIR, bit(21)) ? TBDDefaultCallout;
+
+ /** SCACFIR[22]
+ * Local PIB Response code 6
+ */
+ (rSCACFIR, bit(22)) ? TBDDefaultCallout;
+
+ /** SCACFIR[23]
+ * Local PIB Response code 7
+ */
+ (rSCACFIR, bit(23)) ? TBDDefaultCallout;
+
+ /** SCACFIR[24]
+ * Stall Threshold Error
+ */
+ (rSCACFIR, bit(24)) ? TBDDefaultCallout;
+
+ /** SCACFIR[25]
+ * Parity Error on Internal Register
+ */
+ (rSCACFIR, bit(25)) ? TBDDefaultCallout;
+
+ /** SCACFIR[26]
+ * Parity Error on Pib Target Register
+ */
+ (rSCACFIR, bit(26)) ? TBDDefaultCallout;
+
+ /** SCACFIR[27:31]
+ * Reserved
+ */
+ (rSCACFIR, bit(27|28|29|30|31)) ? TBDDefaultCallout;
+
+ /** SCACFIR[32]
+ * State Machine / Ctrl Logic Error
+ */
+ (rSCACFIR, bit(32)) ? TBDDefaultCallout;
+
+ /** SCACFIR[33]
+ * Register access error
+ */
+ (rSCACFIR, bit(33)) ? TBDDefaultCallout;
+
+ /** SCACFIR[34]
+ * Reset command error
+ */
+ (rSCACFIR, bit(34)) ? TBDDefaultCallout;
+
+ /** SCACFIR[35]
+ * SCOM FIR error
+ */
+ (rSCACFIR, bit(35)) ? TBDDefaultCallout;
+
+ /** SCACFIR[36]
+ * SCOM FIR error clone
+ */
+ (rSCACFIR, bit(36)) ? TBDDefaultCallout;
+
+};
+
+################################################################################
+# Memory Buffer MCBIST FIR 0
+################################################################################
+
+rule rMCBISTFIR_0
+{
+ UNIT_CS:
+ MCBISTFIR_0 & ~MCBISTFIR_0_MASK & ~MCBISTFIR_0_ACT0 & ~MCBISTFIR_0_ACT1;
+ RECOVERABLE:
+ MCBISTFIR_0 & ~MCBISTFIR_0_MASK & ~MCBISTFIR_0_ACT0 & MCBISTFIR_0_ACT1;
+};
+
+group gMCBISTFIR_0 filter singlebit
+{
+ /** MCBISTFIR_0[0]
+ * SCOM Parity Errors
+ */
+ (rMCBISTFIR_0, bit(0)) ? TBDDefaultCallout;
+
+ /** MCBISTFIR_0[1]
+ * MBX parity errors
+ */
+ (rMCBISTFIR_0, bit(1)) ? TBDDefaultCallout;
+
+ /** MCBISTFIR_0[2]
+ * DRAM event 0 error
+ */
+ (rMCBISTFIR_0, bit(2)) ? TBDDefaultCallout;
+
+ /** MCBISTFIR_0[3]
+ * DRAM event 1 error
+ */
+ (rMCBISTFIR_0, bit(3)) ? TBDDefaultCallout;
+
+ /** MCBISTFIR_0[4:14]
+ * Reserved
+ */
+ (rMCBISTFIR_0, bit(4|5|6|7|8|9|10|11|12|13|14)) ? TBDDefaultCallout;
+
+ /** MCBISTFIR_0[15]
+ * SCOM FIR error
+ */
+ (rMCBISTFIR_0, bit(15)) ? TBDDefaultCallout;
+
+ /** MCBISTFIR_0[16]
+ * SCOM FIR error clone
+ */
+ (rMCBISTFIR_0, bit(16)) ? TBDDefaultCallout;
+
+};
+
+################################################################################
+# Memory Buffer MCBIST FIR 1
+################################################################################
+
+rule rMCBISTFIR_1
+{
+ UNIT_CS:
+ MCBISTFIR_1 & ~MCBISTFIR_1_MASK & ~MCBISTFIR_1_ACT0 & ~MCBISTFIR_1_ACT1;
+ RECOVERABLE:
+ MCBISTFIR_1 & ~MCBISTFIR_1_MASK & ~MCBISTFIR_1_ACT0 & MCBISTFIR_1_ACT1;
+};
+
+group gMCBISTFIR_1 filter singlebit
+{
+ /** MCBISTFIR_1[0]
+ * SCOM Parity Errors
+ */
+ (rMCBISTFIR_1, bit(0)) ? TBDDefaultCallout;
+
+ /** MCBISTFIR_1[1]
+ * MBX parity errors
+ */
+ (rMCBISTFIR_1, bit(1)) ? TBDDefaultCallout;
+
+ /** MCBISTFIR_1[2]
+ * DRAM event 0 error
+ */
+ (rMCBISTFIR_1, bit(2)) ? TBDDefaultCallout;
+
+ /** MCBISTFIR_1[3]
+ * DRAM event 1 error
+ */
+ (rMCBISTFIR_1, bit(3)) ? TBDDefaultCallout;
+
+ /** MCBISTFIR_1[4:14]
+ * Reserved
+ */
+ (rMCBISTFIR_1, bit(4|5|6|7|8|9|10|11|12|13|14)) ? TBDDefaultCallout;
+
+ /** MCBISTFIR_1[15]
+ * SCOM FIR error
+ */
+ (rMCBISTFIR_1, bit(15)) ? TBDDefaultCallout;
+
+ /** MCBISTFIR_1[16]
+ * SCOM FIR error clone
+ */
+ (rMCBISTFIR_1, bit(16)) ? TBDDefaultCallout;
+
+};
+
+################################################################################
+# MEM Chiplet FIR
+################################################################################
+
+rule rMEM_CHIPLET_FIR
+{
+ UNIT_CS:
+ MEM_CHIPLET_CS_FIR & ~MEM_CHIPLET_FIR_MASK & `1fffffffffffffff`;
+ RECOVERABLE:
+ (MEM_CHIPLET_RE_FIR >> 2) & ~MEM_CHIPLET_FIR_MASK & `1fffffffffffffff`;
+};
+
+group gMEM_CHIPLET_FIR filter singlebit
+{
+ /** MEM_CHIPLET_FIR[3]
+ * Attention from MEM_LFIR
+ */
+ (rMEM_CHIPLET_FIR, bit(3)) ? analyze(gMEM_LFIR);
+
+ /** MEM_CHIPLET_FIR[5]
+ * Attention from MBACALFIR 0
+ */
+ (rMEM_CHIPLET_FIR, bit(5)) ? analyzeConnectedMBA0;
+
+ /** MEM_CHIPLET_FIR[6]
+ * Attention from MBAFIR 0
+ */
+ (rMEM_CHIPLET_FIR, bit(6)) ? analyzeConnectedMBA0;
+
+ /** MEM_CHIPLET_FIR[7]
+ * Attention from MBACALFIR 1
+ */
+ (rMEM_CHIPLET_FIR, bit(7)) ? analyzeConnectedMBA1;
+
+ /** MEM_CHIPLET_FIR[8]
+ * Attention from MBAFIR 1
+ */
+ (rMEM_CHIPLET_FIR, bit(8)) ? analyzeConnectedMBA1;
+
+ /** MEM_CHIPLET_FIR[9]
+ * Attention from MBADDRPHYFIR 0
+ */
+ (rMEM_CHIPLET_FIR, bit(9)) ? analyzeConnectedMBA0;
+
+ /** MEM_CHIPLET_FIR[10]
+ * Attention from MBADDRPHYFIR 1
+ */
+ (rMEM_CHIPLET_FIR, bit(10)) ? analyzeConnectedMBA1;
+
+ /** MEM_CHIPLET_FIR[12]
+ * Attention from MBASECUREFIR 0
+ */
+ (rMEM_CHIPLET_FIR, bit(12)) ? analyzeConnectedMBA0;
+
+ /** MEM_CHIPLET_FIR[13]
+ * Attention from MBASECUREFIR 1
+ */
+ (rMEM_CHIPLET_FIR, bit(13)) ? analyzeConnectedMBA1;
+
+};
+
+################################################################################
+# MEM Chiplet Special Attention FIR
+################################################################################
+
+rule rMEM_CHIPLET_SPA_FIR
+{
+ HOST_ATTN:
+ MEM_CHIPLET_SPA_FIR & ~MEM_CHIPLET_SPA_FIR_MASK;
+};
+
+group gMEM_CHIPLET_SPA_FIR filter singlebit
+{
+ /** MEM_CHIPLET_SPA_FIR[0]
+ * Attention from MBASPA 0
+ */
+ (rMEM_CHIPLET_SPA_FIR, bit(0)) ? analyzeConnectedMBA0;
+
+ /** MEM_CHIPLET_SPA_FIR[1]
+ * Attention from MBASPA 1
+ */
+ (rMEM_CHIPLET_SPA_FIR, bit(1)) ? analyzeConnectedMBA1;
+
+};
+
+################################################################################
+# MEM chiplet pervasive FIR
+################################################################################
+
+rule rMEM_LFIR
+{
+ UNIT_CS:
+ MEM_LFIR & ~MEM_LFIR_MASK & ~MEM_LFIR_ACT0 & ~MEM_LFIR_ACT1;
+ RECOVERABLE:
+ MEM_LFIR & ~MEM_LFIR_MASK & ~MEM_LFIR_ACT0 & MEM_LFIR_ACT1;
+};
+
+group gMEM_LFIR filter singlebit
+{
+ /** MEM_LFIR[0]
+ * CFIR internal parity error
+ */
+ (rMEM_LFIR, bit(0)) ? TBDDefaultCallout;
+
+ /** MEM_LFIR[1]
+ * GPIO (PCB error)
+ */
+ (rMEM_LFIR, bit(1)) ? TBDDefaultCallout;
+
+ /** MEM_LFIR[2]
+ * CC (PCB error)
+ */
+ (rMEM_LFIR, bit(2)) ? TBDDefaultCallout;
+
+ /** MEM_LFIR[3]
+ * CC (OPCG, parity, scan collision, ...)
+ */
+ (rMEM_LFIR, bit(3)) ? TBDDefaultCallout;
+
+ /** MEM_LFIR[4]
+ * PSC (PCB error)
+ */
+ (rMEM_LFIR, bit(4)) ? TBDDefaultCallout;
+
+ /** MEM_LFIR[5]
+ * PSC (parity error)
+ */
+ (rMEM_LFIR, bit(5)) ? TBDDefaultCallout;
+
+ /** MEM_LFIR[6]
+ * Thermal (parity error)
+ */
+ (rMEM_LFIR, bit(6)) ? TBDDefaultCallout;
+
+ /** MEM_LFIR[7]
+ * Thermal (PCB error)
+ */
+ (rMEM_LFIR, bit(7)) ? TBDDefaultCallout;
+
+ /** MEM_LFIR[8]
+ * Thermal (critical trip error)
+ */
+ (rMEM_LFIR, bit(8)) ? TBDDefaultCallout;
+
+ /** MEM_LFIR[9]
+ * Thermal (fatal trip error)
+ */
+ (rMEM_LFIR, bit(9)) ? TBDDefaultCallout;
+
+ /** MEM_LFIR[10]
+ * Thermal (voltage trip error)
+ */
+ (rMEM_LFIR, bit(10)) ? TBDDefaultCallout;
+
+ /** MEM_LFIR[11:12]
+ * MBA01 Trace Array ( error)
+ */
+ (rMEM_LFIR, bit(11|12)) ? TBDDefaultCallout;
+
+ /** MEM_LFIR[13:14]
+ * MBA23 Trace Array ( error)
+ */
+ (rMEM_LFIR, bit(13|14)) ? TBDDefaultCallout;
+
+ /** MEM_LFIR[15:39]
+ * Reserved
+ */
+ (rMEM_LFIR, bit(15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? TBDDefaultCallout;
+
+ /** MEM_LFIR[40]
+ * malfunction alert (local xstop in another chiplet)
+ */
+ (rMEM_LFIR, bit(40)) ? TBDDefaultCallout;
+
+};
+
+ ##############################################################################
+ # #
+ # # ### #
+ # # # ## ##### ### ### # # # # # # ### ### ### ### #
+ # # # # # # # # # ## # # # # # # # # # #
+ # ####### # # # # # # # # # # ##### ### ### ## ### #
+ # # # # # # # # # # ## # # # # # # # # # #
+ # # # ## # ### ### # # ### ### # # ### ### ### ### #
+ # #
+ ##############################################################################
+
+# Include the common action set.
+.include "cen_common_actions.rule";
+# Include the chip-specific action set.
+.include "cen_centaur_actions.rule";
+
+actionclass analyzeConnectedMBA0 { analyze(connected(TYPE_MBA, 0)); };
+actionclass analyzeConnectedMBA1 { analyze(connected(TYPE_MBA, 1)); };
diff --git a/src/usr/diag/prdf/common/plat/cen/cen_common_actions.rule b/src/usr/diag/prdf/common/plat/cen/cen_common_actions.rule
new file mode 100644
index 000000000..8c6a3f1cb
--- /dev/null
+++ b/src/usr/diag/prdf/common/plat/cen/cen_common_actions.rule
@@ -0,0 +1,131 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/usr/diag/prdf/common/plat/cen/cen_common_actions.rule $
+#
+# OpenPOWER HostBoot Project
+#
+# Contributors Listed Below - COPYRIGHT 2017
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+################################################################################
+# This file is intended to create a common set of actionclasses for all rule
+# files.
+#
+# NOTE: THESE ACTIONCLASSES WILL BE CREATED FOR ALL RULE FILES, REGARDLESS IF
+# THEY ARE ACTUALLY USED. PLEASE LIMIT THIS FILE TO RELATIVELY COMMON
+# ACTIONS. OTHERWISE, IT WILL CAUSE UNWANTED CODE BLOAT AND MEMORY USAGE.
+#
+# Simply add the following line at the top the actionclass section of each rule
+# file:
+#
+# .include "cen_common_actions.rule"
+#
+# Note that no indentation can be used for the .include keyword.
+################################################################################
+
+################################################################################
+# Thresholds #
+################################################################################
+
+# Threshold syntax:
+# threshold( field(<timebase>) [, mfg(<timebase>)|mfg_file(<mfg_theshold>)] );
+#
+# Timebase syntax:
+# <threshold_count> [/ [timbase_count] <sec|min|hour|day>]
+#
+# Note that <mfg_theshold> can be found in prdfMfgThresholds.lst
+#
+# Examples:
+# threshold( field( 1 ) );
+# threshold( field(32 / day) );
+# threshold( field( 5 / 2 min) );
+# threshold( field(32 / 1 day), mfg(2 / hour) );
+# threshold( field( 2 / min), mfg(1 ) );
+# threshold( field(32 / day), mfg_file(P8CHIP_OFFNODE_BUS_CES) );
+
+/** Threshold of 1 */
+actionclass threshold1
+{
+ threshold( field(1) );
+};
+
+/** Threshold of 32 per day */
+actionclass threshold32pday
+{
+ threshold( field(32 / day) );
+};
+
+################################################################################
+# Threshold and Mask policy
+################################################################################
+
+/**
+ * Threshold 32/day (field) and 1 (mnfg). Do not predictively callout on
+ * threshold in the field, instead just mask.
+ */
+actionclass threshold_and_mask
+{
+ threshold32pday;
+ funccall("ClearServiceCallFlag");
+};
+
+actionclass threshold_and_mask_self { calloutSelfMed; threshold_and_mask; };
+
+################################################################################
+# Special Flags #
+################################################################################
+
+/** SUE source */
+actionclass SueSource { flag(UERE); };
+
+/** SUE originated from somewhere else */
+actionclass SueSeen { flag(SUE); };
+
+################################################################################
+# Simple Callouts #
+################################################################################
+
+# Callout self
+actionclass calloutSelfHigh { callout(MRU_HIGH); };
+actionclass calloutSelfMed { callout(MRU_MED); };
+actionclass calloutSelfMedA { callout(MRU_MEDA); };
+actionclass calloutSelfLow { callout(MRU_LOW); };
+
+# 2nd Level Support
+actionclass callout2ndLvlMed
+{ callout(procedure(LEVEL2_SUPPORT), MRU_MED); };
+
+################################################################################
+# Default callouts #
+################################################################################
+
+/** Default action for an unexpected unmasked bit */
+actionclass defaultMaskedError
+{
+ callout2ndLvlMed;
+ threshold1;
+};
+
+/** Default TBD action */
+actionclass TBDDefaultCallout
+{
+ callout2ndLvlMed;
+ threshold( field(32 / day), mfg(32 / day) );
+};
+
diff --git a/src/usr/diag/prdf/common/plat/cen/cen_mba.rule b/src/usr/diag/prdf/common/plat/cen/cen_mba.rule
new file mode 100644
index 000000000..3ef6b246e
--- /dev/null
+++ b/src/usr/diag/prdf/common/plat/cen/cen_mba.rule
@@ -0,0 +1,661 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/usr/diag/prdf/common/plat/cen/cen_mba.rule $
+#
+# OpenPOWER HostBoot Project
+#
+# Contributors Listed Below - COPYRIGHT 2012,2017
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+chip cen_mba
+{
+ name "Centaur MBA chiplet";
+ targettype TYPE_MBA;
+ sigoff 0x9000;
+ dump DUMP_CONTENT_HW;
+ scomlen 64;
+
+ #############################################################################
+ # #
+ # ###### #
+ # # # ###### #### ### #### ##### ###### ##### #### #
+ # # # # # # # # # # # # # #
+ # ###### ##### # # #### # ##### # # #### #
+ # # # # # ### # # # # ##### # #
+ # # # # # # # # # # # # # # # #
+ # # # ###### #### ### #### # ###### # # #### #
+ # #
+ #############################################################################
+
+ ############################################################################
+ # Memory Buffer MBA CAL FIR
+ ############################################################################
+
+ register MBACALFIR
+ {
+ name "Memory Buffer MBA CAL FIR";
+ scomaddr 0x03010400;
+ reset (&, 0x03010401);
+ mask (|, 0x03010405);
+ capture group default;
+ };
+
+ register MBACALFIR_MASK
+ {
+ name "Memory Buffer MBA CAL FIR MASK";
+ scomaddr 0x03010403;
+ capture group default;
+ };
+
+ register MBACALFIR_ACT0
+ {
+ name "Memory Buffer MBA CAL FIR ACT0";
+ scomaddr 0x03010406;
+ capture group default;
+ capture req nonzero("MBACALFIR");
+ };
+
+ register MBACALFIR_ACT1
+ {
+ name "Memory Buffer MBA CAL FIR ACT1";
+ scomaddr 0x03010407;
+ capture group default;
+ capture req nonzero("MBACALFIR");
+ };
+
+ ############################################################################
+ # Memory Buffer MBA SECURE FIR
+ ############################################################################
+
+ # This register is hardwired to channel failure (checkstop) and we cannot
+ # mask or change the state of the action registers.
+ register MBASECUREFIR
+ {
+ name "Memory Buffer MBA SECURE FIR";
+ scomaddr 0x0301041b;
+ reset (&, 0x0301041c);
+ capture group default;
+ };
+
+ ############################################################################
+ # Memory Buffer MBA FIR
+ ############################################################################
+
+ register MBAFIR
+ {
+ name "Memory Buffer MBA FIR";
+ scomaddr 0x03010600;
+ reset (&, 0x03010601);
+ mask (|, 0x03010605);
+ capture group default;
+ };
+
+ register MBAFIR_MASK
+ {
+ name "Memory Buffer MBA FIR MASK";
+ scomaddr 0x03010603;
+ capture group default;
+ };
+
+ register MBAFIR_ACT0
+ {
+ name "Memory Buffer MBA FIR ACT0";
+ scomaddr 0x03010606;
+ capture group default;
+ capture req nonzero("MBAFIR");
+ };
+
+ register MBAFIR_ACT1
+ {
+ name "Memory Buffer MBA FIR ACT1";
+ scomaddr 0x03010607;
+ capture group default;
+ capture req nonzero("MBAFIR");
+ };
+
+ ############################################################################
+ # Memory Buffer MBA SPA register
+ ############################################################################
+
+ register MBASPA
+ {
+ name "Memory Buffer MBA SPA register";
+ scomaddr 0x03010611;
+ reset (&, 0x03010612);
+ mask (|, 0x03010614);
+ capture group default;
+ };
+
+ register MBASPA_MASK
+ {
+ name "Memory Buffer MBA SPA register MASK";
+ scomaddr 0x03010614;
+ capture group default;
+ };
+
+ ############################################################################
+ # Memory Buffer MBA DDR PHY FIR
+ ############################################################################
+
+ register MBADDRPHYFIR
+ {
+ name "Memory Buffer MBA DDR PHY FIR";
+ scomaddr 0x800200900301143F;
+ reset (&, 0x800200910301143F);
+ mask (|, 0x800200950301143F);
+ capture group default;
+ };
+
+ register MBADDRPHYFIR_MASK
+ {
+ name "Memory Buffer MBA DDR PHY FIR MASK";
+ scomaddr 0x800200930301143F;
+ capture group default;
+ };
+
+ register MBADDRPHYFIR_ACT0
+ {
+ name "Memory Buffer MBA DDR PHY FIR ACT0";
+ scomaddr 0x800200960301143F;
+ capture group default;
+ capture req nonzero("MBADDRPHYFIR");
+ };
+
+ register MBADDRPHYFIR_ACT1
+ {
+ name "Memory Buffer MBA DDR PHY FIR ACT1";
+ scomaddr 0x800200970301143F;
+ capture group default;
+ capture req nonzero("MBADDRPHYFIR");
+ };
+
+# Include registers not defined by the xml
+.include "cen_mba_regs.rule";
+
+};
+
+ ##############################################################################
+ # #
+ # #### # #
+ # # # # # # ##### ### # # # ## ##### ### ### # # ### #
+ # # # # # # # # # # # # # # # # # ## # # #
+ # #### # # # #### ### # ####### # # # # # # # # ### #
+ # # # # # # # # # # # # # # # # # # ## # #
+ # # # ### #### ##### ### # # # ## # ### ### # # ### #
+ # #
+ ##############################################################################
+
+################################################################################
+# Summary for MBA
+################################################################################
+
+rule rMBA
+{
+ UNIT_CS:
+ summary( 0, rMBACALFIR ) |
+ summary( 1, rMBASECUREFIR ) |
+ summary( 2, rMBAFIR ) |
+ summary( 3, rMBADDRPHYFIR );
+
+ RECOVERABLE:
+ summary( 0, rMBACALFIR ) |
+ summary( 1, rMBASECUREFIR ) |
+ summary( 2, rMBAFIR ) |
+ summary( 3, rMBADDRPHYFIR );
+
+ HOST_ATTN:
+ summary( 4, rMBASPA );
+};
+
+group gMBA attntype UNIT_CS, RECOVERABLE, HOST_ATTN filter singlebit
+{
+ (rMBA, bit(0)) ? analyze(gMBACALFIR);
+ (rMBA, bit(1)) ? analyze(gMBASECUREFIR);
+ (rMBA, bit(2)) ? analyze(gMBAFIR);
+ (rMBA, bit(3)) ? analyze(gMBADDRPHYFIR);
+ (rMBA, bit(4)) ? analyze(gMBASPA);
+};
+
+################################################################################
+# Memory Buffer MBA CAL FIR
+################################################################################
+
+rule rMBACALFIR
+{
+ UNIT_CS:
+ MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 & ~MBACALFIR_ACT1;
+ RECOVERABLE:
+ MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 & MBACALFIR_ACT1;
+};
+
+group gMBACALFIR filter singlebit
+{
+ /** MBACALFIR[0]
+ * MBA_RECOVERABLE_ERROR
+ */
+ (rMBACALFIR, bit(0)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[1]
+ * MBA_NONRECOVERABLE_ERROR
+ */
+ (rMBACALFIR, bit(1)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[2]
+ * REFRESH_OVERRUN
+ */
+ (rMBACALFIR, bit(2)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[3]
+ * WAT_ERROR
+ */
+ (rMBACALFIR, bit(3)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[4]
+ * RCD parity error on port 0
+ */
+ (rMBACALFIR, bit(4)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[5]
+ * DDR0_CAL_TIMEOUT_ERR
+ */
+ (rMBACALFIR, bit(5)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[6]
+ * DDR1_CAL_TIMEOUT_ERR
+ */
+ (rMBACALFIR, bit(6)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[7]
+ * RCD parity error on port 1
+ */
+ (rMBACALFIR, bit(7)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[8]
+ * MBX_TO_MBA_PAR_ERROR
+ */
+ (rMBACALFIR, bit(8)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[9]
+ * MBA_WRD_UE
+ */
+ (rMBACALFIR, bit(9)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[10]
+ * MBA_WRD_CE
+ */
+ (rMBACALFIR, bit(10)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[11]
+ * MBA_MAINT_UE
+ */
+ (rMBACALFIR, bit(11)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[12]
+ * MBA_MAINT_CE
+ */
+ (rMBACALFIR, bit(12)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[13]
+ * DDR_CAL_RESET_TIMEOUT
+ */
+ (rMBACALFIR, bit(13)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[14]
+ * WRQ_DATA_CE
+ */
+ (rMBACALFIR, bit(14)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[15]
+ * WRQ_DATA_UE
+ */
+ (rMBACALFIR, bit(15)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[16]
+ * WRQ_DATA_SUE
+ */
+ (rMBACALFIR, bit(16)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[17]
+ * WRQ_RRQ_HANG_ERR
+ */
+ (rMBACALFIR, bit(17)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[18]
+ * SM_1HOT_ERR
+ */
+ (rMBACALFIR, bit(18)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[19]
+ * WRD_SCOM_ERROR
+ */
+ (rMBACALFIR, bit(19)) ? TBDDefaultCallout;
+
+ /** MBACALFIR[20]
+ * SCOM FIR error
+ */
+ (rMBACALFIR, bit(20)) ? TBDDefaultCallout; # DD1 action, masked for DD2+
+
+ /** MBACALFIR[21]
+ * SCOM FIR error clone
+ */
+ (rMBACALFIR, bit(21)) ? TBDDefaultCallout; # DD1 action, masked for DD2+
+
+ /** MBACALFIR[22]
+ * RHMR_SEC_ALREADY_FULL
+ */
+ (rMBACALFIR, bit(22)) ? TBDDefaultCallout; # DD2+ only
+
+ /** MBACALFIR[23]
+ * Reserved
+ */
+ (rMBACALFIR, bit(23)) ? TBDDefaultCallout; # DD2+ only
+
+ /** MBACALFIR[24]
+ * SCOM FIR error
+ */
+ (rMBACALFIR, bit(24)) ? TBDDefaultCallout; # DD2+ only
+
+ /** MBACALFIR[25]
+ * SCOM FIR error clone
+ */
+ (rMBACALFIR, bit(25)) ? TBDDefaultCallout; # DD2+ only
+
+};
+
+################################################################################
+# Memory Buffer MBA SECURE FIR
+################################################################################
+
+rule rMBASECUREFIR
+{
+ UNIT_CS:
+ MBASECUREFIR;
+};
+
+group gMBASECUREFIR filter singlebit
+{
+ /** MBASECUREFIR[0]
+ * INVALID_MBA_CAL0Q_ACCESS
+ */
+ (rMBASECUREFIR, bit(0)) ? TBDDefaultCallout;
+
+ /** MBASECUREFIR[1]
+ * INVALID_MBA_CAL1Q_ACCESS
+ */
+ (rMBASECUREFIR, bit(1)) ? TBDDefaultCallout;
+
+ /** MBASECUREFIR[2]
+ * INVALID_MBA_CAL2Q_ACCESS
+ */
+ (rMBASECUREFIR, bit(2)) ? TBDDefaultCallout;
+
+ /** MBASECUREFIR[3]
+ * INVALID_MBA_CAL3Q_ACCESS
+ */
+ (rMBASECUREFIR, bit(3)) ? TBDDefaultCallout;
+
+ /** MBASECUREFIR[4]
+ * INVALID_DDR_CONFIG_REG_ACCESS
+ */
+ (rMBASECUREFIR, bit(4)) ? TBDDefaultCallout;
+
+ /** MBASECUREFIR[5]
+ * INVALID_SIR_MASK_OR_ACTION_REGISTER_ACCESS
+ */
+ (rMBASECUREFIR, bit(5)) ? TBDDefaultCallout;
+
+};
+
+################################################################################
+# Memory Buffer MBA FIR
+################################################################################
+
+rule rMBAFIR
+{
+ UNIT_CS:
+ MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 & ~MBAFIR_ACT1;
+ RECOVERABLE:
+ MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 & MBAFIR_ACT1;
+};
+
+group gMBAFIR filter singlebit
+{
+ /** MBAFIR[0]
+ * Invalid Maintenance Command
+ */
+ (rMBAFIR, bit(0)) ? TBDDefaultCallout;
+
+ /** MBAFIR[1]
+ * Invalid Maintenance Address
+ */
+ (rMBAFIR, bit(1)) ? TBDDefaultCallout;
+
+ /** MBAFIR[2]
+ * Multi-address Maintenance Cmd Timeout
+ */
+ (rMBAFIR, bit(2)) ? TBDDefaultCallout;
+
+ /** MBAFIR[3]
+ * Internal FSM parity error
+ */
+ (rMBAFIR, bit(3)) ? TBDDefaultCallout;
+
+ /** MBAFIR[4]
+ * MCBIST error
+ */
+ (rMBAFIR, bit(4)) ? TBDDefaultCallout;
+
+ /** MBAFIR[5]
+ * SCOM command register parity error
+ */
+ (rMBAFIR, bit(5)) ? TBDDefaultCallout;
+
+ /** MBAFIR[6]
+ * Unrecoverable channel error
+ */
+ (rMBAFIR, bit(6)) ? TBDDefaultCallout;
+
+ /** MBAFIR[7]
+ * UE or CE Error in WRD caw2 data latches
+ */
+ (rMBAFIR, bit(7)) ? TBDDefaultCallout;
+
+ /** MBAFIR[8]
+ * An illegal state transition in maintenance state machine
+ */
+ (rMBAFIR, bit(8)) ? TBDDefaultCallout; # DD2+ only
+
+ /** MBAFIR[9:14]
+ * Reserved
+ */
+ (rMBAFIR, bit(9|10|11|12|13|14)) ? TBDDefaultCallout;
+
+ /** MBAFIR[15]
+ * SCOM FIR error
+ */
+ (rMBAFIR, bit(15)) ? TBDDefaultCallout;
+
+ /** MBAFIR[16]
+ * SCOM FIR error clone
+ */
+ (rMBAFIR, bit(16)) ? TBDDefaultCallout;
+
+};
+
+################################################################################
+# Memory Buffer MBA SPA register
+################################################################################
+
+rule rMBASPA
+{
+ HOST_ATTN:
+ MBASPA & ~MBASPA_MASK;
+};
+
+group gMBASPA filter singlebit
+{
+ /** MBASPA[0]
+ * Maintenance command complete
+ */
+ (rMBASPA, bit(0)) ? TBDDefaultCallout;
+
+ /** MBASPA[1]
+ * Hard NCE ETE
+ */
+ (rMBASPA, bit(1)) ? TBDDefaultCallout;
+
+ /** MBASPA[2]
+ * Soft NCE ETE
+ */
+ (rMBASPA, bit(2)) ? TBDDefaultCallout;
+
+ /** MBASPA[3]
+ * Intermittent NCE ETE
+ */
+ (rMBASPA, bit(3)) ? TBDDefaultCallout;
+
+ /** MBASPA[4]
+ * Retry CE ETE
+ */
+ (rMBASPA, bit(4)) ? TBDDefaultCallout;
+
+ /** MBASPA[5]
+ * Emergency throttle attention
+ */
+ (rMBASPA, bit(5)) ? TBDDefaultCallout;
+
+ /** MBASPA[6]
+ * Firmware generated attention 0
+ */
+ (rMBASPA, bit(6)) ? TBDDefaultCallout;
+
+ /** MBASPA[7]
+ * Firmware generated attention 1
+ */
+ (rMBASPA, bit(7)) ? TBDDefaultCallout;
+
+ /** MBASPA[8]
+ * Maintenance command complete
+ */
+ (rMBASPA, bit(8)) ? TBDDefaultCallout;
+
+ /** MBASPA[9]
+ * Spare
+ */
+ (rMBASPA, bit(9)) ? TBDDefaultCallout;
+
+ /** MBASPA[10]
+ * MCBIST done
+ */
+ (rMBASPA, bit(10)) ? TBDDefaultCallout;
+
+};
+
+################################################################################
+# Memory Buffer MBA DDR PHY FIR
+################################################################################
+
+rule rMBADDRPHYFIR
+{
+ UNIT_CS:
+ MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 & ~MBADDRPHYFIR_ACT1;
+ RECOVERABLE:
+ MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 & MBADDRPHYFIR_ACT1;
+};
+
+group gMBADDRPHYFIR filter singlebit
+{
+ /** MBADDRPHYFIR[48]
+ * FSM Error Checkstop
+ */
+ (rMBADDRPHYFIR, bit(48)) ? TBDDefaultCallout;
+
+ /** MBADDRPHYFIR[49]
+ * Parity Error Checkstop
+ */
+ (rMBADDRPHYFIR, bit(49)) ? TBDDefaultCallout;
+
+ /** MBADDRPHYFIR[50]
+ * Calibration Error RE
+ */
+ (rMBADDRPHYFIR, bit(50)) ? TBDDefaultCallout;
+
+ /** MBADDRPHYFIR[51]
+ * FSM Recoverable Error
+ */
+ (rMBADDRPHYFIR, bit(51)) ? TBDDefaultCallout;
+
+ /** MBADDRPHYFIR[52]
+ * Parity Recoverable Error
+ */
+ (rMBADDRPHYFIR, bit(52)) ? TBDDefaultCallout;
+
+ /** MBADDRPHYFIR[53]
+ * Parity Recoverable Error
+ */
+ (rMBADDRPHYFIR, bit(53)) ? TBDDefaultCallout;
+
+ /** MBADDRPHYFIR[54:55]
+ * Reserved
+ */
+ (rMBADDRPHYFIR, bit(54|55)) ? TBDDefaultCallout;
+
+ /** MBADDRPHYFIR[56]
+ * FSM Error Checkstop
+ */
+ (rMBADDRPHYFIR, bit(56)) ? TBDDefaultCallout;
+
+ /** MBADDRPHYFIR[57]
+ * Parity Error Checkstop
+ */
+ (rMBADDRPHYFIR, bit(57)) ? TBDDefaultCallout;
+
+ /** MBADDRPHYFIR[58]
+ * Calibration Error RE
+ */
+ (rMBADDRPHYFIR, bit(58)) ? TBDDefaultCallout;
+
+ /** MBADDRPHYFIR[59]
+ * FSM Recoverable Error
+ */
+ (rMBADDRPHYFIR, bit(59)) ? TBDDefaultCallout;
+
+ /** MBADDRPHYFIR[60]
+ * Parity Recoverable Error
+ */
+ (rMBADDRPHYFIR, bit(60)) ? TBDDefaultCallout;
+
+};
+
+ ##############################################################################
+ # #
+ # # ### #
+ # # # ## ##### ### ### # # # # # # ### ### ### ### #
+ # # # # # # # # # ## # # # # # # # # # #
+ # ####### # # # # # # # # # # ##### ### ### ## ### #
+ # # # # # # # # # # ## # # # # # # # # # #
+ # # # ## # ### ### # # ### ### # # ### ### ### ### #
+ # #
+ ##############################################################################
+
+# Include the common action set.
+.include "cen_common_actions.rule";
+# Include the chip-specific action set.
+.include "cen_mba_actions.rule";
+
diff --git a/src/usr/diag/prdf/common/plat/p9/prdfCommonPlugins.C b/src/usr/diag/prdf/common/plat/p9/prdfCommonPlugins.C
index 06d524416..ea2565edb 100644
--- a/src/usr/diag/prdf/common/plat/p9/prdfCommonPlugins.C
+++ b/src/usr/diag/prdf/common/plat/p9/prdfCommonPlugins.C
@@ -80,6 +80,8 @@ PRDF_PLUGIN_DEFINE_NS( p9_cumulus, CommonPlugins, ClearServiceCallFlag );
PRDF_PLUGIN_DEFINE_NS( p9_mc, CommonPlugins, ClearServiceCallFlag );
PRDF_PLUGIN_DEFINE_NS( p9_mi, CommonPlugins, ClearServiceCallFlag );
PRDF_PLUGIN_DEFINE_NS( p9_dmi, CommonPlugins, ClearServiceCallFlag );
+PRDF_PLUGIN_DEFINE_NS( cen_centaur,CommonPlugins, ClearServiceCallFlag );
+PRDF_PLUGIN_DEFINE_NS( cen_mba, CommonPlugins, ClearServiceCallFlag );
/**
* @brief Clear the service call flag (field and MNFG) so that thresholding
diff --git a/src/usr/diag/prdf/common/plat/p9/prdfP9Configurator.C b/src/usr/diag/prdf/common/plat/p9/prdfP9Configurator.C
index 758fc1af9..571965a24 100755
--- a/src/usr/diag/prdf/common/plat/p9/prdfP9Configurator.C
+++ b/src/usr/diag/prdf/common/plat/p9/prdfP9Configurator.C
@@ -264,6 +264,22 @@ errlHndl_t PlatConfigurator::addDomainChips( TARGETING::TYPE i_type,
case TYPE_MI: fileName = p9_mi; break;
case TYPE_DMI: fileName = p9_dmi; break;
+ case TYPE_MEMBUF:
+ {
+ // Get the MEMBUF model. We don't support mixed MEMBUF models so
+ // should be able to use the first MEMBUF in the list.
+ TARGETING::MODEL model = getChipModel( trgtList[0] );
+
+ if ( MODEL_CENTAUR == model ) fileName = cen_centaur;
+ else
+ // Print a trace statement, but do not fail the build.
+ PRDF_ERR( "[addDomainChips] Unsupported MEMBUF model: %d",
+ model );
+ break;
+ }
+
+ case TYPE_MBA: fileName = cen_mba; break;
+
default:
// Print a trace statement, but do not fail the build.
PRDF_ERR( "[addDomainChips] Unsupported target type: %d",
diff --git a/src/usr/diag/prdf/common/rule/prdfRuleFiles.C b/src/usr/diag/prdf/common/rule/prdfRuleFiles.C
index e43b28160..00f162833 100755
--- a/src/usr/diag/prdf/common/rule/prdfRuleFiles.C
+++ b/src/usr/diag/prdf/common/rule/prdfRuleFiles.C
@@ -51,9 +51,9 @@ namespace PRDF
const char * p9_mi = "p9_mi";
const char * p9_dmi = "p9_dmi";
- // Pegasus Centaur Chip
-// const char * Membuf = "Membuf";
-// const char * Mba = "Mba";
+ // P9 Centaur Chip
+ const char * cen_centaur = "cen_centaur";
+ const char * cen_mba = "cen_mba";
} // end namespace PRDF
diff --git a/src/usr/diag/prdf/common/rule/prdfRuleFiles.H b/src/usr/diag/prdf/common/rule/prdfRuleFiles.H
index e2bd96c82..b079260c8 100755
--- a/src/usr/diag/prdf/common/rule/prdfRuleFiles.H
+++ b/src/usr/diag/prdf/common/rule/prdfRuleFiles.H
@@ -52,9 +52,9 @@ namespace PRDF
extern const char * p9_mi;
extern const char * p9_dmi;
- // Centaur Chip
-// extern const char * Membuf;
-// extern const char * Mba;
+ // P9 Centaur Chip
+ extern const char * cen_centaur;
+ extern const char * cen_mba;
} // end namespace PRDF
diff --git a/src/usr/diag/prdf/common/rule/prdf_rule.mk b/src/usr/diag/prdf/common/rule/prdf_rule.mk
index 5209b7bdf..4aff799b3 100644
--- a/src/usr/diag/prdf/common/rule/prdf_rule.mk
+++ b/src/usr/diag/prdf/common/rule/prdf_rule.mk
@@ -40,6 +40,8 @@ PRDR_RULE_TABLES += p9_mca.prf
PRDR_RULE_TABLES += p9_mc.prf
PRDR_RULE_TABLES += p9_mi.prf
PRDR_RULE_TABLES += p9_dmi.prf
+PRDR_RULE_TABLES += cen_centaur.prf
+PRDR_RULE_TABLES += cen_mba.prf
prd_rule_prf_targets = ${PRDR_RULE_TABLES}
prd_rule_err_targets = ${PRDR_RULE_TABLES:.prf=.prf.err.C}
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