INITPROC: Hostboot - SW233456 Sundry initfile

Change-Id: I70133aada9879bc5ca2f2575def7d228ac7a5f78
CQ:SW233456
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7142
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

4 files changed, 169 insertions, 36 deletions

diff --git a/src/usr/hwpf/hwp/centaur_ec_attributes.xml b/src/usr/hwpf/hwp/centaur_ec_attributes.xml
index 55277dbca..b373256bb 100644
--- a/src/usr/hwpf/hwp/centaur_ec_attributes.xml
+++ b/src/usr/hwpf/hwp/centaur_ec_attributes.xml
@@ -22,7 +22,7 @@
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <attributes>
 <!-- ********************************************************************* -->
-  <!-- $Id: centaur_ec_attributes.xml,v 1.10 2013/09/11 12:29:40 bwieman Exp $ -->
+  <!-- $Id: centaur_ec_attributes.xml,v 1.14 2013/10/31 13:17:30 bwieman Exp $ -->
   <attribute>
     <id>ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
@@ -41,6 +41,41 @@
   </attribute>
 
   <attribute>
+    <id>ATTR_CENTAUR_EC_ENABLE_NM_CHANGE_AFTER_SYNC</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  IF TRUE, ENABLE NM change after sync.
+        This fix that is going into DD2 (to use values in N/M shadow registers when a sync command is seen), we should be able to change M to a different value if we wanted to without any issues.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  IF TRUE, Enable ROW HAMMER ENHANCEMENT FOR DD2.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
     <id>ATTR_CENTAUR_EC_WRITE_FIR_MASK_FEATURE</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>
@@ -132,7 +167,7 @@ Controls the ddr_phy_reset procedure.  When set to TRUE, the procedure will cont
     <id>ATTR_CENTAUR_EC_ECID_CONTAINS_PORT_LOGIC_BAD_INDICATION</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>
-      If true then mss_get_cen_ecid reads the ECID bits to determine if 
+      If true then mss_get_cen_ecid reads the ECID bits to determine if
       logic on either of the ports are good.  For DD2, these bits are not
       used for this purpose and so the check is not made.
       This is true for Centaur 1.*
@@ -147,7 +182,7 @@ Controls the ddr_phy_reset procedure.  When set to TRUE, the procedure will cont
       </chip>
     </chipEcFeature>
   </attribute>
- 
+
   <attribute>
     <id>ATTR_CENTAUR_EC_MCBIST_RANDOM_DATA_GEN</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
@@ -164,7 +199,7 @@ Controls the ddr_phy_reset procedure.  When set to TRUE, the procedure will cont
       </chip>
     </chipEcFeature>
   </attribute>
-  
+
   <attribute>
     <id>ATTR_CENTAUR_EC_MCBIST_TRAP_RESET</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
@@ -181,7 +216,7 @@ Controls the ddr_phy_reset procedure.  When set to TRUE, the procedure will cont
       </chip>
     </chipEcFeature>
   </attribute>
-  
+
   <attribute>
     <id>ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
@@ -199,4 +234,38 @@ Controls the ddr_phy_reset procedure.  When set to TRUE, the procedure will cont
     </chipEcFeature>
   </attribute>
 
+    <attribute>
+    <id>ATTR_CENTAUR_EC_SCOM_PARITY_ERROR_HW244827_FIXED</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  If false, draminit_mc will execute a putscom to clear the scom parity error fir for all densities on DD1.X parts.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+    <attribute>
+    <id>ATTR_CENTAUR_EC_HW217608_MBSPA_0_CMD_COMPLETE_ATTN_FIXED</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  If true, MBSPA bit 8 is masked, and MBSPA bit 0 is unmasked and configured to report when maint cmd either stops clean or stops on error. Otherwise, MBSPA bit 0 is masked, and MBSPA bit 8 is unmasked. NOTE: For DD1 when using MBSPA bit 8, a scan init is needed to enable the WAT workaround allows bit 8 to report when maint cmd either stops clean or stops on error. The scan init is enabled for DD1 and disabled for DD2, but does not use this same attribute.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
 </attributes>
diff --git a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile
index 1ed84a791..95e3424fb 100755
--- a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile
+++ b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile
@@ -1,4 +1,4 @@
-#-- $Id: cen_ddrphy.initfile,v 1.26 2013/07/17 15:45:02 mwuu Exp $
+#-- $Id: cen_ddrphy.initfile,v 1.27 2013/11/01 19:40:50 mwuu Exp $
 #-- $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
 #--          centaur/working/procedures/ec_ind/scoms/cen_ddrphy.initfile,v $
 #
@@ -6,6 +6,11 @@
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#		1.28|mwuu    |11/01/13|Had a typo for ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8,
+#		                      |port A was getting the value of A9 phase rotator.
+#		                      |Using attribute settings for GPO,RLO,WLO for LRDIMM
+#		1.27|mwuu    |08/22/13|Changed RLO/GPO settings for LRDIMM to be picked up
+#		                      |by mss_eff_config_termination.
 #--     1.26|mwuu    |07/17/13|Changed FAST_SIM_PC to use SIM attribute, changed
 #           |        |        |type1 define to use CUSTOM attribute as well.
 #           |        |        |Changed READ_CLOCK section to enable clocks for x4.
@@ -430,7 +435,7 @@ scom 0x8000C00D0301143F {
 # 	# 9.4.12.2	RLO = READ_LATENCY_OFFSET (2's complement -8 to 7) {0=CDIMM, 1=RDIMM, 2=LRDIMM}
 # 	52:55	,	0x1			,	(def_is_rdimm)						;	# RDIMM
 # 	52:55	,	0x0			,	any									;	# CDIMM/UDIMM
- 	52:55	,	0x6			,	(def_is_lrdimm)						;	# LRDIMM
+# 	52:55	,	0x6			,	(def_is_lrdimm)						;	# LRDIMM	# !! need to review LR settings !!
  	52:55	,	(ATTR_EFF_RLO[0]),	any								;	# based on attribute now..
  	56		,	0b0			,	any									;	# MEMCTL_CIC_FAST
  	57		,	0b0			,	any									;	# MEMCTL_CTRN_IGNORE
@@ -855,8 +860,8 @@ scom 0x80013C7A0301143f {				# NFET_TERM_P1_[0:4]	broadcast
 	48:59	,	0x000	,	any											;	# 240/0, 480/0
 #	60:63	,	0b0000	,	any											;	# reserved
 }
-# DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_0	0x07B	0x8000007B0301143f
-#scom 0x8000(00,04,08,0C,10)7B0301143f {	# PFET_TERM_P1_[0:4]
+# DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_0	0x07B	0x8001007B0301143f
+#scom 0x8001(00,04,08,0C,10)7B0301143f {	# PFET_TERM_P1_[0:4]
 scom 0x80013C7B0301143f {				# PFET_TERM_P1_[0:4]	broadcast
 	bits	,	scom_data,	expr									;
 #	0:47	,	0x000000000000,	any									;	# reserved
@@ -3757,7 +3762,7 @@ scom 0x8000C8000301143F {	# _P0
 	#
 	# min GPO = 5 + max(rndUp(System_delay)) - RLO + ADVANCE_RD_VALID + SPAM_EN
 	# max GPO = 11 if in 2:1, 13 if in 4:1
-	48:51	,	0b0111		,	(def_is_lrdimm)	;	# GLOBAL_PHY_OFFSET LRDIMM set to 7
+#	48:51	,	0b0111		,	(def_is_lrdimm)	;	# GLOBAL_PHY_OFFSET LRDIMM set to 7		# need to review LR settings
 	48:51	,	(ATTR_EFF_GPO[0]),	any			;	# GLOBAL_PHY_OFFSET (GPO), based on attribute now
 #	48:51	,	0b0101		,	any				;	# GLOBAL_PHY_OFFSET (GPO), ideally 2:1 max=11, 4:1 max=13
 	52		,	0b0			,	any				;	# ADVANCE_RD_VALID	ask Yuen
@@ -4555,10 +4560,10 @@ scom 0x800048080301143F {	# DPHY01_DDRPHY_ADR_DELAY4_P0_ADR2
 scom 0x800048090301143F {	# DPHY01_DDRPHY_ADR_DELAY5_P0_ADR2
 	bits	,	scom_data			,	expr									;
 #	0:47	,	0x000000000000		,	any										;	# reserved
-	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0])		,	(def_is_mba01)	;	# P0 L12, A0_CLK1_n
-	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0])		,	(def_is_mba01)	;	# P0 L13, A0_CLK1_p
-	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0])		,	(def_is_mba23)	;	# P2 L12, C0_CLK0_n
-	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0])		,	(def_is_mba23)	;	# P2 L13, C0_CLK0_p
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0])		,	(def_is_mba01)	;	# P0 L10, A0_CLK1_n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0])		,	(def_is_mba01)	;	# P0 L11, A0_CLK1_p
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0])		,	(def_is_mba23)	;	# P2 L10, C0_CLK0_n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0])		,	(def_is_mba23)	;	# P2 L11, C0_CLK0_p
 }
 scom 0x8000480A0301143F {	# DPHY01.DDRPHY_ADR_DELAY6_P0_ADR2
 	bits	,	scom_data			,	expr									;
@@ -4612,16 +4617,16 @@ scom 0x80004C080301143F {	# DPHY01_DDRPHY_ADR_DELAY4_P0_ADR3
 scom 0x80004C090301143F {	# DPHY01_DDRPHY_ADR_DELAY5_P0_ADR3
 	bits	,	scom_data			,	expr									;
 #	0:47	,	0x000000000000		,	any										;	# reserved
-	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7[0])		,	(def_is_mba01)	;	# P0 L12, A_A7
-	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_ACTN[0])			,	(def_is_mba01)	;	# P0 L13, A_ACTn
-	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0[0])		,	(def_is_mba23)	;	# P2 L12, C_BA0
-	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN[0])		,	(def_is_mba23)	;	# P2 L13, C_CASn
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7[0])		,	(def_is_mba01)	;	# P0 L10, A_A7
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_ACTN[0])			,	(def_is_mba01)	;	# P0 L11, A_ACTn
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0[0])		,	(def_is_mba23)	;	# P2 L10, C_BA0
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN[0])		,	(def_is_mba23)	;	# P2 L11, C_CASn
 }
 scom 0x80004C0A0301143F {	# DPHY01.DDRPHY_ADR_DELAY6_P0_ADR3
 	bits	,	scom_data			,	expr									;
 #	0:47	,	0x000000000000		,	any										;	# reserved
 	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[0])		,	(def_is_mba01)	;	# P0 L12, A_A9
-	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[0])		,	(def_is_mba01)	;	# P0 L13, A_A8
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8[0])		,	(def_is_mba01)	;	# P0 L13, A_A8	# fixed typo
 	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4[0])		,	(def_is_mba23)	;	# P2 L12, C_A4
 	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3[0])	,	(def_is_mba23)	;	# P2 L13, C0_CS3n
 }
diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
index fc1065bb1..b57f56872 100644
--- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile
+++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
@@ -1,9 +1,11 @@
 
-#-- $Id: mba_def.initfile,v 1.49 2013/10/24 18:49:51 yctschan Exp $
+#-- $Id: mba_def.initfile,v 1.51 2013/11/06 22:03:00 yctschan Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.51|tschang |11/06/13|DD2 row hammer enhancement added with ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE attribute
+#--     1.50|tschang |11/06/13|ATTR_CENTAUR_EC_ENABLE_NM_CHANGE_AFTER_SYNC is 1 for DD2 - HW245888
 #--     1.49|tschang |10/24/13|added ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT, ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT to throttle settings
 #--     1.48|tschang | 9/30/13|add 10% margin to refresh check interval calculations
 #--     1.47|tschang | 8/15/13| HW259719 - dd2 only fix - ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL to turn on clock gates
@@ -1705,9 +1707,36 @@ scom 0x03010416     {
     51      ,   0b1                                       ,            1            ,     ((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 2) || (ATTR_EFF_DIMM_TYPE == 3));          # cfg_nm_per_slot_enabled	Set to 0 for CDIMM, Set to 1 for everything else
     52      ,   0b0                                       ,            1            ,     (ATTR_EFF_DIMM_TYPE == 0);          # cfg_nm_count_other_mba_dis	Set to 0 for CDIMM, Set to 1 for everything else
     52      ,   0b1                                       ,            1            ,     ((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 2) || (ATTR_EFF_DIMM_TYPE == 3));          # cfg_nm_count_other_mba_dis	Set to 0 for CDIMM, Set to 1 for everything else
+    53      ,   0b1                                       ,            1            ,     (ATTR_CENTAUR_EC_ENABLE_NM_CHANGE_AFTER_SYNC == 1);          # cfg_nm_change_after_sync
 }
 
 
+#Register Name	N/M Throttling Control
+#Mnemonic	MBA_FARB4Q
+#Attributes	PAR:EVEN	Bit	Field Mnemonic	Attribute or Setting to use
+#Description	N/M throttling control (Centaur only)
+#MBA_FARB4Q(0:1)		cfg_rhmr_en			01		Track only (only FIRs will go off, signaling when a block would have occurred)
+#MBA_FARB4Q(2)			cfg_rhmr_secondary_en	0		Secondary Structure disabled (this is for repair sequence)
+#MBA_FARB4Q(3)			cfg_rhmr_hash_swizzle_en	0		Disable swizzling hash (so we don't switch which rows correspond to which counters)
+#MBA_FARB4Q(4:9)		Reserved			000000		Don't Care
+#MBA_FARB4Q(10:11)		cfg_rhmr_decrement_weight	01		Decrement by 1 (minimum weight)
+#MBA_FARB4Q(12:18)		cfg_rhmr_primary_decr_intv	1111111	Slowest rate of decrements. Once ever 2^14 or 16K DRAM clocks*
+#MBA_FARB4Q(19:25)		cfg_rhmr_secondary_decr_intv	0000000	Don't care
+#MBA_FARB4Q(26)		cfg_rhmr_sim_en		0		Disable sim mode
+#*I think this corresponds to protecting a row from being hammered 64K times.
+
+scom 0x03010417     {
+    bits    ,   scom_data                                 ,       ATTR_FUNCTIONAL,     expr;
+    0:1     ,   0b01                                      ,            1            ,    (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+    2       ,   0b0                                       ,            1            ,    (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+    3       ,   0b0                                       ,            1            ,    (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+    4:9     ,   0b000000                                  ,            1            ,    (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+    10:11   ,   0b01                                      ,            1            ,    (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+    12:18   ,   0b1111111                                 ,            1            ,    (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+    19:25   ,   0b0000000                                 ,            1            ,    (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+    26      ,   0b0                                       ,            1            ,    (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+}
+
 
 # ATTR_EFF_DIMM_TYPE
 # CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3
@@ -2074,6 +2103,7 @@ scom 0x0301040C     {
 # 1600Mbps CDIMM WL = Setting + 7 = CWL + AL[CL-1] = 18
 #putscom cen.mba 301040a 30 6 001011 -ib -pall -call
 
+#define def_WLO = ((ATTR_EFF_WLO[0] & 0x07) + (((ATTR_EFF_WLO[0] & 0x0F) >> 3) * -8));
 define def_WL_AL0 = (ATTR_EFF_DRAM_CWL - 7);
 define def_WL_AL_MINUS1 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 1 - 7);
 define def_WL_AL_MINUS2 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 2 - 7);
@@ -2099,10 +2129,13 @@ scom 0x0301040A     {
     12:17   ,   0b000000    ,           1            ,    any; # CFG_WODT_start_dly is 0 for all cfgs   23                     D
     18:23   ,   0b000101    ,           1            ,    any; # CFG_WODT_end_dly is 5 for all cfgs     24                     D
     24:29   ,   0b011000    ,           1            ,    any; # wrdone_dly is 24 for all cfgs 25                              D
+#    30:35   ,   def_WL_AL0 + def_WLO  ,       1            ,    (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_AL == 0)); # wrdata_dly
     30:35   ,   def_WL_AL0 + 1  ,       1            ,    (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_AL == 0)); # wrdata_dly
     30:35   ,   def_WL_AL0      ,       1            ,    (((ATTR_EFF_DIMM_TYPE == 0) || (ATTR_EFF_DIMM_TYPE == 2)) && (ATTR_EFF_DRAM_AL == 0)); # wrdata_dly
+#    30:35   ,   def_WL_AL_MINUS1 + def_WLO  , 1            ,    (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_AL == 1)); # wrdata_dly
     30:35   ,   def_WL_AL_MINUS1 + 1  , 1            ,    (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_AL == 1)); # wrdata_dly
     30:35   ,   def_WL_AL_MINUS1      , 1            ,    (((ATTR_EFF_DIMM_TYPE == 0) || (ATTR_EFF_DIMM_TYPE == 2)) && (ATTR_EFF_DRAM_AL == 1)); # wrdata_dly
+#    30:35   ,   def_WL_AL_MINUS2 + def_WLO  , 1            ,    (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_AL == 2)); # wrdata_dly
     30:35   ,   def_WL_AL_MINUS2 + 1  , 1            ,    (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_AL == 2)); # wrdata_dly
     30:35   ,   def_WL_AL_MINUS2      , 1            ,    (((ATTR_EFF_DIMM_TYPE == 0) || (ATTR_EFF_DIMM_TYPE == 2)) && (ATTR_EFF_DRAM_AL == 2)); # wrdata_dly
     36:41   ,   0b001100 + def_margin_rdtag   ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly12 == 1); # rdtag_dly		27
diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
index d08dcb611..37e51d709 100644
--- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
+++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
@@ -1,8 +1,9 @@
-#-- $Id: mbs_def.initfile,v 1.37 2013/08/15 19:20:26 yctschan Exp $
+#-- $Id: mbs_def.initfile,v 1.38 2013/10/30 23:51:42 yctschan Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--   1.38  |tschang |10/30/13| hash mode update for other IBM types
 #--   1.37  |tschang |08/15/13| HW259719 - dd2 only fix - ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL to turn on clock gates
 #--   1.36  |tschang |07/03/13| L4.ATTR_FUNCTIONAL for cache enable for some bits I missed
 #--   1.35  |tschang |07/02/13| L4.ATTR_FUNCTIONAL for cache enable
@@ -399,13 +400,6 @@ define def_mba23_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated = (def_mb
 define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated    = (def_mba23_1a_2socket      ||def_mba23_1b_2socket      ||def_mba23_1c_2socket      ||def_mba23_2a_2socket      ||def_mba23_2a_2socket_ddr4 ||def_mba23_2b_2socket      ||def_mba23_2b_2socket_ddr4 ||def_mba23_2c_2socket      ||def_mba23_2c_2socket_ddr4 ||def_mba23_3a_2socket      ||def_mba23_3a_2socket_ddr4 ||def_mba23_3b_2socket      ||def_mba23_3c_2socket_ddr4 ||def_mba23_5b_2socket      ||def_mba23_5c_2socket      ||def_mba23_5d_2socket      ||def_mba23_7a_2socket      ||def_mba23_7b_2socket      ||def_mba23_7c_2socket      ||def_mba23_7a_2socket_ddr4 ||def_mba23_7b_2socket_ddr4 ||def_mba23_7c_2socket_ddr4 ||def_mba23_1c_cdimm        ||def_mba23_3a_cdimm        ||def_mba23_3b_cdimm        ||def_mba23_3c_cdimm        ||def_mba23_3a_ddr4_cdimm   ||def_mba23_3b_ddr4_cdimm   ||def_mba23_3c_ddr4_cdimm   ||def_mba23_4a_cdimm        ||def_mba23_4a_ddr4_cdimm   ||def_mba23_4b_ddr4_cdimm   ||def_mba23_4c_ddr4_cdimm);
 
 ## Temp defines until the code adds these attributes
-#define  def_ATTR_MSS_CACHE_ENABLE = 0;                                   # cache disable
-#define  def_ATTR_MSS_PREFETCH_ENABLE = 0;                                # prefetch disable
-#define  def_ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT = 0;                        # no MBA interleave
-#define  def_01ATTR_MSS_MBA_INTERLEAVE_MODE = 0;
-#define  def_23ATTR_MSS_MBA_INTERLEAVE_MODE = 0;
-#define  def_01ATTR_EFF_MBA_POS = 0;	# -MW not needed?
-#define  def_23ATTR_EFF_MBA_POS = 1;	# -MW not needed?
 
 #--******************************************************************************
 #-- MBS FIR MASK Register
@@ -418,7 +412,7 @@ define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated    = (def_mb
 
 
 #--******************************************************************************
-# TRACE_TRCTRL_CONFIG MBA01 Trace Control Configuration Register
+# TRACE_TRCTRL_CONFIG Trace Control Configuration Register
 #
 # HW259719 - lcl_clk_gate_ctrl needs to be turned on and left on
 # DD2 fixed ONLY
@@ -601,6 +595,22 @@ define def_mba01_hash0_type1a = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1) || (MBA0.AT
 # Type 1B/5B - simplied table to hash mode 2 when both dimm configured  and hash mode 1 when 1 dimm is configured
 define def_mba01_hash2_type1b_5b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15)) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] != 0) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] != 0);
 define def_mba01_hash1_type1b_5b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15)) && ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0) || (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0));
+# Type 1D/5C - simplied table to hash mode 2 for all cfgs
+define def_mba01_hash2_type1d_5c = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 16));
+# Type 2A - simplied table to hash mode 1 when both dimm configured  and hash mode 0 when 1 dimm is configured
+define def_mba01_hash1_type2a = (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] != 0) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] != 0);
+define def_mba01_hash0_type2a = (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5) && ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0) || (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0));
+# Type 2B - simplied table to hash mode 0 for all cfgs
+define def_mba01_hash0_type2b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6));
+# Type 3A/7A - simplied table to hash mode 1 for all cfgs
+define def_mba01_hash1_type3a_7a = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21));
+# Type 3B/7B - simplied table to hash mode 0 for all cfgs
+define def_mba01_hash0_type3b_7b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22));
+# Type 2C - simplied table to hash mode 0 for all cfgs
+define def_mba01_hash0_type2c = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7));
+# Type 3C/7C - simplied table to hash mode 0 for all cfgs
+define def_mba01_hash0_type3c_7c = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23));
+
 
 # MBA23 Type 1A - simplied table to hash mode 1 when both dimm configured
 define def_mba23_hash1_type1a = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1) || (MBA1.ATTR_EFF_IBM_TYPE[1][1] == 1)) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] != 0) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] != 0);
@@ -608,14 +618,30 @@ define def_mba23_hash0_type1a = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1) || (MBA1.AT
 # Type 1B/5B - simplied table to hash mode 2 when both dimm configured  and hash mode 1 when 1 dimm is configured
 define def_mba23_hash2_type1b_5b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15)) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] != 0) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] != 0);
 define def_mba23_hash1_type1b_5b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15)) && ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0) || (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] == 0));
+# Type 1D/5C - simplied table to hash mode 2 for all cfgs
+define def_mba23_hash2_type1d_5c = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 16));
+# Type 2A - simplied table to hash mode 1 when both dimm configured  and hash mode 0 when 1 dimm is configured
+define def_mba23_hash1_type2a = (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] != 0) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] != 0);
+define def_mba23_hash0_type2a = (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5) && ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0) || (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0));
+# Type 2B - simplied table to hash mode 0 for all cfgs
+define def_mba23_hash0_type2b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6));
+# Type 3A/7A - simplied table to hash mode 1 for all cfgs
+define def_mba23_hash1_type3a_7a = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21));
+# Type 3B/7B - simplied table to hash mode 0 for all cfgs
+define def_mba23_hash0_type3b_7b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22));
+# Type 2C - simplied table to hash mode 0 for all cfgs
+define def_mba23_hash0_type2c = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7));
+# Type 3C/7C - simplied table to hash mode 0 for all cfgs
+define def_mba23_hash0_type3c_7c = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23));
+
+define def_mba01_hash0_sel = (def_mba01_hash0_type1a)    ||(def_mba01_hash0_type2a)    ||(def_mba01_hash0_type2b)    ||(def_mba01_hash0_type2c)    ||(def_mba01_hash0_type3b_7b) ||(def_mba01_hash0_type3c_7c) ;
+define def_mba01_hash1_sel = (def_mba01_hash1_type1a)    ||(def_mba01_hash1_type1b_5b) ||(def_mba01_hash1_type2a)    ||(def_mba01_hash1_type3a_7a) ;
+define def_mba01_hash2_sel = (def_mba01_hash2_type1b_5b) ||(def_mba01_hash2_type1d_5c) ;
+
+define def_mba23_hash0_sel = (def_mba23_hash0_type1a)    ||(def_mba23_hash0_type2a)    ||(def_mba23_hash0_type2b)    ||(def_mba23_hash0_type2c)    ||(def_mba23_hash0_type3b_7b) ||(def_mba23_hash0_type3c_7c) ;
+define def_mba23_hash1_sel = (def_mba23_hash1_type1a)    ||(def_mba23_hash1_type1b_5b) ||(def_mba23_hash1_type2a)    ||(def_mba23_hash1_type3a_7a) ;
+define def_mba23_hash2_sel = (def_mba23_hash2_type1b_5b) ||(def_mba23_hash2_type1d_5c) ;
 
-define def_mba01_hash0_sel = (def_mba01_hash0_type1a);
-define def_mba01_hash1_sel = (def_mba01_hash1_type1a) || (def_mba01_hash1_type1b_5b);
-define def_mba01_hash2_sel = (def_mba01_hash1_type1b_5b);
-
-define def_mba23_hash0_sel = (def_mba23_hash0_type1a);
-define def_mba23_hash1_sel = (def_mba23_hash1_type1a) || (def_mba23_hash1_type1b_5b);
-define def_mba23_hash2_sel = (def_mba23_hash1_type1b_5b);
 ####################################
 # MBA01 address translation config #
 ####################################