Centaur file updates (hostboot)

Change-Id: I8ea312cf1ca1229046fe3c9b3c10aa7b78eea8e3
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5882
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

22 files changed, 3487 insertions, 350 deletions

diff --git a/src/usr/hwpf/hwp/dmi_training/mss_getecid/memory_mss_get_cen_ecid.xml b/src/usr/hwpf/hwp/dmi_training/mss_getecid/memory_mss_get_cen_ecid.xml
new file mode 100644
index 000000000..c95575e7d
--- /dev/null
+++ b/src/usr/hwpf/hwp/dmi_training/mss_getecid/memory_mss_get_cen_ecid.xml
@@ -0,0 +1,28 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dmi_training/mss_getecid/memory_mss_get_cen_ecid.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+<!-- $Id: memory_mss_get_cen_ecid.xml,v 1.1 2013/06/19 18:28:15 bellows Exp $ -->
+<!-- For file ../../ipl/fapi/mss_get_cen_ecid.C -->
+<!-- // *! OWNER NAME  : Mark Bellows Email: bellows@us.ibm.com -->
+
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/memory_mss_extent_setup.xml b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/memory_mss_extent_setup.xml
new file mode 100644
index 000000000..362ac7a9e
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/memory_mss_extent_setup.xml
@@ -0,0 +1,27 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/memory_mss_extent_setup.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+<!-- $Id: memory_mss_extent_setup.xml,v 1.1 2013/06/19 18:28:06 bellows Exp $ -->
+<!-- For file ../../ipl/fapi/mss_extent_setup.C -->
+
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C
index 30cc399b8..7dddc8c98 100644
--- a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C
+++ b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C
@@ -1,26 +1,25 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: mss_extent_setup.C,v 1.8 2012/07/17 13:24:10 bellows Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H
index be03117f0..b2d0353f3 100755
--- a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H
+++ b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H
@@ -1,26 +1,25 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: mss_extent_setup.H,v 1.8 2012/07/17 13:22:51 bellows Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/memory_mss_thermal_init.xml b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/memory_mss_thermal_init.xml
new file mode 100644
index 000000000..449352799
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/memory_mss_thermal_init.xml
@@ -0,0 +1,29 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/memory_mss_thermal_init.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+<!-- $Id: memory_mss_thermal_init.xml,v 1.1 2013/06/19 18:28:33 bellows Exp $ -->
+<!-- For file ../../ipl/fapi/mss_thermal_init.C -->
+<!-- // *! OWNER NAME  : Joab Henderson    Email: joabhend@us.ibm.com -->
+<!-- // *! BACKUP NAME : Michael Pardeik   Email: pardeik@us.ibm.com -->
+
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/memory_mss_draminit.xml b/src/usr/hwpf/hwp/dram_training/mss_draminit/memory_mss_draminit.xml
new file mode 100644
index 000000000..0a9689da7
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/memory_mss_draminit.xml
@@ -0,0 +1,27 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/memory_mss_draminit.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+<!-- $Id: memory_mss_draminit.xml,v 1.1 2013/06/19 18:27:45 bellows Exp $ -->
+<!-- For file ../../ipl/fapi/mss_draminit.C -->
+
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/memory_mss_draminit_mc.xml b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/memory_mss_draminit_mc.xml
new file mode 100644
index 000000000..4b4f25363
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/memory_mss_draminit_mc.xml
@@ -0,0 +1,29 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/memory_mss_draminit_mc.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+<!-- $Id: memory_mss_draminit_mc.xml,v 1.1 2013/06/19 18:27:47 bellows Exp $ -->
+<!-- For file ../../ipl/fapi/mss_draminit_mc.C -->
+<!-- // *! OWNER NAME :  David Cadigan   Email: dcadiga@us.ibm.com -->
+<!-- // *! BACKUP NAME : Jacob Sloat   Email: jdsloat@us.ibm.com -->
+
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_access_delay_reg.xml b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_access_delay_reg.xml
new file mode 100644
index 000000000..ed94fb4f8
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_access_delay_reg.xml
@@ -0,0 +1,29 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_access_delay_reg.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+<!-- $Id: memory_mss_access_delay_reg.xml,v 1.1 2013/06/19 18:27:36 bellows Exp $ -->
+<!-- For file ../../ipl/fapi/mss_access_delay_reg.C -->
+<!-- // *! OWNER NAME  : Saurabh Chadha     Email: sauchadh@in.ibm.com -->
+
+
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_draminit_training_advanced.xml b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_draminit_training_advanced.xml
new file mode 100644
index 000000000..84515a9be
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_draminit_training_advanced.xml
@@ -0,0 +1,30 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_draminit_training_advanced.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+<!-- $Id: memory_mss_draminit_training_advanced.xml,v 1.1 2013/06/19 18:27:51 bellows Exp $ -->
+<!-- For file ../../ipl/fapi/mss_draminit_training_advanced.C -->
+<!-- // *! OWNER NAME : Saravanan Sethuraman          email ID:saravanans@in.ibm.com -->
+<!-- // *! BACKUP NAME: Mark D Bellows	 			 email ID:bellows@us.ibm.com -->
+
+
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_generic_shmoo.xml b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_generic_shmoo.xml
new file mode 100644
index 000000000..3d129fdb0
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_generic_shmoo.xml
@@ -0,0 +1,30 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_generic_shmoo.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+<!-- $Id: memory_mss_generic_shmoo.xml,v 1.1 2013/06/19 18:28:14 bellows Exp $ -->
+<!-- For file ../../ipl/fapi/mss_generic_shmoo.C -->
+<!-- // *! OWNER  NAME          : Abhijit Saurabh          Email: abhijit.saurabh@in.ibm.com -->
+<!-- // *! BACKUP NAME          : Sidhartha Vijay      	  Email: sidvijay@in.ibm.com -->
+
+
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_mcbist.xml b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_mcbist.xml
new file mode 100644
index 000000000..efba853a0
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_mcbist.xml
@@ -0,0 +1,30 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_mcbist.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+<!-- $Id: memory_mss_mcbist.xml,v 1.1 2013/06/19 18:28:20 bellows Exp $ -->
+<!-- For file ../../ipl/fapi/mss_mcbist.C -->
+<!-- // *! OWNER  NAME          : Devashikamani, Aditya         Email: adityamd@in.ibm.com -->
+<!-- // *! BACKUP               : Sethuraman, Saravanan         Email: saravanans@in.ibm.com -->
+
+
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_training/mss_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_funcs.C
index f4e1b03a1..1fe38f852 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_funcs.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_funcs.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_funcs.C,v 1.30 2013/04/09 23:33:09 jdsloat Exp $
+// $Id: mss_funcs.C,v 1.31 2013/05/20 21:29:50 jdsloat Exp $
 /* File mss_funcs.C created by SLOAT JACOB D. (JAKE),2D3970 on Fri Apr 22 2011. */
 
 //------------------------------------------------------------------------------
@@ -43,6 +43,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.31   | jdsloat  | 05/20/13| Added ddr_gen determination in address mirror mode function
 //  1.30   | jdsloat  | 04/09/13| Moved Address mirror mode sub function in  from mss_draminit
 //  1.29   | jsabrow  | 11/19/12| added CCS data loader: mss_ccs_load_data_pattern
 //  1.28   | bellows  | 07/16/12|added in Id tag
@@ -131,6 +132,10 @@ ReturnCode mss_address_mirror_swizzle(
     ecmdDataBufferBase bank_post_swizzle_3(3);
     uint16_t mirror_mode_ba = 0;
     uint16_t mirror_mode_ad  = 0;
+    uint8_t dram_gen = 0;
+
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen);
+    if(rc) return rc;
 
 	FAPI_INF( "ADDRESS MIRRORING ON %s PORT%d DIMM%d RANK%d", i_target.toEcmdString(), i_port, i_dimm, i_rank);
 
@@ -143,21 +148,50 @@ ReturnCode mss_address_mirror_swizzle(
 	rc_num = rc_num | address_post_swizzle_16.insert(io_address, 0, 16, 0);
 	rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 3, 0);
 
-	//Swap A3 and A4
-	rc_num = rc_num | address_post_swizzle_16.insert(io_address, 4, 1, 3);
-	rc_num = rc_num | address_post_swizzle_16.insert(io_address, 3, 1, 4);
+	if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) 
+	{
+		//Swap A3 and A4
+		rc_num = rc_num | address_post_swizzle_16.insert(io_address, 4, 1, 3);
+		rc_num = rc_num | address_post_swizzle_16.insert(io_address, 3, 1, 4);
+
+		//Swap A5 and A6
+		rc_num = rc_num | address_post_swizzle_16.insert(io_address, 6, 1, 5);
+		rc_num = rc_num | address_post_swizzle_16.insert(io_address, 5, 1, 6);
 
-	//Swap A5 and A6
-	rc_num = rc_num | address_post_swizzle_16.insert(io_address, 6, 1, 5);
-	rc_num = rc_num | address_post_swizzle_16.insert(io_address, 5, 1, 6);
+		//Swap A7 and A8
+		rc_num = rc_num | address_post_swizzle_16.insert(io_address, 8, 1, 7);
+		rc_num = rc_num | address_post_swizzle_16.insert(io_address, 7, 1, 8);
 
-	//Swap A7 and A8
-	rc_num = rc_num | address_post_swizzle_16.insert(io_address, 8, 1, 7);
-	rc_num = rc_num | address_post_swizzle_16.insert(io_address, 7, 1, 8);
+		//Swap BA0 and BA1
+		rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 1, 1, 0);
+		rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 1, 1);
+	}
+	else if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
+	{
+		//Swap A3 and A4
+		rc_num = rc_num | address_post_swizzle_16.insert(io_address, 4, 1, 3);
+		rc_num = rc_num | address_post_swizzle_16.insert(io_address, 3, 1, 4);
 
-	//Swap BA0 and BA1
-	rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 1, 1, 0);
-	rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 1, 1);
+		//Swap A5 and A6
+		rc_num = rc_num | address_post_swizzle_16.insert(io_address, 6, 1, 5);
+		rc_num = rc_num | address_post_swizzle_16.insert(io_address, 5, 1, 6);
+
+		//Swap A7 and A8
+		rc_num = rc_num | address_post_swizzle_16.insert(io_address, 8, 1, 7);
+		rc_num = rc_num | address_post_swizzle_16.insert(io_address, 7, 1, 8);
+
+		//Swap A11 and A13
+		rc_num = rc_num | address_post_swizzle_16.insert(io_address, 13, 1, 11);
+		rc_num = rc_num | address_post_swizzle_16.insert(io_address, 11, 1, 13);
+
+		//Swap BA0 and BA1
+		rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 1, 1, 0);
+		rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 1, 1);
+
+		//Swap BG0 and BG1 (BA2 and ADDR 15)
+		rc_num = rc_num | bank_post_swizzle_3.insert(io_address, 2, 1, 15);
+		rc_num = rc_num | address_post_swizzle_16.insert(io_bank, 15, 1, 2);
+	}
 
 	rc_num = rc_num | address_post_swizzle_16.extractPreserve(&mirror_mode_ad, 0, 16, 0);
 	FAPI_INF( "POST - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad);
@@ -688,7 +722,7 @@ ReturnCode mss_execute_zq_cal(
     ecmdDataBufferBase bank_buffer_8(8);
     rc_num = rc_num | bank_buffer_8.flushTo0();
     ecmdDataBufferBase activate_buffer_1(1);
-    rc_num = rc_num | activate_buffer_1.flushTo0();
+    rc_num = rc_num | activate_buffer_1.flushTo1();
     ecmdDataBufferBase rasn_buffer_1(1);
     rc_num = rc_num | rasn_buffer_1.flushTo1(); //For ZQCal rasn = 1; casn = 1; wen = 0;
     ecmdDataBufferBase casn_buffer_1(1);
@@ -741,7 +775,7 @@ ReturnCode mss_execute_zq_cal(
         rc.setEcmdError(rc_num);
         return rc;
     }
-    rc = fapiPutScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64);
+     rc = fapiPutScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64);
     if(rc) return rc;
 
     for(uint8_t dimm = 0; dimm < MAX_NUM_DIMM; dimm++)
@@ -764,6 +798,7 @@ ReturnCode mss_execute_zq_cal(
             rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1);
             if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
             rc = mss_execute_ccs_inst_array(i_target, NUM_POLL, 60);
+	    instruction_number = 0;
             if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
         }
     }
diff --git a/src/usr/hwpf/hwp/dram_training/mss_unmask_errors.H b/src/usr/hwpf/hwp/dram_training/mss_unmask_errors.H
index e779b9725..994650b30 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_unmask_errors.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_unmask_errors.H
@@ -1,11 +1,11 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_unmask_errors.H $          */
+/* $Source: src/usr/hwpf/hwp/utility_procedures/mss_unmask_errors.C $     */
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_unmask_errors.H,v 1.1 2012/09/05 21:04:20 gollub Exp $
+// $Id: mss_unmask_errors.C,v 1.3 2013/03/08 22:03:00 gollub Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -29,247 +29,2812 @@
 // Version:|   Date:  | Author: | Comment:
 //---------|----------|---------|-----------------------------------------------
 //   1.1   | 09/05/12 | gollub  | Created
-
-#ifndef _MSS_UNMASK_ERRORS_H
-#define _MSS_UNMASK_ERRORS_H
-
-/** @file  mss_unmask_errors.H
- *  @brief Utility functions to set action regs and unmask FIR bits 
- *         at the end of various mss IPL procedures.
- */
-
+//   1.2   | 01/31/13 | gollub  | Keeping maint UE/MPE, and MBSPA threshold
+//         |          |         | errors masked until mss_unmask_fetch_errors,
+//         |          |         | so they will be masked during memdiags, and
+//         |          |         | unmasked before scrub is started.
+//   1.3   | 03/08/13 | gollub  | Masking MBSPA[0] for DD1, and using MBSPA[8] instead.
 
 //------------------------------------------------------------------------------
 //  Includes
 //------------------------------------------------------------------------------
 
-#include <fapi.H>
-#include <ecmdDataBufferBase.H>
-
+#include <mss_unmask_errors.H>
+#include <cen_scom_addresses.H>
+using namespace fapi;
 
 
 //------------------------------------------------------------------------------
 // Constants and enums
 //------------------------------------------------------------------------------
+        
+
+//------------------------------------------------------------------------------
+// mss_unmask_inband_errors
+//------------------------------------------------------------------------------
+                                           
+fapi::ReturnCode mss_unmask_inband_errors( const fapi::Target & i_target,
+                                           fapi::ReturnCode i_bad_rc )
+                                           
+{
 
+    FAPI_INF("ENTER mss_unmask_inband_errors()"); 
+    
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmd_rc = 0;            
 
+    //*************************
+    //*************************
+    // MBS_FIR_REG
+    //*************************
+    //*************************
 
+    ecmdDataBufferBase l_mbs_fir_mask(64);
+    ecmdDataBufferBase l_mbs_fir_mask_or(64);    
+    ecmdDataBufferBase l_mbs_fir_mask_and(64);
+    ecmdDataBufferBase l_mbs_fir_action0(64);
+    ecmdDataBufferBase l_mbs_fir_action1(64);
+    
+    // Read mask 
+    l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }    
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
 
 
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
 
-//------------------------------------------------------------------------------
-// mss_unmask_inband_errors
-//------------------------------------------------------------------------------
+    l_ecmd_rc |= l_mbs_fir_action0.flushTo0();
+    l_ecmd_rc |= l_mbs_fir_action1.flushTo0();
+    l_ecmd_rc |= l_mbs_fir_mask_or.flushTo0();
+    l_ecmd_rc |= l_mbs_fir_mask_and.flushTo1();
 
+    // 0    host_protocol_error     channel checkstop   unmask
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(0);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(0);
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(0);
+    
+    // 1    int_protocol_error      channel checkstop   unmask
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(1);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(1);
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(1);
+    
+    // 2    invalid_address_error   channel checkstop   mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(2);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(2);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(2);
+
+    // 3    external_timeout        channel checkstop   mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(3);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(3);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(3);
+    
+    // 4    internal_timeout        channel checkstop   mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(4);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(4);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(4);
+
+    // 5    int_buffer_ce           recoverable         unmask
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(5);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(5);
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(5);
+
+    // 6    int_buffer_ue           recoverable         unmask
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(6);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(6);
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(6);
+
+    // 7    int_buffer_sue          recoverable         mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(7);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(7);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(7);
+
+    // 8    int_parity_error        channel checkstop   unmask
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(8); 
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(8); 
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(8);
+
+    // 9    cache_srw_ce            recoverable         mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(9);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(9);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(9);
+
+    // 10    cache_srw_ue           recoverable         mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(10);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(10);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(10);
+
+    // 11    cache_srw_sue          recoverable         mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(11);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(11);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(11);
+
+    // 12    cache_co_ce            recoverable         mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(12);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(12);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(12);
+
+    // 13    cache_co_ue            recoverable         mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(13);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(13);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(13);
+
+    // 14    cache_co_sue           recoverable         mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(14);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(14);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(14);
+
+    // 15    dir_ce                 recoverable         mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(15);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(15);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(15);
+
+    // 16    dir_ue                 channel checkstop   mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(16);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(16);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(16);
+
+    // 17    dir_member_deleted     recoverable         mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(17);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(17);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(17);
+
+    // 18    dir_all_members_deleted channel checkstop  mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(18);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(18);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(18);
+
+    // 19    lru_error               recoverable        mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(19);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(19);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(19);
+
+    // 20    eDRAM error             channel checkstop  mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(20);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(20);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(20);
+
+    // 21    emergency_throttle_set  recoverable        mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(21);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(21);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(21);
+
+    // 22    Host Inband Read Error  recoverable        mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(22);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(22);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(22);
+
+    // 23    Host Inband Write Error recoverable        mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(23);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(23);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(23);
+
+    // 24    OCC Inband Read Error   recoverable        mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(24);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(24);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(24);
+
+    // 25    OCC Inband Write Error  recoverable        mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(25);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(25);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(25);
+
+    // 26    srb_buffer_ce           recoverable        mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(26);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(26);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(26);
+
+    // 27    srb_buffer_ue           recoverable         mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(27);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(27);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(27);
+
+    // 28    srb_buffer_sue          recoverable         mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(28);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(28);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(28);
+
+    // 29    internal_scom_error     recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(29);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(29);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(29);
+
+    // 30    internal_scom_error_copy recoverable        mask (tbd)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(30);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(30);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(30);
+
+    // 31:63    Reserved                not implemented, so won't touch these
+    
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    // Write action0
+    l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_ACTION0_REG_0x02011406, l_mbs_fir_action0);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write action1
+    l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_ACTION1_REG_0x02011407, l_mbs_fir_action1);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    
+    // Write mask OR
+    l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_MASK_REG_OR_0x02011405, l_mbs_fir_mask_or); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_MASK_REG_AND_0x02011404, l_mbs_fir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_ACTION0_REG_0x02011406, l_mbs_fir_action0); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_ACTION1_REG_0x02011407, l_mbs_fir_action1); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+    
+    
+    FAPI_INF("EXIT mss_unmask_inband_errors()"); 
+
+    return i_bad_rc;
+}
 
-/**
- * @brief  To be called at the end of proc_cen_set_inband_addr.C
- *         Sets action regs and mask settings for inband errors to their 
- *         runtime settings.
- *
- * @param  i_target         Centaur target
- * @param  i_bad_rc         If proc_cen_set_inband_addr.C already has a bad rc
- *                          before it calls this function, we pass it in as 
- *                          i_bad_rc. If this function gets it's own bad local 
- *                          l_rc, i_bad_rc will be commited, and l_rc will be 
- *                          passed back as return value. Else if no l_rc, 
- *                          i_bad_rc will be be passed back as return value.
- * @return Non-SUCCESS if i_bad_rc Non_SUCCESS, or if internal function fails, 
- *         SUCCESS otherwise.
- */
-fapi::ReturnCode mss_unmask_inband_errors( const fapi::Target & i_target,
-                                           fapi::ReturnCode i_bad_rc );
 
 
 //------------------------------------------------------------------------------
 // mss_unmask_ddrphy_errors
 //------------------------------------------------------------------------------
+                                           
+fapi::ReturnCode mss_unmask_ddrphy_errors( const fapi::Target & i_target,
+                                           fapi::ReturnCode i_bad_rc )
+                                           
+{
 
+    FAPI_INF("ENTER mss_unmask ddrphy_errors()"); 
+    
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmd_rc = 0;            
+
+    //*************************
+    //*************************
+    // DDRPHY_FIR_REG
+    //*************************
+    //*************************
+
+    ecmdDataBufferBase l_ddrphy_fir_mask(64);
+    ecmdDataBufferBase l_ddrphy_fir_mask_or(64);
+    ecmdDataBufferBase l_ddrphy_fir_mask_and(64);        
+    ecmdDataBufferBase l_ddrphy_fir_action0(64);
+    ecmdDataBufferBase l_ddrphy_fir_action1(64);
+
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
 
-/**
- * @brief  To be called at the end of mss_ddr_phy_reset.C.
- *         Sets action regs and mask settings for ddr phy errors to their 
- *         runtime settings.
- *
- * @param  i_target         MBA target
- * @param  i_bad_rc         If mss_ddr_phy_reset.C already has a bad rc
- *                          before it calls this function, we pass it in as 
- *                          i_bad_rc. If this function gets it's own bad local 
- *                          l_rc, i_bad_rc will be commited, and l_rc will be 
- *                          passed back as return value. Else if no l_rc, 
- *                          i_bad_rc will be be passed back as return value.
- * @return Non-SUCCESS if i_bad_rc Non_SUCCESS, or if internal function fails, 
- *         SUCCESS otherwise.
- */
-fapi::ReturnCode mss_unmask_ddrphy_errors( const fapi::Target & i_target,
-                                           fapi::ReturnCode i_bad_rc );
+
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
+        
+    l_ecmd_rc |= l_ddrphy_fir_action0.flushTo0();
+    l_ecmd_rc |= l_ddrphy_fir_action1.flushTo0();
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.flushTo0();
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.flushTo0();
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.setBit(48,16);
+        
+    // 0:47 Reserved                not implemented, so won't touch these
+    
+    // 48   ddr0_fsm_ckstp          channel checkstop   unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(48);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(48);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(48);
+    
+    // 49   ddr0_parity_ckstp       channel checkstop   unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(49);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(49);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(49);
+
+    // 50   ddr0_calibration_error  recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(50);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(50);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(50);
+
+    // 51   ddr0_fsm_err            recoverable         unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(51);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(51);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(51);
+
+    // 52   ddr0_parity_err         recoverable         unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(52);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(52);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(52);
+
+    // 53   ddr01_fir_parity_err    recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(53);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(53);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(53);
+    
+    // 54   Reserved                recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(54);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(54);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(54);
+
+    // 55   Reserved                recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(55);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(55);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(55);
+
+    // 56   ddr1_fsm_ckstp          channel checkstop   unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(56);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(56);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(56);
+    
+    // 57   ddr1_parity_ckstp       channel checkstop   unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(57);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(57);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(57);
+
+    // 58   ddr1_calibration_error  recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(58);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(58);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(58);
+
+    // 59   ddr1_fsm_err            recoverable         unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(59);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(59);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(59);
+
+    // 60   ddr1_parity_err         recoverable         unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(60);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(60);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(60);
+
+    // 61   Reserved                recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(61);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(61);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(61);
+
+    // 62   Reserved                recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(62);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(62);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(62);
+
+    // 63   Reserved                recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(63);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(63);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(63);
+
+
+
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    // Write action0
+    l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION0_REG_0x800200960301143f, l_ddrphy_fir_action0);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write action1
+    l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION1_REG_0x800200970301143f, l_ddrphy_fir_action1);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    
+    // Write mask OR
+    l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_MASK_REG_OR_0x800200950301143f, l_ddrphy_fir_mask_or); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_MASK_REG_AND_0x800200940301143f, l_ddrphy_fir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION0_REG_0x800200960301143f, l_ddrphy_fir_action0); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION1_REG_0x800200970301143f, l_ddrphy_fir_action1); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, PHY01_DDRPHY_FIR_MASK_REG_0x800200930301143f, l_ddrphy_fir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+    
+    
+    //*************************
+    //*************************
+    // MBAFIR
+    //*************************
+    //*************************
+    
+    ecmdDataBufferBase l_mbafir_mask(64);
+    ecmdDataBufferBase l_mbafir_mask_or(64);
+    ecmdDataBufferBase l_mbafir_mask_and(64);
+    ecmdDataBufferBase l_mbafir_action0(64);
+    ecmdDataBufferBase l_mbafir_action1(64);
+            
+    
+    // Read mask
+    l_rc = fapiGetScom_w_retry(i_target,
+                               MBA01_MBAFIRMASK_0x03010603,
+                               l_mbafir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
+                
+    l_ecmd_rc |= l_mbafir_action0.flushTo0();
+    l_ecmd_rc |= l_mbafir_action1.flushTo0();
+    l_ecmd_rc |= l_mbafir_mask_or.flushTo0();
+    l_ecmd_rc |= l_mbafir_mask_and.flushTo1();
+
+
+    // 0	Invalid_Maint_Cmd           recoverable         masked (forever)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(0);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(0);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(0);
+    
+    // 1	Invalid_Maint_Address       recoverable         masked (forever)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(1);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(1);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(1);
+
+    // 2	Multi_address_Maint_timeout recoverable         masked (until mss_unmask_maint_errors)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(2);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(2);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(2);
+
+    // 3	Internal_fsm_error          recoverable         unmask
+    l_ecmd_rc |= l_mbafir_action0.clearBit(3);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(3);
+    l_ecmd_rc |= l_mbafir_mask_and.clearBit(3);
+
+    // 4	MCBIST_Error                recoverable         mask (forever)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(4);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(4);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(4);
+    
+    // 5	scom_cmd_reg_pe             recoverable         unmask
+    l_ecmd_rc |= l_mbafir_action0.clearBit(5);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(5);
+    l_ecmd_rc |= l_mbafir_mask_and.clearBit(5);
+
+    // 6	channel_chkstp_err          channel checkstop   unmask
+    l_ecmd_rc |= l_mbafir_action0.clearBit(6);            
+    l_ecmd_rc |= l_mbafir_action1.clearBit(6);
+    l_ecmd_rc |= l_mbafir_mask_and.clearBit(6);
+
+    // 7	wrd_caw2_data_ce_ue_err     recoverable         masked (until mss_unmask_maint_errors)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(7);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(7);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(7);
+
+    // 8:14	RESERVED                    recoverable         mask (forever)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(8,7);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(8,7);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(8,7);
+
+    // 15	internal scom error         recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(15);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(15);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(15);
+
+    // 16	internal scom error clone   recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(16);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(16);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(16);
+
+
+    // 17:63 RESERVED           not implemented, so won't touch these
+
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    // Write action0
+    l_rc = fapiPutScom_w_retry(i_target,
+                               MBA01_MBAFIRACT0_0x03010606,
+                               l_mbafir_action0);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write action1
+    l_rc = fapiPutScom_w_retry(i_target,
+                               MBA01_MBAFIRACT1_0x03010607,
+                               l_mbafir_action1);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    
+    // Write mask OR
+    l_rc = fapiPutScom_w_retry(i_target,
+                               MBA01_MBAFIRMASK_OR_0x03010605,
+                               l_mbafir_mask_or); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target,
+                               MBA01_MBAFIRMASK_AND_0x03010604,
+                               l_mbafir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target,
+                               MBA01_MBAFIRACT0_0x03010606,
+                               l_mbafir_action0); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target,
+                               MBA01_MBAFIRACT1_0x03010607,
+                               l_mbafir_action1); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target,
+                               MBA01_MBAFIRMASK_0x03010603,
+                               l_mbafir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+    
+    
+    FAPI_INF("EXIT mss_unmask_ddrphy_errors()"); 
+
+    return i_bad_rc;
+}
 
 
 //------------------------------------------------------------------------------
 // mss_unmask_draminit_errors
 //------------------------------------------------------------------------------
+                                           
+fapi::ReturnCode mss_unmask_draminit_errors( const fapi::Target & i_target,
+                                             fapi::ReturnCode i_bad_rc )
+                                           
+{
 
+    FAPI_INF("ENTER mss_unmask_draminit_errors()"); 
+    
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmd_rc = 0;            
 
-/**
- * @brief  To be called at the end of mss_draminit.C.
- *         Sets MBACALFIR action regs to their runtime settings, and unmasks
- *         errors that are valid for PRD to handle after mss_draminit procedure.
- *
- * @param  i_target         MBA target
- * @param  i_bad_rc         If mss_draminit.C already has a bad rc
- *                          before it calls this function, we pass it in as 
- *                          i_bad_rc. If this function gets it's own bad local 
- *                          l_rc, i_bad_rc will be commited, and l_rc will be 
- *                          passed back as return value. Else if no l_rc, 
- *                          i_bad_rc will be be passed back as return value.
- * @return Non-SUCCESS if i_bad_rc Non_SUCCESS, or if internal function fails, 
- *         SUCCESS otherwise.
- */
-fapi::ReturnCode mss_unmask_draminit_errors( const fapi::Target & i_target,
-                                             fapi::ReturnCode i_bad_rc );
+    //*************************
+    //*************************
+    // MBACALFIR
+    //*************************
+    //*************************
+
+    ecmdDataBufferBase l_mbacalfir_mask(64);
+    ecmdDataBufferBase l_mbacalfir_mask_or(64);
+    ecmdDataBufferBase l_mbacalfir_mask_and(64);        
+    ecmdDataBufferBase l_mbacalfir_action0(64);
+    ecmdDataBufferBase l_mbacalfir_action1(64);
+
+
+    // Read mask
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
+        
+    l_ecmd_rc |= l_mbacalfir_action0.flushTo0();
+    l_ecmd_rc |= l_mbacalfir_action1.flushTo0();
+    l_ecmd_rc |= l_mbacalfir_mask_or.flushTo0();
+    l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1();        
+    
+    // 0	MBA Recoverable Error       recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(0);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(0);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(0);
+
+    // 1	MBA Nonrecoverable Error    channel checkstop   mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(1);            
+    l_ecmd_rc |= l_mbacalfir_action1.clearBit(1);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(1);
+
+    // 2	Refresh Overrun             recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(2);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(2);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(2);
+
+    // 3	WAT error                   recoverable         mask (forever)
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(3);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(3);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(3);
+
+    // 4	RCD Parity Error 0          recoverable         unmask (only if set)
+    // TODO: Unmask, only if set, only if ISD DIMM
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(4);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(4);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(4);
+
+    // 5	ddr0_cal_timeout_err        recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(5);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(5);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(5);
+
+    // 6	ddr1_cal_timeout_err        recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(6);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(6);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(6);
+
+    // 7	RCD Parity Error 1          recoverable         unmask (only if set)
+    // TODO: Unmask, only if set, only if ISD DIMM
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(7);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(7);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(7);
+
+
+    // 8	mbx to mba par error        channel checkstop   mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(8);            
+    l_ecmd_rc |= l_mbacalfir_action1.clearBit(8);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(8);
+
+    // 9	mba_wrd ue                  recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(9);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(9);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(9);
+
+    // 10	mba_wrd ce                  recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(10);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(10);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(10);
+
+    // 11	mba_maint ue                recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(11);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(11);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(11);
+
+    // 12	mba_maint ce                recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(12);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(12);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(12);
+
+    // 13	ddr_cal_reset_timeout       channel checkstop   mask
+    // TODO: Leaving masked until I find proper spot to unmask this
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(13);            
+    l_ecmd_rc |= l_mbacalfir_action1.clearBit(13);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(13);
+
+    // 14	wrq_data_ce                 recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(14);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(14);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(14);
+
+    // 15	wrq_data_ue                 recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(15);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(15);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(15);
+
+    // 16	wrq_data_sue                recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(16);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(16);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(16);
+
+    // 17	wrq_rrq_hang_err            recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(17);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(17);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(17);
+
+    // 18	sm_1hot_err                 recoverable         unmask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(18);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(18);
+    l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(18);
+
+    // 19	wrd_scom_error              recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(19);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(19);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(19);
+
+    // 20	internal_scom_error         recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(20);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(20);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(20);
+
+    // 21	internal_scom_error_copy    recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(21);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(21);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(21);
+
+    // 22-63	Reserved            not implemented, so won't touch these          
+
+
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    // Write action0
+    l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_ACTION0_0x03010406, l_mbacalfir_action0);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write action1
+    l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_ACTION1_0x03010407, l_mbacalfir_action1);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    
+    // Write mask OR
+    l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_OR_0x03010405, l_mbacalfir_mask_or); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_AND_0x03010404, l_mbacalfir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_ACTION0_0x03010406, l_mbacalfir_action0); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_ACTION1_0x03010407, l_mbacalfir_action1); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+    
+    
+    FAPI_INF("EXIT mss_unmask_draminit_errors()"); 
+
+    return i_bad_rc;
+}
 
 
 //------------------------------------------------------------------------------
 // mss_unmask_draminit_training_errors
 //------------------------------------------------------------------------------
+                                           
+fapi::ReturnCode mss_unmask_draminit_training_errors( 
+                                             const fapi::Target & i_target,
+                                             fapi::ReturnCode i_bad_rc )
+                                           
+{
 
+    FAPI_INF("ENTER mss_unmask_draminit_training_errors()"); 
+    
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmd_rc = 0;            
 
-/**
- * @brief  To be called at the end of mss_draminit_training.C.
- *         Unmasks MBACALFIR errors that are valid for PRD to handle after
- *         mss_draminit_training procedure.
- *
- * @param  i_target         MBA target
- * @param  i_bad_rc         If mss_draminit_training.C already has a bad rc
- *                          before it calls this function, we pass it in as 
- *                          i_bad_rc. If this function gets it's own bad local 
- *                          l_rc, i_bad_rc will be commited, and l_rc will be 
- *                          passed back as return value. Else if no l_rc, 
- *                          i_bad_rc will be be passed back as return value.
- * @return Non-SUCCESS if i_bad_rc Non_SUCCESS, or if internal function fails, 
- *         SUCCESS otherwise.
- */
-fapi::ReturnCode mss_unmask_draminit_training_errors( 
-                                            const fapi::Target & i_target,
-                                            fapi::ReturnCode i_bad_rc );
+    //*************************
+    //*************************
+    // MBACALFIR
+    //*************************
+    //*************************
+
+    ecmdDataBufferBase l_mbacalfir_mask(64);
+    ecmdDataBufferBase l_mbacalfir_mask_and(64);
+
+    // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been
+    // called, which has already set the MBACALFIR action regs to their runtime
+    // values, so no need to touch the action regs here.
+
+    // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been
+    // called, which has already unmasked the approproiate MBACALFIR errors
+    // following mss_draminit. So all we will do here is unmask a few more
+    // errors that would be considered valid after the mss_draminit_training
+    // procedure. 
+    
+
+    // Read mask
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
+                
+    l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1();        
+        
+    // 0	MBA Recoverable Error       recoverable         umask
+    l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(0);
+
+    // 4	RCD Parity Error 0          recoverable         unmask (only if set)
+    // TODO: Unmask, only if set, only if ISD DIMM
+
+    // 7	RCD Parity Error 1          recoverable         unmask (only if set)
+    // TODO: Unmask, only if set, only if ISD DIMM
+
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_AND_0x03010404, l_mbacalfir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+    
+    
+    FAPI_INF("EXIT mss_unmask_draminit_training_errors()"); 
+
+    return i_bad_rc;
+}
 
 
 //------------------------------------------------------------------------------
 // mss_unmask_draminit_training_advanced_errors
 //------------------------------------------------------------------------------
+                                           
+fapi::ReturnCode mss_unmask_draminit_training_advanced_errors( 
+                                             const fapi::Target & i_target,
+                                             fapi::ReturnCode i_bad_rc )
+                                           
+{
 
+    FAPI_INF("ENTER mss_unmask_draminit_training_advanced_errors()"); 
+    
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmd_rc = 0;            
+
+    //*************************
+    //*************************
+    // MBACALFIR
+    //*************************
+    //*************************
+
+    ecmdDataBufferBase l_mbacalfir_mask(64);
+    ecmdDataBufferBase l_mbacalfir_mask_and(64);
+
+    // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been
+    // called, which has already set the MBACALFIR action regs to their runtime
+    // values, so no need to touch the action regs here.
+
+    // NOTE: In the IPL sequence, mss_unmask_draminit_errors and 
+    // mss_unmask_draminit_training has already been
+    // called, which has already unmasked the approproiate MBACALFIR errors
+    // following mss_draminit and mss_draminit_training. So all we will do here
+    // is unmask a few more errors that would be considered valid after the
+    // mss_draminit_training_advanced procedure. 
+    
+
+    // Read mask
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
+                
+    l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1();            
+    
+    // 4	RCD Parity Error 0          recoverable         unmask 
+    // TODO: Unmask, only if ISD DIMM
+
+    // 7	RCD Parity Error 1          recoverable         unmask 
+    // TODO: Unmask, only if ISD DIMM
+
+    // 8	mbx to mba par error        channel checkstop   unmask
+    l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(8);
+
+    // 11	mba_maint ue                recoverable         unmask
+    l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(11);
+
+    // 12	mba_maint ce                recoverable         unmask
+    l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(12);
+
+    // 17	wrq_rrq_hang_err            recoverable         unmask
+    l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(17);
+
+
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_AND_0x03010404, l_mbacalfir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************ 
+    
+
+    //*************************
+    //*************************
+    // MBSFIR
+    //*************************
+    //*************************    
+    
+    fapi::Target l_targetCentaur;
+    uint8_t l_mbaPosition;             // 0 = mba01, 1 = mba23
+
+    uint32_t l_mbsfir_mask_address[2]={
+    // port0/1                       port2/3
+    MBS01_MBSFIRMASK_0x02011603,     MBS23_MBSFIRMASK_0x02011703};
+
+    uint32_t l_mbsfir_mask_or_address[2]={
+    // port0/1                       port2/3
+    MBS01_MBSFIRMASK_OR_0x02011605,  MBS23_MBSFIRMASK_OR_0x02011705};
+
+    uint32_t l_mbsfir_mask_and_address[2]={
+    // port0/1                       port2/3
+    MBS01_MBSFIRMASK_AND_0x02011604, MBS23_MBSFIRMASK_AND_0x02011704};
+
+    uint32_t l_mbsfir_action0_address[2]={
+    // port0/1                       port2/3
+    MBS01_MBSFIRACT0_0x02011606,     MBS23_MBSFIRACT0_0x02011706};
+
+    uint32_t l_mbsfir_action1_address[2]={
+    // port0/1                       port2/3
+    MBS01_MBSFIRACT1_0x02011607,     MBS23_MBSFIRACT1_0x02011707};
+
+    ecmdDataBufferBase l_mbsfir_mask(64);
+    ecmdDataBufferBase l_mbsfir_mask_or(64);
+    ecmdDataBufferBase l_mbsfir_mask_and(64);        
+    ecmdDataBufferBase l_mbsfir_action0(64);
+    ecmdDataBufferBase l_mbsfir_action1(64);
+
+    // Get Centaur target for the given MBA
+    l_rc = fapiGetParentChip(i_target, l_targetCentaur);
+    if(l_rc)
+    {
+        FAPI_ERR("Error getting Centaur parent target for the given MBA");
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    
+    // Get MBA position: 0 = mba01, 1 = mba23
+    l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition);
+    if(l_rc)
+    {
+        FAPI_ERR("Error getting MBA position");
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);                
+        return l_rc;
+    }    
+    
+    // Read mask
+    l_rc = fapiGetScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_mask_address[l_mbaPosition], 
+                               l_mbsfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
+                
+    l_ecmd_rc |= l_mbsfir_action0.flushTo0();
+    l_ecmd_rc |= l_mbsfir_action1.flushTo0();
+    l_ecmd_rc |= l_mbsfir_mask_or.flushTo0();
+    l_ecmd_rc |= l_mbsfir_mask_and.flushTo1();
+
+    // 0	scom_par_errors             recoverable         unmask
+    l_ecmd_rc |= l_mbsfir_action0.clearBit(0);            
+    l_ecmd_rc |= l_mbsfir_action1.setBit(0);
+    l_ecmd_rc |= l_mbsfir_mask_and.clearBit(0);
+
+    // 1	mbx_par_errors              channel checkstop   unmask
+    l_ecmd_rc |= l_mbsfir_action0.clearBit(1);            
+    l_ecmd_rc |= l_mbsfir_action1.clearBit(1);
+    l_ecmd_rc |= l_mbsfir_mask_and.clearBit(1);
+
+    // 2:14	RESERVED                    recoverable         mask (forever)
+    l_ecmd_rc |= l_mbsfir_action0.clearBit(2,13);            
+    l_ecmd_rc |= l_mbsfir_action1.setBit(2,13);
+    l_ecmd_rc |= l_mbsfir_mask_or.setBit(2,13);
+
+    // 15	internal scom error         recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbsfir_action0.clearBit(15);            
+    l_ecmd_rc |= l_mbsfir_action1.setBit(15);
+    l_ecmd_rc |= l_mbsfir_mask_or.setBit(15);
+
+    // 16	internal scom error clone   recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbsfir_action0.clearBit(16);            
+    l_ecmd_rc |= l_mbsfir_action1.setBit(16);
+    l_ecmd_rc |= l_mbsfir_mask_or.setBit(16);
+
+    // 17:63 RESERVED           not implemented, so won't touch these
+    
+        
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    // Write action0
+    l_rc = fapiPutScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_action0_address[l_mbaPosition], 
+                               l_mbsfir_action0); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write action1
+    l_rc = fapiPutScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_action1_address[l_mbaPosition], 
+                               l_mbsfir_action1); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    
+    // Write mask OR
+    l_rc = fapiPutScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_mask_or_address[l_mbaPosition], 
+                               l_mbsfir_mask_or); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_mask_and_address[l_mbaPosition], 
+                               l_mbsfir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_action0_address[l_mbaPosition], 
+                               l_mbsfir_action0); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    l_rc = fapiGetScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_action1_address[l_mbaPosition], 
+                               l_mbsfir_action1); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    l_rc = fapiGetScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_mask_address[l_mbaPosition], 
+                               l_mbsfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+   
+    
+    FAPI_INF("EXIT mss_unmask_draminit_training_advanced_errors()"); 
+
+    return i_bad_rc;
+}
 
-/**
- * @brief  To be called at the end of mss_draminit_training_advanced.C.
- *         Unmasks MBACALFIR errors that are valid for PRD to handle after
- *         mss_draminit_training_advanced procedure.
- *
- * @param  i_target         MBA target
- * @param  i_bad_rc         If mss_draminit_training_advanced.C already has a 
- *                          bad rc before it calls this function, we pass it in 
- *                          as i_bad_rc. If this function gets it's own bad  
- *                          local l_rc, i_bad_rc will be commited, and l_rc will 
- *                          be passed back as return value. Else if no l_rc, 
- *                          i_bad_rc will be be passed back as return value.
- * @return Non-SUCCESS if i_bad_rc Non_SUCCESS, or if internal function fails, 
- *         SUCCESS otherwise.
- */
-fapi::ReturnCode mss_unmask_draminit_training_advanced_errors( 
-                                            const fapi::Target & i_target,
-                                            fapi::ReturnCode i_bad_rc );
 
 
 //------------------------------------------------------------------------------
 // mss_unmask_maint_errors
 //------------------------------------------------------------------------------
+                                           
+fapi::ReturnCode mss_unmask_maint_errors(const fapi::Target & i_target,
+                                         fapi::ReturnCode i_bad_rc )
+                                           
+{
+
+    // Target: Centaur
+    
+    FAPI_INF("ENTER mss_unmask_maint_errors()"); 
+    
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmd_rc = 0; 
+    std::vector<fapi::Target> l_mbaChiplets;
+    uint8_t l_mbaPosition;             // 0 = mba01, 1 = mba23
+
+    ecmdDataBufferBase l_mbacalfir_mask(64);
+    ecmdDataBufferBase l_mbacalfir_mask_and(64);    
+
+    ecmdDataBufferBase l_mbafir_mask(64);
+    ecmdDataBufferBase l_mbafir_mask_and(64);
+           
+    ecmdDataBufferBase l_mbaspa_mask(64);
+
+    uint32_t l_mbeccfir_mask_address[2]={
+    // port0/1                            port2/3
+    MBS_ECC0_MBECCFIR_MASK_0x02011443,    MBS_ECC1_MBECCFIR_MASK_0x02011483};
+
+    uint32_t l_mbeccfir_mask_or_address[2]={
+    // port0/1                            port2/3
+    MBS_ECC0_MBECCFIR_MASK_OR_0x02011445, MBS_ECC1_MBECCFIR_MASK_OR_0x02011485};
+
+    uint32_t l_mbeccfir_mask_and_address[2]={
+    // port0/1                            port2/3
+    MBS_ECC0_MBECCFIR_MASK_AND_0x02011444,MBS_ECC1_MBECCFIR_MASK_AND_0x02011484};
+
+    uint32_t l_mbeccfir_action0_address[2]={
+    // port0/1                            port2/3
+    MBS_ECC0_MBECCFIR_ACTION0_0x02011446, MBS_ECC1_MBECCFIR_ACTION0_0x02011486};
+
+    uint32_t l_mbeccfir_action1_address[2]={
+    // port0/1                            port2/3
+    MBS_ECC0_MBECCFIR_ACTION1_0x02011447, MBS_ECC1_MBECCFIR_ACTION1_0x02011487};
+
+    ecmdDataBufferBase l_mbeccfir_mask(64);
+    ecmdDataBufferBase l_mbeccfir_mask_or(64);
+    ecmdDataBufferBase l_mbeccfir_mask_and(64);
+    ecmdDataBufferBase l_mbeccfir_action0(64);
+    ecmdDataBufferBase l_mbeccfir_action1(64);
+
+
+
+    // Get associated functional MBAs on this centaur
+    l_rc = fapiGetChildChiplets(i_target,
+                                fapi::TARGET_TYPE_MBA_CHIPLET,
+                                l_mbaChiplets);
+    if(l_rc)
+    {
+        FAPI_ERR("Error getting functional MBAs on this Centaur");
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);                
+        return l_rc;
+    }    
+
+    // Loop through functional MBAs on this Centaur
+    for (uint32_t i=0; i < l_mbaChiplets.size(); i++)
+    {
+
+        // Get MBA position: 0 = mba01, 1 = mba23
+        l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mbaChiplets[i], l_mbaPosition);
+        if(l_rc)
+        {
+            FAPI_ERR("Error getting MBA position");
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);                
+            return l_rc;
+        }    
+
+
+
+
+        //*************************
+        //*************************
+        // MBACALFIR
+        //*************************
+        //*************************    
+
+
+        // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been
+        // called, which has already set the MBACALFIR action regs to their runtime
+        // values, so no need to touch the action regs here.
+
+        // NOTE: In the IPL sequence, mss_unmask_draminit_errors,
+        // mss_unmask_draminit_training and mss_unmask_draminit_training_advanced
+        // have already been called, which have already unmasked the approproiate
+        // MBACALFIR errors following mss_draminit, mss_draminit_training, and
+        // mss_unmask_draminit_training_advanced. So all we will do here
+        // is unmask a few more errors that would be considered valid after the
+        // mss_draminit_mc procedure. 
+    
+        // Read mask
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBACALFIR_MASK_0x03010403,
+                                   l_mbacalfir_mask);       
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+        
+        // TODO: Here is where I could clear bits that were bogus, before I unmask 
+        //       them. But typically we are expecting the bit set at this point
+        //       to be valid errors for PRD to log.
+
+
+        //(Action0, Action1, Mask)
+        //
+        // (0,0,0) = checkstop
+        // (0,1,0) = recoverable error
+        // (1,0,0) = report unused
+        // (1,1,0) = machine check
+        // (x,x,1) = error is masked
+        
+        l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1();            
+                    
+        // 1	MBA Nonrecoverable Error    channel checkstop   unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(1);
+
+        // 2	Refresh Overrun             recoverable         unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(2);
+        
+        // 5	ddr0_cal_timeout_err        recoverable         unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(5);
+
+        // 6	ddr1_cal_timeout_err        recoverable         unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(6);
+        
+        if(l_ecmd_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }                                                                              
+
+        // Write mask AND
+        l_rc = fapiPutScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBACALFIR_MASK_AND_0x03010404,
+                                   l_mbacalfir_mask_and); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************    
+        // DEBUG: read them all back to verify
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBACALFIR_MASK_0x03010403,
+                                   l_mbacalfir_mask);       
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************ 
+    
+
+        //*************************
+        //*************************
+        // MBAFIR
+        //*************************
+        //*************************    
+        
+        // NOTE: In the IPL sequence, mss_unmask_ddr_phy_errors has already been
+        // called, which has already set the MBAFIR action regs to their runtime
+        // values, so no need to touch the action regs here.
+
+        // NOTE: In the IPL sequence, mss_unmask_ddr_phy_errors,
+        // has already been called, which has already unmasked the approproiate
+        // MBAFIR errors following mss_ddr_phy_reset. So all we will do here
+        // is unmask a few more errors that would be considered valid after the
+        // mss_draminit_mc procedure. 
+        
+        // Read mask
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBAFIRMASK_0x03010603,
+                                   l_mbafir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+        
+        // TODO: Here is where I could clear bits that were bogus, before I unmask 
+        //       them. But typically we are expecting the bit set at this point
+        //       to be valid errors for PRD to log.
+
+
+        //(Action0, Action1, Mask)
+        //
+        // (0,0,0) = checkstop
+        // (0,1,0) = recoverable error
+        // (1,0,0) = report unused
+        // (1,1,0) = machine check
+        // (x,x,1) = error is masked
+                    
+        l_ecmd_rc |= l_mbafir_mask_and.flushTo1();
+
+        // 2	Multi_address_Maint_timeout recoverable         unmask
+        l_ecmd_rc |= l_mbafir_mask_and.clearBit(2);
+
+
+        // 7	wrd_caw2_data_ce_ue_err     recoverable         unmask
+        l_ecmd_rc |= l_mbafir_mask_and.clearBit(7);
+
+        if(l_ecmd_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }                                                                              
+
+        // Write mask AND
+        l_rc = fapiPutScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBAFIRMASK_AND_0x03010604,
+                                   l_mbafir_mask_and); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+
+        //************************************************    
+        // DEBUG: read them all back to verify
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBAFIRMASK_0x03010603,
+                                   l_mbafir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************    
+
+
+        //*************************
+        //*************************
+        // MBASPA
+        //*************************
+        //*************************
+        
+                
+        // Read mask
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBSPAMSKQ_0x03010614,
+                                   l_mbaspa_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+        
+        // TODO: Here is where I could clear bits that were bogus, before I unmask 
+        //       them. But typically we are expecting the bit set at this point
+        //       to be valid errors for PRD to log.
+
+
+        // 0	Command_Complete                             mask (broken on DD1)
+        // NOTE: This bit broken in DD1.
+        // It can be made to come on when cmd completes clean, or make to come
+        // on when cmd stops on error, but can't be set to do both. 
+        l_ecmd_rc |= l_mbaspa_mask.setBit(0);            
+
+        // 1	Hard_CE_ETE_Attn                             mask (until after memdiags)
+        // NOTE: FW memdiags needs this masked because they want to wait till
+        // cmd gets to end of rank before getting any attention.
+        // NOTE: Hards counted during super fast read, but can't be called 
+        // true hard CEs since super fast read doesn't write back and read again.
+        l_ecmd_rc |= l_mbaspa_mask.setBit(1);            
+
+        // 2	Soft_CE_ETE_Attn                             mask (until after memdiags)
+        // NOTE: FW memdiags needs this masked because they want to wait till
+        // cmd gets to end of rank before getting any attention.
+        // NOTE: Softs not counted during super fast read.
+        l_ecmd_rc |= l_mbaspa_mask.setBit(2);            
+
+        // 3	Intermittent_ETE_Attn                        mask (until after memdiags)
+        // NOTE: FW memdiags needs this masked because they want to wait till
+        // cmd gets to end of rank before getting any attention.
+        // NOTE: Intermittents not counted during super fast read.
+        l_ecmd_rc |= l_mbaspa_mask.setBit(3);            
+
+        // 4	RCE_ETE_Attn                                 mask (until after memdiags)
+        // NOTE: FW memdiags needs this masked because they want to wait till
+        // cmd gets to end of rank before getting any attention.
+        // NOTE: RCEs not counted during super fast read.
+        l_ecmd_rc |= l_mbaspa_mask.setBit(4);            
+
+        // 5	Emergency_Throttle_Attn                      masked (forever)
+        l_ecmd_rc |= l_mbaspa_mask.setBit(5);            
+
+        // 6	Firmware_Attn0                               masked (forever)
+        l_ecmd_rc |= l_mbaspa_mask.setBit(6);            
+
+        // 7	Firmware_Attn1                               masked (forever)
+        l_ecmd_rc |= l_mbaspa_mask.setBit(7);            
+
+        // 8	wat_debug_attn                               unmasked
+        // NOTE: DD1 workaround for broken bit 0. This bit will come on whenever 
+        // cmd stops, either stop clean or stop on error.
+        l_ecmd_rc |= l_mbaspa_mask.clearBit(8);            
+
+        // 9	Spare_Attn1                                  masked (forever)
+        l_ecmd_rc |= l_mbaspa_mask.setBit(9);            
+
+        // 10	MCBIST_Done                                  masked (forever)
+        l_ecmd_rc |= l_mbaspa_mask.setBit(10);            
+
+        // 11:63 RESERVED     not implemented, so won't touch these
+                    
+
+        if(l_ecmd_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }                                                                              
+        
+        // Write mask
+        l_rc = fapiPutScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBSPAMSKQ_0x03010614,
+                                   l_mbaspa_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************    
+        // DEBUG: read them all back to verify
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBSPAMSKQ_0x03010614,
+                                   l_mbaspa_mask);
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+        //************************************************    
+
+
+
+        //*************************
+        //*************************
+        // MBECCFIR
+        //*************************
+        //*************************    
+        
+        // Get MBA position: 0 = mba01, 1 = mba23
+        l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mbaChiplets[i], l_mbaPosition);
+        if(l_rc)
+        {
+            FAPI_ERR("Error getting MBA position");
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);                
+            return l_rc;
+        }    
+        
+        // Read mask
+        l_rc = fapiGetScom_w_retry(i_target, 
+                                   l_mbeccfir_mask_address[l_mbaPosition], 
+                                   l_mbeccfir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+        
+        // TODO: Here is where I could clear bits that were bogus, before I unmask 
+        //       them. But typically we are expecting the bit set at this point
+        //       to be valid errors for PRD to log.
+
+
+        //(Action0, Action1, Mask)
+        //
+        // (0,0,0) = checkstop
+        // (0,1,0) = recoverable error
+        // (1,0,0) = report unused
+        // (1,1,0) = machine check
+        // (x,x,1) = error is masked
+                    
+        l_ecmd_rc |= l_mbeccfir_action0.flushTo0();
+        l_ecmd_rc |= l_mbeccfir_action1.flushTo0();
+        l_ecmd_rc |= l_mbeccfir_mask_or.flushTo0();
+        l_ecmd_rc |= l_mbeccfir_mask_and.flushTo1();
+
+        // 0:7	Memory MPE Rank 0:7         recoverable         mask (until mainline traffic)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(0,8);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(0,8);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(0,8);
+
+        // 8:15	Reserved                    recoverable         mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(8,8);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(8,8);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(8,8);
+        
+        // 16	Memory NCE                  recoverable         mask (until mainline traffic)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(16);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(16);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(16);
+
+        // 17	Memory RCE                  recoverable         mask (until mainline traffic)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(17);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(17);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(17);
+
+        // 18	Memory SUE                  recoverable         mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(18);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(18);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(18);
+
+        // 19	Memory UE                   recoverable         mask (until mainline traffic)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(19);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(19);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(19);
+
+        // 20:27	Maint MPE Rank 0:7      recoverable         mask (until after memdiags)
+        // NOTE: FW memdiags needs this masked because they want to wait till
+        // cmd gets to end of rank before getting any attention.
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(20,8);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(20,8);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(20,8);
+
+        // 28:35	Reserved                recoverable         mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(28,8);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(28,8);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(28,8);
+        
+        // 36	Maintenance NCE             recoverable         mask (forever)
+        // NOTE: PRD planning to use maint CE thresholds instead.
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(36);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(36);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(36);
+
+        // 37	Maintenance SCE             recoverable         mask (forever)
+        // NOTE: Don't care if symbol still bad after it's symbol marked.
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(37);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(37);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(37);
+
+        // 38	Maintenance MCE             recoverable         mask (forever)
+        // NOTE: PRD plans to check manually as part of verify chip mark procedure.
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(38);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(38);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(38);
+
+        // 39	Maintenance RCE             recoverable         mask (forever)
+        // NOTE: PRD planning to use maint RCE thresholds instead.
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(39);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(39);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(39);
+
+        // 40	Maintenance SUE             recoverable         mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(40);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(40);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(40);
+
+        // 41	Maintenance UE              recoverable         mask (until after memdiags)
+        // NOTE: FW memdiags needs this masked because they want to wait till
+        // cmd gets to end of rank before getting any attention.
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(41);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(41);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(41);
+
+        // 42	MPE during maintenance mark mode  recoverable   mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(42);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(42);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(42);
+
+        // 43	Prefetch Memory UE          recoverable         mask (until mainline traffic)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(43);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(43);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(43);
+
+        // 44	Memory RCD parity error     recoverable         mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(44);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(44);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(44);
+
+        // 45	Maint RCD parity error.     recoverable         mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(45);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(45);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(45);
+
+        // 46	Recoverable reg parity      recoverable         unmask
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(46);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(46);
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(46);
+
+
+        // 47	Unrecoverable reg parity    channel checkstop   unmask
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(47);            
+        l_ecmd_rc |= l_mbeccfir_action1.clearBit(47);
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(47);
+
+        // 48	Maskable reg parity error   recoverable         mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(48);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(48);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(48);
+
+        // 49	ecc datapath parity error   channel checkstop   unmask
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(49);            
+        l_ecmd_rc |= l_mbeccfir_action1.clearBit(49);
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(49);
+
+        // 50	internal scom error         recovereble         mask (tbd)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(50);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(50);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(50);
+
+        // 51	internal scom error clone   recovereble         mask (tbd)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(51);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(51);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(51);
+
+        // 52:63	Reserved    not implemented, so won't touch these
+
+
+        
+            
+        if(l_ecmd_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }                                                                              
+
+        // Write action0
+        l_rc = fapiPutScom_w_retry(i_target, 
+                                   l_mbeccfir_action0_address[l_mbaPosition], 
+                                   l_mbeccfir_action0); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        // Write action1
+        l_rc = fapiPutScom_w_retry(i_target, 
+                                   l_mbeccfir_action1_address[l_mbaPosition], 
+                                   l_mbeccfir_action1); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        
+        // Write mask OR
+        l_rc = fapiPutScom_w_retry(i_target, 
+                                   l_mbeccfir_mask_or_address[l_mbaPosition], 
+                                   l_mbeccfir_mask_or); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        // Write mask AND
+        l_rc = fapiPutScom_w_retry(i_target, 
+                                   l_mbeccfir_mask_and_address[l_mbaPosition], 
+                                   l_mbeccfir_mask_and); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+
+        //************************************************    
+        // DEBUG: read them all back to verify
+        l_rc = fapiGetScom_w_retry(i_target, 
+                                   l_mbeccfir_action0_address[l_mbaPosition], 
+                                   l_mbeccfir_action0); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        l_rc = fapiGetScom_w_retry(i_target, 
+                                   l_mbeccfir_action1_address[l_mbaPosition], 
+                                   l_mbeccfir_action1); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        l_rc = fapiGetScom_w_retry(i_target, 
+                                   l_mbeccfir_mask_address[l_mbaPosition], 
+                                   l_mbeccfir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************    
+
+   } // End for loop through functional MBAs on this Centaur
+    
+    FAPI_INF("EXIT mss_unmask_maint_errors()"); 
+
+    return i_bad_rc;
+}
 
 
-/**
- * @brief  To be called at the end of mss_draminit_mc.C.
- *         Sets action regs and unmasks maint errors prior to the maint logic
- *         being used in memdiags so that PRD will be able to handle them 
- *         if they happen during memdiags.
- *
- * @param  i_target         MBA target
- * @param  i_bad_rc         If mss_draminit_mc already has a 
- *                          bad rc before it calls this function, we pass it in 
- *                          as i_bad_rc. If this function gets it's own bad  
- *                          local l_rc, i_bad_rc will be commited, and l_rc will 
- *                          be passed back as return value. Else if no l_rc, 
- *                          i_bad_rc will be be passed back as return value.
- * @return Non-SUCCESS if i_bad_rc Non_SUCCESS, or if internal function fails, 
- *         SUCCESS otherwise.
- */
-fapi::ReturnCode mss_unmask_maint_errors(const fapi::Target & i_target,
-                                         fapi::ReturnCode i_bad_rc );
 
 
 //------------------------------------------------------------------------------
 // mss_unmask_fetch_errors
 //------------------------------------------------------------------------------
+                                           
+fapi::ReturnCode mss_unmask_fetch_errors(const fapi::Target & i_target,
+                                         fapi::ReturnCode i_bad_rc )
+                                           
+{
 
+    // Target: Centaur
 
-/**
- * @brief  To be called at the end of mss_thermal_init.C.
- *         Sets action regs and unmasks fetch errors prior to the start of
- *         mainline traffic.
- *
- * @param  i_target         Centaur target
- * @param  i_bad_rc         If mss_thermal_init already has a 
- *                          bad rc before it calls this function, we pass it in 
- *                          as i_bad_rc. If this function gets it's own bad  
- *                          local l_rc, i_bad_rc will be commited, and l_rc will 
- *                          be passed back as return value. Else if no l_rc, 
- *                          i_bad_rc will be be passed back as return value.
- * @return Non-SUCCESS if i_bad_rc Non_SUCCESS, or if internal function fails, 
- *         SUCCESS otherwise.
- */
-fapi::ReturnCode mss_unmask_fetch_errors(const fapi::Target & i_target,
-                                         fapi::ReturnCode i_bad_rc );
+    FAPI_INF("ENTER mss_unmask_fetch_errors()"); 
+    
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmd_rc = 0;            
+
+
+    //*************************
+    //*************************
+    // SCAC_LFIR
+    //*************************
+    //*************************    
+    
+    ecmdDataBufferBase l_scac_lfir_mask(64);
+    ecmdDataBufferBase l_scac_lfir_mask_or(64);
+    ecmdDataBufferBase l_scac_lfir_mask_and(64);
+    ecmdDataBufferBase l_scac_lfir_action0(64);
+    ecmdDataBufferBase l_scac_lfir_action1(64);
+    
+    // Read mask
+    l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRMASK_0x020115C3, l_scac_lfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
+
+    l_ecmd_rc |= l_scac_lfir_action0.flushTo0();
+    l_ecmd_rc |= l_scac_lfir_action1.flushTo0();
+    l_ecmd_rc |= l_scac_lfir_mask_or.flushTo0();
+    l_ecmd_rc |= l_scac_lfir_mask_and.flushTo1();
+                
+    // 0	I2CMInvAddr                 recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(0);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(0);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(0);
+    
+    // 1	I2CMInvWrite                recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(1);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(1);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(1);
+
+    // 2	I2CMInvRead                 recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(2);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(2);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(2);
+
+    // 3	I2CMApar                    recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(3);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(3);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(3);
+
+    // 4	I2CMPar                     recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(4);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(4);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(4);
+
+    // 5	I2CMLBPar                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(5);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(5);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(5);
+
+    // 6:9	Expansion                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(6,4);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(6,4);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(6,4);    
+    
+    // 10	I2CMInvCmd                  recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(10);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(10);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(10);
+
+    // 11	I2CMPErr                    recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(11);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(11);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(11);
 
+    // 12	I2CMOverrun                 recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(12);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(12);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(12);
 
+    // 13	I2CMAccess                  recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(13);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(13);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(13);
+
+    // 14	I2CMArb                     recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(14);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(14);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(14);
+
+    // 15	I2CMNack                    recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(15);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(15);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(15);
+
+    // 16	I2CMStop                    recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(16);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(16);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(16);
+
+    // 17	LocalPib1                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(17);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(17);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(17);
+
+    // 18	LocalPib2                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(18);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(18);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(18);
+
+    // 19	LocalPib3                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(19);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(19);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(19);
+
+    // 20	LocalPib4                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(20);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(20);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(20);
+
+    // 21	LocalPib5                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(21);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(21);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(21);
+
+    // 22	LocalPib6                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(22);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(22);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(22);
+
+    // 23	LocalPib7                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(23);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(23);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(23);
+
+    // 24	StallError                  recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(24);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(24);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(24);
+
+    // 25	RegParErr                   channel checkstop   unmask
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(25);            
+    l_ecmd_rc |= l_scac_lfir_action1.clearBit(25);
+    l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(25);
+
+    // 26	RegParErrX                  channel checkstop   unmask
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(26);            
+    l_ecmd_rc |= l_scac_lfir_action1.clearBit(26);
+    l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(26);
+
+    // 27:31	Reserved                recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(27,5);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(27,5);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(27,5);
+    
+    // 32	SMErr                       recoverable         unmask
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(32);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(32);
+    l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(32);
+    
+    // 33	RegAccErr                   recoverable         unmask
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(33);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(33);
+    l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(33);
+
+    // 34	ResetErr                    recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(34);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(34);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(34);
+
+    // 35	internal_scom_error         recoverable         masked (tbd)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(35);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(35);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(35);
+
+    // 36	internal_scom_error_clone   recoverable         masked (tbd)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(36);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(36);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(36);
+
+    // 37:63	Reserved
+    // Can we write to these bits?
+
+
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    // Write action0
+    l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRACTION0_0x020115C6, l_scac_lfir_action0);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write action1
+    l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRACTION1_0x020115C7, l_scac_lfir_action1);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    
+    // Write mask OR
+    l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRMASK_OR_0x020115C5, l_scac_lfir_mask_or); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRMASK_AND_0x020115C4, l_scac_lfir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRACTION0_0x020115C6, l_scac_lfir_action0); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRACTION1_0x020115C7, l_scac_lfir_action1); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRMASK_0x020115C3, l_scac_lfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+
+
+    //*************************
+    //*************************
+    // MBS_FIR_REG
+    //*************************
+    //*************************
+    
+    
+    // NOTE: In the IPL sequence, mss_unmask_inband_errors has already been
+    // called, which has already set the MBS_FIR_REG action regs to their 
+    // runtime values, so no need to touch the action regs here.
+
+    // NOTE: In the IPL sequence, mss_unmask_inband_errors,
+    // has already been called, which has already unmasked the approproiate
+    // MBS_FIR_REG errors following mss_unmask_inband_errors. So all we will do 
+    // here is unmask errors requiring mainline traffic which would be 
+    // considered valid after the mss_thermal_init procedure. 
+    
+
+    ecmdDataBufferBase l_mbs_fir_mask(64);
+    ecmdDataBufferBase l_mbs_fir_mask_and(64);
+    
+    // Read mask 
+    l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }    
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+    l_ecmd_rc |= l_mbs_fir_mask_and.flushTo1();
+    
+    // 2    invalid_address_error   channel checkstop   unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(2);
+
+    // 3    external_timeout        channel checkstop   unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(3);
+    
+    // 4    internal_timeout        channel checkstop   unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(4);
+
+    // 9    cache_srw_ce            recoverable         unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(9);
+
+    // 10    cache_srw_ue           recoverable         unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(10);
+
+    // 12    cache_co_ce            recoverable         unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(12);
+
+    // 13    cache_co_ue            recoverable         unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(13);
+
+    // 15    dir_ce                 recoverable         unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(15);
+
+    // 16    dir_ue                 channel checkstop   unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(16);
+
+    // 18    dir_all_members_deleted channel checkstop  unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(18);
+
+    // 19    lru_error               recoverable        unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(19);
+
+    // 20    eDRAM error             channel checkstop  unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(20);
+
+    // 26    srb_buffer_ce           recoverable        unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(26);
+
+    // 27    srb_buffer_ue           recoverable        unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(27);
+    
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_MASK_REG_AND_0x02011404, l_mbs_fir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+
+
+    
+    std::vector<fapi::Target> l_mbaChiplets;
+    uint8_t l_mbaPosition;             // 0 = mba01, 1 = mba23
+
+
+    uint32_t l_mbeccfir_mask_address[2]={
+    // port0/1                            port2/3
+    MBS_ECC0_MBECCFIR_MASK_0x02011443,MBS_ECC1_MBECCFIR_MASK_0x02011483};
+
+    uint32_t l_mbeccfir_mask_and_address[2]={
+    // port0/1                            port2/3
+    MBS_ECC0_MBECCFIR_MASK_AND_0x02011444,MBS_ECC1_MBECCFIR_MASK_AND_0x02011484};
+
+    ecmdDataBufferBase l_mbeccfir_mask(64);
+    ecmdDataBufferBase l_mbeccfir_mask_and(64);
+
+    ecmdDataBufferBase l_mbaspa_mask(64);
+
+    // Get associated functional MBAs on this centaur
+    l_rc = fapiGetChildChiplets(i_target,
+                                fapi::TARGET_TYPE_MBA_CHIPLET,
+                                l_mbaChiplets);
+    if(l_rc)
+    {
+        FAPI_ERR("Error getting functional MBAs on this Centaur");
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);                
+        return l_rc;
+    }    
+
+    // Loop through functional MBAs on this Centaur
+    for (uint32_t i=0; i < l_mbaChiplets.size(); i++)
+    {
+
+        // Get MBA position: 0 = mba01, 1 = mba23
+        l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mbaChiplets[i], l_mbaPosition);
+        if(l_rc)
+        {
+            FAPI_ERR("Error getting MBA position");
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);                
+            return l_rc;
+        }    
+    
+
+        //*************************
+        //*************************
+        // MBASPA
+        //*************************
+        //*************************        
+                
+        // Read mask
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBSPAMSKQ_0x03010614,
+                                   l_mbaspa_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+        
+        // TODO: Here is where I could clear bits that were bogus, before I unmask 
+        //       them. But typically we are expecting the bit set at this point
+        //       to be valid errors for PRD to log.
+
+
+        // 1	Hard_CE_ETE_Attn                             unmask
+        // NOTE: Unmasking, but PRD responsible for setting and enabling the threshold.
+        l_ecmd_rc |= l_mbaspa_mask.clearBit(1);            
+
+        // 2	Soft_CE_ETE_Attn                             unmask
+        // NOTE: Unmasking, but PRD responsible for setting and enabling the threshold.
+        l_ecmd_rc |= l_mbaspa_mask.clearBit(2);            
+
+        // 3	Intermittent_ETE_Attn                        unmask
+        // NOTE: Unmasking, but PRD responsible for setting and enabling the threshold.
+        l_ecmd_rc |= l_mbaspa_mask.clearBit(3);            
+
+        // 4	RCE_ETE_Attn                                 unmask
+        // NOTE: Unmasking, but PRD responsible for setting and enabling the threshold.
+        l_ecmd_rc |= l_mbaspa_mask.clearBit(4);            
+                    
+
+        if(l_ecmd_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }                                                                              
+        
+        // Write mask
+        l_rc = fapiPutScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBSPAMSKQ_0x03010614,
+                                   l_mbaspa_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************    
+        // DEBUG: read them all back to verify
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBSPAMSKQ_0x03010614,
+                                   l_mbaspa_mask);
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+        //************************************************    
+
+
+
+        //*************************
+        //*************************
+        // MBECCFIR
+        //*************************
+        //*************************    
+
+        // Read mask
+        l_rc = fapiGetScom_w_retry(i_target, 
+                                   l_mbeccfir_mask_address[l_mbaPosition], 
+                                   l_mbeccfir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+    
+        // TODO: Here is where I could clear bits that were bogus, before I unmask 
+        //       them. But typically we are expecting the bit set at this point
+        //       to be valid errors for PRD to log.
+                    
+        // NOTE: In the IPL sequence, mss_unmask_maint_errors has already been
+        // called, which has already set the MBECCFIR action regs to their runtime
+        // values, so no need to touch the action regs here.
+
+        // NOTE: In the IPL sequence, mss_unmask_maint_errors,
+        // has already been called, which has already unmasked the approproiate
+        // MBECCFIR errors following mss_unmask_maint_errors. So all we will do 
+        // here is unmask errors requiring mainline traffic which would be 
+        // considered valid after the mss_thermal_init procedure. 
+
+        l_ecmd_rc |= l_mbeccfir_mask_and.flushTo1();
+
+        // 0:7	Memory MPE Rank 0:7         recoverable         unmask
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(0,8);
+
+        // 16	Memory NCE                  recoverable         unmask
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(16);
+
+        // 17	Memory RCE                  recoverable         unmask
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(17);
+
+        // 19	Memory UE                   recoverable         unmask
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(19);
+        
+        // 20:27	Maint MPE Rank 0:7      recoverable         unmask
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(20,8);
+        
+        // 41	Maintenance UE              recoverable         unmask
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(41);
+        
+        // 43	Prefetch Memory UE          recoverable         unmask
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(43);
+
+            
+        if(l_ecmd_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }                                                                              
+        
+        // Write mask AND
+        l_rc = fapiPutScom_w_retry(i_target,
+                                   l_mbeccfir_mask_and_address[l_mbaPosition], 
+                                   l_mbeccfir_mask_and); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************    
+        // DEBUG: read them all back to verify
+        l_rc = fapiGetScom_w_retry(i_target,
+                                   l_mbeccfir_mask_address[l_mbaPosition], 
+                                   l_mbeccfir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************    
+    }
+    
+    
+    //*************************
+    //*************************
+    // MBACALFIR
+    //*************************
+    //*************************
+
+    ecmdDataBufferBase l_mbacalfir_mask(64);
+    ecmdDataBufferBase l_mbacalfir_mask_and(64);        
+    
+    // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been
+    // called, which has already set the MBACALFIR action regs to their runtime
+    // values, so no need to touch the action regs here.
+
+    // NOTE: In the IPL sequence, various bits have already been unmasked
+    // after the approproiate procedures. So all we will do here is unmask
+    // errors requiring mainline traffic which would be considered valid after
+    // the mss_thermal_init procedure. 
+
+    // Loop through functional MBAs on this Centaur
+    for (uint32_t i=0; i < l_mbaChiplets.size(); i++)
+    {
+
+        // Read mask
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBACALFIR_MASK_0x03010403,
+                                   l_mbacalfir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+        
+        // TODO: Here is where I could clear bits that were bogus, before I unmask 
+        //       them. But typically we are expecting the bit set at this point
+        //       to be valid errors for PRD to log.
+            
+        l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1();        
+        
+        // 9	mba_wrd ue                  recoverable         unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(9);
+
+        // 10	mba_wrd ce                  recoverable         unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(10);
+
+        // 14	wrq_data_ce                 recoverable         unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(14);
+
+        // 15	wrq_data_ue                 recoverable         unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(15);
+
+        if(l_ecmd_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }                                                                              
+
+        // Write mask AND
+        l_rc = fapiPutScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBACALFIR_MASK_AND_0x03010404,
+                                   l_mbacalfir_mask_and); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+
+        //************************************************    
+        // DEBUG: read them all back to verify
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBACALFIR_MASK_0x03010403,
+                                   l_mbacalfir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************    
+    }
+
+
+   
+    
+    FAPI_INF("EXIT mss_unmask_fetch_errors()"); 
+
+    return i_bad_rc;
+}
 
 //------------------------------------------------------------------------------
 // fapiGetScom_w_retry
 //------------------------------------------------------------------------------
-
-/**
- * @brief     Reads a SCOM register from a Chip and retries once if SCOM fails.
- *            Retry is done with assumption that hostboot will switch from
- *            inband SCOM to FSI, so if inband failed due to channel fail,
- *            FSI may still work.
- * @param[in] i_target      Target to operate on
- * @param[in] i_address     Scom address to read from
- * @param[out] o_data       ecmdDataBufferBase object that holds data read from
- *                             address
- * @return ReturnCode. Zero on success, else platform specified error
- */
 fapi::ReturnCode fapiGetScom_w_retry(const fapi::Target& i_target,
                                      const uint64_t i_address,
-                                     ecmdDataBufferBase & o_data);
+                                     ecmdDataBufferBase & o_data)
+{
+    fapi::ReturnCode l_rc;
+    
+    l_rc = fapiGetScom(i_target, i_address, o_data);
+    if(l_rc)
+    {
+        FAPI_ERR("1st Centaur fapiGetScom failed, so attempting retry.");
+
+        // Log centaur scom error
+        fapiLogError(l_rc);        
+
+        // Retry centaur scom with assumption that retry is done via FSI,
+        // which may still work.
+        // NOTE: If scom fail was due to channel fail a retry via FSI may
+        // work. But if scom fail was due to PIB error, retry via FSI may
+        // also fail.
+        l_rc = fapiGetScom(i_target, i_address, o_data); 
+        if(l_rc)
+        {
+            FAPI_ERR("fapiGetScom retry via FSI failed.");       
+            // Retry didn't work either so give up and pass 
+            // back centaur scom error
+        }
+    }    
+    
+    return l_rc;
+}
+
 
 //------------------------------------------------------------------------------
 // fapiPutScom_w_retry
 //------------------------------------------------------------------------------
-
-/**
- * @brief     Writes a SCOM register on a Chip and retries once if SCOM fails.
- *            Retry is done with assumption that hostboot will switch from
- *            inband SCOM to FSI, so if inband failed due to channel fail,
- *            FSI may still work.
- * @param[in] i_target Target to operate on
- * @param[in] i_address Scom address to write to
- * @param[in] i_data ecmdDataBufferBase object that holds data to write into
- *                   address
- * @return ReturnCode. Zero on success, else platform specified error
- */
 fapi::ReturnCode fapiPutScom_w_retry(const fapi::Target& i_target,
                                      const uint64_t i_address,
-                                     ecmdDataBufferBase & i_data);
-
-
-
-
+                                     ecmdDataBufferBase & i_data)
+{
+    fapi::ReturnCode l_rc;
+    
+    // NOTE: Inband scom device driver takes care of read to special reg after
+    // an inband scom write in order to detect SUE
+    l_rc = fapiPutScom(i_target, i_address, i_data);
+    if(l_rc)
+    {
+        FAPI_ERR("1st Centaur fapiPutScom failed, so attempting retry.");
 
+        // Log centaur scom error
+        fapiLogError(l_rc);        
 
-#endif /* _MSS_UNMASK_ERRORS_H */
+        // Retry centaur scom with assumption that retry is done via FSI,
+        // which may still work.
+        // NOTE: If scom fail was due to channel fail a retry via FSI may
+        // work. But if scom fail was due to PIB error, retry via FSI may
+        // also fail.
+        l_rc = fapiPutScom(i_target, i_address, i_data); 
+        if(l_rc)
+        {
+            FAPI_ERR("fapiPutScom retry via FSI failed.");       
+            // Retry didn't work either so give up and pass 
+            // back centaur scom error
+        }
+    }    
+    
+    return l_rc;
+}
diff --git a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile
index 9ed7c6d6d..1ed84a791 100755
--- a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile
+++ b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile
@@ -1,4 +1,4 @@
-#-- $Id: cen_ddrphy.initfile,v 1.25 2013/05/09 00:33:41 mwuu Exp $
+#-- $Id: cen_ddrphy.initfile,v 1.26 2013/07/17 15:45:02 mwuu Exp $
 #-- $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
 #--          centaur/working/procedures/ec_ind/scoms/cen_ddrphy.initfile,v $
 #
@@ -6,6 +6,9 @@
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.26|mwuu    |07/17/13|Changed FAST_SIM_PC to use SIM attribute, changed
+#           |        |        |type1 define to use CUSTOM attribute as well.
+#           |        |        |Changed READ_CLOCK section to enable clocks for x4.
 #--     1.25|mwuu    |05/08/13|Fixed change in DDR4/DDR3 DIMM type
 #--     1.24|mwuu    |04/19/13|Changed to use ATTR_EFF_DIMM_SPARE instead of CDIMM
 #--     1.23|mwuu    |04/09/13|Fixed typo ENUM for 2N mode.
@@ -22,7 +25,7 @@
 #--     1.19|mwuu    |12/12/12|Commented out settings for SIM, changed attribute
 #           |        |        |to CEN.ATTR_CENTAUR_EC_WRITE_FIR_MASK_FEATURE
 #--		1.18|mwuu	 |12/03/12|Changed DP18_PLL_CONFIG1 VCO setting
-#--		1.17|mwuu	 |11/30/12|Changed DP18_PLL_CONFIG0/1 registers & 
+#--		1.17|mwuu	 |11/30/12|Changed DP18_PLL_CONFIG0/1 registers &
 #           |        |        |DP18_IO_TX_CONFIG0 INTERP_SIG_SLEW field
 #--		1.16|mwuu	 |11/28/12|Changed ADR TSYS to 0x70 and DP18 TSYS to 0x6B.
 #           |        |        |Changed ADR_PLL_VREG_CONFIG0/1 registers.
@@ -91,7 +94,7 @@ define CEN = TGT1;	# parent Centaur
 define def_is_sim		=	(SYS.ATTR_IS_SIMULATION == 1)	;
 
 # FAST_SIM_PER_CNTR for periodic calibrations
-define def_FAST_SIM_PC	=	1	;
+define def_FAST_SIM_PC	=	(SYS.ATTR_IS_SIMULATION == 1)	;
 
 # for real HW uncomment,  !!FIX once ATTR_EFF_DIMM_SPARE available [2][4][4] port, dimm, rank
 define def_p0_has_spare_full	=	(ATTR_EFF_DIMM_SPARE[0][0][0] == ENUM_ATTR_EFF_DIMM_SPARE_FULL_BYTE)	;	# spare byte
@@ -106,7 +109,7 @@ define def_p1_no_spare			=	(ATTR_EFF_DIMM_SPARE[1][0][0] == ENUM_ATTR_EFF_DIMM_S
 
 # ports 0,1 must have functional dimms to be valid
 define def_valid_p0		=	(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR >> 4);		# ((def_is_mba01) || (def_is_mba23)) &&
-define def_valid_p1		=	(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR & 0x0F);	
+define def_valid_p1		=	(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR & 0x0F);
 
 # short test for MBA01 or MBA23
 define def_is_mba01		=	(ATTR_CHIP_UNIT_POS == 0)	;	# MBA01
@@ -279,17 +282,19 @@ define def_cdi_spcke_ohm20_p1	=	(ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_
 define def_cdi_spcke_ohm30_p1	=	(ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM30)	;	# OHM30 = 0x1E (30)
 define def_cdi_spcke_ohm40_p1	=	(ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40)	;	# OHM40 = 0x28 (40)
 
-# define for glacier1(1), glacier2=normal(0)
-define def_is_type1	=	((ATTR_MSS_DQS_SWIZZLE_TYPE == 1) && (ATTR_EFF_DIMM_TYPE != ENUM_ATTR_EFF_DIMM_TYPE_CDIMM))	;
+# define for glacier1(1), glacier2=normal(0)   remove dimm_type != cdimm later
+define def_is_type1	=	((ATTR_MSS_DQS_SWIZZLE_TYPE == 1) && ((ATTR_EFF_CUSTOM_DIMM != ENUM_ATTR_EFF_CUSTOM_DIMM_YES) || (ATTR_EFF_DIMM_TYPE != ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)));
 
-define def_is_custom = (ATTR_EFF_CUSTOM_DIMM == ENUM_ATTR_EFF_CUSTOM_DIMM_YES);
+# remove dimm_type == cdimm later
+define def_is_custom = ((ATTR_EFF_CUSTOM_DIMM == ENUM_ATTR_EFF_CUSTOM_DIMM_YES) || (ATTR_EFF_DIMM_TYPE == ENUM_ATTR_EFF_DIMM_TYPE_CDIMM));
 
 # define for 2 cycle addressing mode (2N)
 define def_2N_mode	= (ATTR_EFF_DRAM_2N_MODE_ENABLED == ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_TRUE) ;
 
 # fix phase rotators due to NWELL issue
-define def_CL_adj = (CEN.ATTR_MSS_NWELL_MISPLACEMENT * 0x7F);
-define def_PR_adj = (CEN.ATTR_MSS_NWELL_MISPLACEMENT * 32);
+#define def_CL_adj = (CEN.ATTR_MSS_NWELL_MISPLACEMENT * 0x7F);
+#	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[0] | (def_CL_adj))		,	(def_is_mba01)	;	# P0 L1	, A_A0	centerlane
+#define def_PR_adj = (CEN.ATTR_MSS_NWELL_MISPLACEMENT * 32);
 
 # SIMPLIFY
 # ================================================================================
@@ -298,7 +303,7 @@ define def_AL_ena	= (ATTR_EFF_DRAM_AL != 0);
 define def_AL_dis	= (ATTR_EFF_DRAM_AL == 0);
 
 # for calculating FW_RD_WR delay...  NOTE: AL could be disabled(=0)
-define def_TWTR_PLUS_OFF = (ATTR_EFF_DRAM_TWTR + 11)	;	# change from +8 on reg spec 
+define def_TWTR_PLUS_OFF = (ATTR_EFF_DRAM_TWTR + 11)	;	# change from +8 on reg spec
 define def_TRTP_PLUS_AL	= (ATTR_EFF_DRAM_TRTP + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_AL + 3)	;
 define def_TRTP_PLUS_NOAL = (ATTR_EFF_DRAM_TRTP + 3)	;
 
@@ -316,8 +321,8 @@ define def_tODTL_DDR4_NOAL	= (ATTR_EFF_DRAM_CWL - 3)	;	# DDR4 & 2tCK, no AL
 # def_1PR 			= 1000*1000 / (FREQ / 2)
 # def_dqs_offset 	= (10 + ((def_p2p_jitter / 2) / def_1PR) + 1)	# +1 for ceiling FN
 #define def_p2p_jitter		=	240										;	# DQS peak to peak jitter in ps
-define def_p2p_jitter		=	2600										;	# DQS peak to peak jitter in ps
-define def_dqs_offset		=	(11 + ((def_p2p_jitter * CEN.ATTR_MSS_FREQ) / 4000000))	;
+define def_p2p_jitter		=	2600									;	# DQS peak to peak jitter in ps
+define def_dqs_offset		=	(11 + (((def_p2p_jitter) * CEN.ATTR_MSS_FREQ) / 4000000))	;
 
 #---------------------------------------------------------------------------------
 
@@ -413,18 +418,20 @@ scom 0x800(0,1)C00C0301143F {	# _P[0:1]
 # PC_CONFIG1
 #
 # DPHY01.DDRPHY_PC_CONFIG1_P0
-scom 0x800(0,1)C00D0301143F {
+scom 0x8000C00D0301143F {
 	bits	,	scom_data	,	expr								;
 #	0:47	,	0x000000000000,	any		;	# reserved
 # 	# WLO is normally 0 except for RDIMM (RCD) configurations in which case it's set to 1
 # DD0 = PORT_BUFFER_LATENCY
- 	48:51	,	0x1			,	(def_is_rdimm)						;	# RDIMM
  	48:51	,	0xF			,	(def_is_lrdimm)						;	# LRDIMM  set WLO=-1
- 	48:51	,	0x0			,	any									;	# WLO=WRITE_LATENCY_OFFSET (2's complement -8 to 7)
+ 	48:51	,	(ATTR_EFF_WLO[0]),	any								;	# based on attribute now..
+# 	48:51	,	0x1			,	(def_is_rdimm)						;	# RDIMM
+# 	48:51	,	0x0			,	any									;	# WLO=WRITE_LATENCY_OFFSET (2's complement -8 to 7)
 # 	# 9.4.12.2	RLO = READ_LATENCY_OFFSET (2's complement -8 to 7) {0=CDIMM, 1=RDIMM, 2=LRDIMM}
- 	52:55	,	0x1			,	(def_is_rdimm)						;	# RDIMM
+# 	52:55	,	0x1			,	(def_is_rdimm)						;	# RDIMM
+# 	52:55	,	0x0			,	any									;	# CDIMM/UDIMM
  	52:55	,	0x6			,	(def_is_lrdimm)						;	# LRDIMM
- 	52:55	,	0x0			,	any									;	# CDIMM/UDIMM
+ 	52:55	,	(ATTR_EFF_RLO[0]),	any								;	# based on attribute now..
  	56		,	0b0			,	any									;	# MEMCTL_CIC_FAST
  	57		,	0b0			,	any									;	# MEMCTL_CTRN_IGNORE
  	58		,	0b0			,	any									;	# DISABLE_MEMCTL_CAL
@@ -448,6 +455,39 @@ scom 0x800(0,1)C00D0301143F {
 #	63		,	0b0			,	any									;	# Retain_Percal_SW
 }
 
+# DPHY01.DDRPHY_PC_CONFIG1_P1
+scom 0x8001C00D0301143F {
+	bits	,	scom_data	,	expr								;
+#	0:47	,	0x000000000000,	any		;	# reserved
+# 	# WLO is normally 0 except for RDIMM (RCD) configurations in which case it's set to 1
+# DD0 = PORT_BUFFER_LATENCY
+ 	48:51	,	0xF			,	(def_is_lrdimm)						;	# LRDIMM  set WLO=-1
+ 	48:51	,	(ATTR_EFF_WLO[1]),	any								;	# based on attribute now..
+# 	48:51	,	0x1			,	(def_is_rdimm)						;	# RDIMM
+# 	48:51	,	0x0			,	any									;	# WLO=WRITE_LATENCY_OFFSET (2's complement -8 to 7)
+# 	# 9.4.12.2	RLO = READ_LATENCY_OFFSET (2's complement -8 to 7) {0=CDIMM, 1=RDIMM, 2=LRDIMM}
+ 	52:55	,	0x6			,	(def_is_lrdimm)						;	# LRDIMM
+ 	52:55	,	(ATTR_EFF_RLO[1]),	any								;	# based on attribute now..
+# 	52:55	,	0x1			,	(def_is_rdimm)						;	# RDIMM
+# 	52:55	,	0x0			,	any									;	# CDIMM/UDIMM
+ 	56		,	0b0			,	any									;	# MEMCTL_CIC_FAST
+ 	57		,	0b0			,	any									;	# MEMCTL_CTRN_IGNORE
+ 	58		,	0b0			,	any									;	# DISABLE_MEMCTL_CAL
+# 	Memory Type
+# 	# 59:61 , 000=DDR3/DDR4 CDIMM, DDR3 (001=RDIMM, 011=LRDIMM), DDR4 (101=RDIMM, 111=LRDIMM)
+	59		,	0b0			,	(def_is_custom)						;	# special for CDIMM
+	59		,	0b1			,	(def_is_ddr4)						;	# DDR4
+	59		,	0b0			,	any									;	# DDR3 or custom
+
+	60		,	0b1			,	(def_is_lrdimm)						;	# LRDIMM
+	60		,	0b0			,	any									;	# not LRDIMM
+
+	61		,	0b1			,	((def_is_lrdimm) || (def_is_rdimm))	;	# registered C/A
+	61		,	0b0			,	any									;	# unbuffered C/A
+#	62		,	0b1			,	any									;	# DDR4 Latency Chicken SW
+#	63		,	0b0			,	any									;	# Retain_Percal_SW
+}
+
 # ---------------------------------------------------------------------------------------
 # PC Resets register			default=0xC000
 #
@@ -500,7 +540,7 @@ scom 0x800(0,1)BC300301143F {		# PHY01 Port[0:1] broadcast ADR32S[0:1]
  	48:59	,	0x6A9		,	(CEN.ATTR_MSS_FREQ > 1459)		;	# >= 730 MHz, >=1460 MT/s
 
 	60:63	,	0x4			,	(def_is_ddr4)					;	# VCO = high for DDR4
-	60:63	,	0x0			,	any								;	# VCO = low for DDR3 
+	60:63	,	0x0			,	any								;	# VCO = low for DDR3
 
 }
 
@@ -571,11 +611,11 @@ scom 0x800(0,1)3C760301143F {			# CONFIG0_P[0:1] broadcast [0:4]
 #  	# 0b111 000 111011 00 00	20uA, gain 1, SE(200 ohms, 24pF, 3pF), VCO=low
 #	# 300-599.9 MHz, < 1200 MT/s
 #  	48:59	,	0xE3B		,	((def_is_sim) && (CEN.ATTR_MSS_FREQ < 1200))	;
-# 
+#
 #  	# 0b010 000 111000 00 00	40uA, gain 1, SE(200 ohms, 16pF, 2pF), VCO=low
 #	# 600-999.9 MHz, 1200-2000 MT/s
-#  	48:59	,	0x438		,	((def_is_sim) &&  (CEN.ATTR_MSS_FREQ < 2000))	;	
-# 
+#  	48:59	,	0x438		,	((def_is_sim) &&  (CEN.ATTR_MSS_FREQ < 2000))	;
+#
 # 	# 0b100 011 111011 01 00	28.57uA, gain 4, SE(200 ohms, 24pF, 3pF), VCO=high
 #	# 1000-1066 MHz, >=2000 MT/s
 #  	48:59	,	0x8FB		,	((def_is_sim) && (CEN.ATTR_MSS_FREQ >= 2000))	;
@@ -592,7 +632,7 @@ scom 0x800(0,1)3C760301143F {			# CONFIG0_P[0:1] broadcast [0:4]
 
 #	60:63	,	0x0			,	(def_is_sim)					;	# for SIM
 	60:63	,	0x4			,	(CEN.ATTR_MSS_FREQ > 1459)		;	# VCO = high for >= 730MHz or 1460 MT/s
-	60:63	,	0x0			,	any								;	# VCO = low for < 730MHz 
+	60:63	,	0x0			,	any								;	# VCO = low for < 730MHz
 }
 
 # ---------------------------------------------------------------------------------------
@@ -712,7 +752,7 @@ scom 0x80013C750301143F {				# CONFIG0_P1 broadcast [0:4]
  	48:51	,	0b0100		,	((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460))	;	# 1333
  	48:51	,	0b0010		,	((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732))	;	# 1600
  	48:51	,	0b1100		,	((CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993))	;	# 1866
-	
+
 	# Post Cursor, tap coefficient for FFE, 0=no equalization
 	52:55	,	0b0001		,	(def_ffe1_p1)	;	# enable 1 FFE slice
 	52:55	,	0b0011		,	(def_ffe2_p1)	;	# enable 2 FFE slices
@@ -905,7 +945,7 @@ scom 0x80013C7(8,9)0301143F {	# [N:P]FET_SLICE_P1_[0:4]	broadcast
 #!scom 0x800(0,1)(40,44,48,4C)(10,11,12,13)0301143F {	# EN[0:3]_P[0:1]_ADR[0:3]
 #!scom 0x800(0,1)7C(10,11,12,13)0301143F {	# EN[0:3]_P[0:1]_ADR[0:3] via broadcast
 #!	bits	,	scom_data	;
-#	0:47	,	0x000000000000			;	# reserved
+##	0:47	,	0x000000000000			;	# reserved
 #!	48:63	,	0b1111111111110000		;
 #!}
 #!
@@ -917,7 +957,7 @@ scom 0x80013C7(8,9)0301143F {	# [N:P]FET_SLICE_P1_[0:4]	broadcast
 #!scom 0x800(0,1)(40,44,48,4C)(14,15,16,17)0301143F {	# EN[0:3]_P[0:1]_ADR[0:3]
 #!scom 0x800(0,1)7C(14,15,16,17)0301143F {	# EN[0:3]_P[0:1]_ADR[0:3] via broadcast
 #!	bits	,	scom_data	;
-#	0:47	,	0x000000000000			;	# reserved
+##	0:47	,	0x000000000000			;	# reserved
 #!	48:63	,	0b1111111111110000		;
 #!}
 #**********************************************************************************
@@ -1923,7 +1963,7 @@ scom 0x80014c210301143f {
 #scom 0x8000(40,44,48,4c)1A0301143f {	# VALUE_P0_ADR[0:3]
 #scom 0x800(0,1)7C1A0301143f {			# VALUE_P[0:1]_ADR[0:3] broadcast
 #	bits	,	scom_data	,	expr								;
-#	0:47	,	0x000000000000,	any									;	# reserved
+##	0:47	,	0x000000000000,	any									;	# reserved
 	# SLEW_CTL0, used for command (A0:15, BA0:3, ACT, PAR, CAS, RAS, WE)
 #	48:51	,	0b0000		,	(ATTR_EFF_CEN_SLEW_RATE_ADDR[0])	;
 	# SLEW_CTL1, used for control (CKE0:1, CKE4:5, ODT, CSN0:7)
@@ -2403,7 +2443,7 @@ scom 0x80014c2b0301143f {
 # DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0		0x006	0x800000060301143f
 # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.RDDP18CNTL_MAC.RCVRPEAK_L2
 #scom 0x800(0,1)(00,04,08,0C,10)060301143f {	# _P[0:1]_[0:4]
-scom 0x80003C060301143f {	# _P[0:1]_[0:4] via broadcast
+scom 0x80003C060301143f {	# _P0_[0:4] via broadcast
 	bits	,	scom_data	,	expr			;
 #	0:47	,	0x000000000000,	any				;	# reserved
 	48:50	,	0b000		,	any				;	# PEAK_AMP_CTL_SIDE0, amp ctl bits
@@ -2900,6 +2940,7 @@ scom 0x800(0,1)c0330301143f {
 #
 # DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_0		0x037	0x800000370301143f
 # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.RDDP18CNTL_MAC.DQSOFFSET_L2(0:6)
+#scom 0x8000(00,04,08,0C,10)370301143f {	# _P0_[0:4], all instances
 scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 	bits	,	scom_data		,	expr			;
 #	0:47	,	0x000000000000	,	any				;	# reserved
@@ -2910,11 +2951,11 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 }
 
 # ---------------------------------------------------------------------------------------
-# DP18 Write DQ offset value register	default=0		aka=windage
+# DP18 Write DQ offset value register	default=0
 #
-# Used to perform a pre-offset before write leveling starts.  Value will be used by the
-# Write centering calibration state machine.
-# NOTE:  Does NOT affect the data bit delay values if calibration is not run!
+# Used to shift(left/right) the Write Eye after Write centering calibration.
+# The value is 2's complement and can only move it in 2 tick increments.
+# NOTE:  Does NOT affect the data bit delay values if Write centering calibration is not run!
 #
 # 200 ps offset / # steps based on freq?
 #
@@ -2931,7 +2972,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # _RP[0:3]_P[0:1]_[0:4], all instances and rank pairs via broadcast, both ports
 # scom 0x800(0,1)3CFE0301143f {	# _RP[0:3]_P[0:1]_[0:4]
 # 	bits	,	scom_data	,	expr			;
-#	0:47	,	0x000000000000,	any				;	# reserved
+##	0:47	,	0x000000000000,	any				;	# reserved
 # 	48:51	,	0x0			,	any				;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	any				;	# DQ_WR_OFFSET_N1
 # 	56:59	,	0x0			,	any				;	# DQ_WR_OFFSET_N2
@@ -2940,7 +2981,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 #
 # scom 0x80003C7E0301143f {	# _RP0_P0_[0:4], rank pair 0, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
-#	0:47	,	0x000000000000,	any				;	# reserved
+##	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 0  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -2954,7 +2995,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # }
 # scom 0x80003D7E0301143f {	# _RP1_P0_[0:4], rank pair 1, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
-#	0:47	,	0x000000000000,	any				;	# reserved
+##	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 0  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -2968,7 +3009,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # }
 # scom 0x80003E7E0301143f {	# _RP2_P0_[0:4], rank pair 2, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
-#	0:47	,	0x000000000000,	any				;	# reserved
+##	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 0  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -2982,7 +3023,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # }
 # scom 0x80003F7E0301143f {	# _RP3_P0_[0:4], rank pair 3, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
-#	0:47	,	0x000000000000,	any				;	# reserved
+##	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 0  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -2997,7 +3038,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # ===============================================================================
 # scom 0x80013C7E0301143f {	# _RP0_P1_[0:4], rank pair 0, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
-#	0:47	,	0x000000000000,	any				;	# reserved
+##	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 1  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -3011,7 +3052,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # }
 # scom 0x80013D7E0301143f {	# _RP1_P1_[0:4], rank pair 1, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
-#	0:47	,	0x000000000000,	any				;	# reserved
+##	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 1  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -3025,7 +3066,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # }
 # scom 0x80013E7E0301143f {	# _RP2_P1_[0:4], rank pair 2, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
-#	0:47	,	0x000000000000,	any				;	# reserved
+##	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 1  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -3039,7 +3080,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # }
 # scom 0x80013F7E0301143f {	# _RP3_P1_[0:4], rank pair 3, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
-#	0:47	,	0x000000000000,	any				;	# reserved
+##	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 1  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -3141,19 +3182,17 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 scom 0x8000C0160301143F {	# Port 0
 	bits	,	scom_data	,	expr				;
 #	0:47	,	0x000000000000,	any					;	# reserved
-	48		,	0b1			,	any					;	# ENA_WR_LEVEL
-	49		,	0b0			,	any					;	# ENA_INITIAL_PAT_WR, for custom pattern
-	50		,	0b1			,	any					;	# ENA_DQS_ALIGN
-	51		,	0b1			,	any					;	# ENA_RDCLK_ALIGN
-
-	52		,	0b1			,	any					;	# ENA_READ_CTR
-	53		,	0b1			,	any					;	# ENA_WRITE_CTR
-	54		,	0b1			,	any					;	# ENA_INITIAL_COARSE_WR
-	55		,	0b1			,	any					;	# ENA_COARSE_RD
-
+#	48		,	0b1			,	(def_is_sim)		;	# ENA_WR_LEVEL
+#	49		,	0b0			,	(def_is_sim)		;	# ENA_INITIAL_PAT_WR, for custom pattern
+#	50		,	0b1			,	(def_is_sim)		;	# ENA_DQS_ALIGN
+#	51		,	0b1			,	(def_is_sim)		;	# ENA_RDCLK_ALIGN
+#	52		,	0b1			,	(def_is_sim)		;	# ENA_READ_CTR
+#	53		,	0b1			,	(def_is_sim)		;	# ENA_WRITE_CTR
+#	54		,	0b1			,	(def_is_sim)		;	# ENA_INITIAL_COARSE_WR
+#	55		,	0b1			,	(def_is_sim)		;	# ENA_COARSE_RD
 	56		,	0b0			,	any					;	# ENA_CUSTOM_RD
 	57		,	0b0			,	any					;	# ENA_CUSTOM_WR
-	58		,	0b1			,	any					;	# ABORT_ON_CAL_ERROR
+#	58		,	0b1			,	(def_is_sim)		;	# ABORT_ON_CAL_ERROR
 	59		,	0b0			,	any					;	# ENA_DIGITAL_EYE
 
 	# ENA_RANK_GROUP[0:3], 4 bits
@@ -3171,17 +3210,17 @@ scom 0x8000C0160301143F {	# Port 0
 scom 0x8001C0160301143F {	# Port 1
 	bits	,	scom_data	,	expr				;
 #	0:47	,	0x000000000000,	any					;	# reserved
-	48		,	0b1			,	(def_is_sim)		;	# ENA_WR_LEVEL
-	49		,	0b0			,	(def_is_sim)		;	# ENA_INITIAL_PAT_WR, for custom pattern
-	50		,	0b1			,	(def_is_sim)		;	# ENA_DQS_ALIGN
-	51		,	0b1			,	(def_is_sim)		;	# ENA_RDCLK_ALIGN
-	52		,	0b1			,	(def_is_sim)		;	# ENA_READ_CTR
-	53		,	0b1			,	(def_is_sim)		;	# ENA_WRITE_CTR
-	54		,	0b1			,	(def_is_sim)		;	# ENA_INITIAL_COARSE_WR
-	55		,	0b1			,	(def_is_sim)		;	# ENA_COARSE_RD
+#	48		,	0b1			,	(def_is_sim)		;	# ENA_WR_LEVEL
+#	49		,	0b0			,	(def_is_sim)		;	# ENA_INITIAL_PAT_WR, for custom pattern
+#	50		,	0b1			,	(def_is_sim)		;	# ENA_DQS_ALIGN
+#	51		,	0b1			,	(def_is_sim)		;	# ENA_RDCLK_ALIGN
+#	52		,	0b1			,	(def_is_sim)		;	# ENA_READ_CTR
+#	53		,	0b1			,	(def_is_sim)		;	# ENA_WRITE_CTR
+#	54		,	0b1			,	(def_is_sim)		;	# ENA_INITIAL_COARSE_WR
+#	55		,	0b1			,	(def_is_sim)		;	# ENA_COARSE_RD
 	56		,	0b0			,	any					;	# ENA_CUSTOM_RD
 	57		,	0b0			,	any					;	# ENA_CUSTOM_WR
-	58		,	0b1			,	(def_is_sim)		;	# ABORT_ON_CAL_ERROR
+#	58		,	0b1			,	(def_is_sim)		;	# ABORT_ON_CAL_ERROR
 	59		,	0b0			,	any					;	# ENA_DIGITAL_EYE
 	# ENA_RANK_GROUP[0:3], 4 bits
 	60		,	0b1			,	(def_val_prg0_p1)	;	# enable primary rank group 0
@@ -3434,7 +3473,7 @@ scom 0x8000c0090301143f {
 # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG17_L2
 #scom 0x8000c0110301143f {
 #	bits	,	scom_data	,	expr		;
-#	0:47	,	0x000000000000,	any			;	# reserved
+##	0:47	,	0x000000000000,	any			;	# reserved
 #	48		,	0b0			,	any			;	# ADDR_MIRROR_RP0_PRI
 #	49		,	0b0			,	any			;	# ADDR_MIRROR_RP0_SEC
 #	50		,	0b0			,	any			;	# ADDR_MIRROR_RP1_PRI
@@ -3458,7 +3497,7 @@ scom 0x8000c0090301143f {
 # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG53_L2
 #scom 0x8000c0350301143f {
 #	bits	,	scom_data	,	expr		;
-#	0:47	,	0x000000000000,	any			;	# reserved
+##	0:47	,	0x000000000000,	any			;	# reserved
 #	48		,	0b0			,	any			;	# ADDR_MIRROR_RP0_TER
 #	49		,	0b0			,	any			;	# ADDR_MIRROR_RP0_QUA
 #	50		,	0b0			,	any			;	# ADDR_MIRROR_RP1_TER
@@ -3704,7 +3743,36 @@ scom 0x8001c0310301143f {
 #
 # DPHY01_DDRPHY_RC_CONFIG0_P0		0x000	0x8000c8000301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.RCX.RC_CONFIG0_L2
-scom 0x800(0,1)C8000301143F {	# _P[0:1]
+scom 0x8000C8000301143F {	# _P0
+	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
+	#
+	# System_Delay = ( ( (ADR_DELAY - 64) +
+	# {wire delay from the PHY memory clock output to the DRAM module converted to units of 1/128th of a MEMINTCLKO clock cycle} +
+	# {delay of DQS at the memory module pin relative to memory clock at the memory module pin introduced by the memory module
+	# (that is, tDQSCK) converted to units of 1/128th of a MEMINTCLKO clock cycle} +
+	# {wire delay from the DRAM DQS output to the PHY converted to units of 1/128th of a MEMINTCLKO clock cycle}) / 128) +
+	# {number of pipeline stages in the addr/cmd path} +
+	# {number of pipeline stages in the read data path}
+	#
+	# min GPO = 5 + max(rndUp(System_delay)) - RLO + ADVANCE_RD_VALID + SPAM_EN
+	# max GPO = 11 if in 2:1, 13 if in 4:1
+	48:51	,	0b0111		,	(def_is_lrdimm)	;	# GLOBAL_PHY_OFFSET LRDIMM set to 7
+	48:51	,	(ATTR_EFF_GPO[0]),	any			;	# GLOBAL_PHY_OFFSET (GPO), based on attribute now
+#	48:51	,	0b0101		,	any				;	# GLOBAL_PHY_OFFSET (GPO), ideally 2:1 max=11, 4:1 max=13
+	52		,	0b0			,	any				;	# ADVANCE_RD_VALID	ask Yuen
+	53		,	0b0			,	any				;	# PER_DUTY_CYCLE_SW, 0=rd cmds 50% duty cycle during per.cal, 1=continuously
+	54:56	,	0b000		,	any				;	# NUM_PERIODIC_CAL, (value+1)=num bits per peridic cal
+	57		,	0b0			,	any				;	# SINGLE_BIT_MPR_RP0
+	58		,	0b0			,	any				;	# SINGLE_BIT_MPR_RP1
+	59		,	0b0			,	any				;	# SINGLE_BIT_MPR_RP2
+	60		,	0b0			,	any				;	# SINGLE_BIT_MPR_RP3
+	61		,	0b0			,	any				;	# ALIGN_ON_EVEN_CYCLES
+# !! switched to '1' to match SIM
+	62		,	0b1			,	any				;	# PERFORM_RDCLK_ALIGN
+	63		,	0b0			,	any				;	# STAGGERED_PATTERN		# for DDR4, 0=serial, 1=staggered
+}
+scom 0x8001C8000301143F {	# _P1
 	bits	,	scom_data	,	expr			;
 #	0:47	,	0x000000000000,	any				;	# reserved
 	#
@@ -3719,9 +3787,10 @@ scom 0x800(0,1)C8000301143F {	# _P[0:1]
 	# min GPO = 5 + max(rndUp(System_delay)) - RLO + ADVANCE_RD_VALID + SPAM_EN
 	# max GPO = 11 if in 2:1, 13 if in 4:1
 	48:51	,	0b0111		,	(def_is_lrdimm)	;	# GLOBAL_PHY_OFFSET LRDIMM set to 7
-	48:51	,	0b0101		,	any				;	# GLOBAL_PHY_OFFSET (GPO), ideally 2:1 max=11, 4:1 max=13
+	48:51	,	(ATTR_EFF_GPO[1]),	any			;	# GLOBAL_PHY_OFFSET (GPO), based on attribute now
+#	48:51	,	0b0101		,	any				;	# GLOBAL_PHY_OFFSET (GPO), ideally 2:1 max=11, 4:1 max=13
 	52		,	0b0			,	any				;	# ADVANCE_RD_VALID	ask Yuen
-	53		,	0b0			,	any				;	# PER_DUTY_CYCLE_SW, 0=rd cmds 50% duty cycle during per.cal, 1=continuously 
+	53		,	0b0			,	any				;	# PER_DUTY_CYCLE_SW, 0=rd cmds 50% duty cycle during per.cal, 1=continuously
 	54:56	,	0b000		,	any				;	# NUM_PERIODIC_CAL, (value+1)=num bits per peridic cal
 	57		,	0b0			,	any				;	# SINGLE_BIT_MPR_RP0
 	58		,	0b0			,	any				;	# SINGLE_BIT_MPR_RP1
@@ -4005,7 +4074,7 @@ scom 0x800(0,1)C4140301143F {	# _P[0:1]
 #DPHY01_DDRPHY_SEQ_LPT_ADDR2_P0		0x017	0x8000c4170301143f
 #scom 0x8000c4170301143f {
 #	bits	,	scom_data		;
-#	0:47	,	0x000000000000	;	# reserved
+##	0:47	,	0x000000000000	;	# reserved
 #	48:63	,	0xFFFF			;	# LPT_ADDR2
 #}
 
@@ -4034,7 +4103,7 @@ scom 0x800(0,1)CC000301143F {	# _P[0:1]
 	# FW_WR_RD [same formula as RD_WR? max(tWTR+11,AL+tRTP+3), ATTR_EFF_DRAM_AL(0,1,2)]
 	57:62	,	0b000000			,	(def_is_sim)							;   # is this max?
 	57:62	,	0b010001			,	any										;	# same as dd0, 17 clocks
-	
+
 	# AL={1,2};	max (TWTR + 11, TRTP + AL + 3)
 #	57:62	,	(def_TWTR_PLUS_OFF)	,	(def_AL_ena && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_AL) )	;	# TWTR + 11
 #	57:62	,	(def_TRTP_PLUS_AL)	,	(def_AL_ena && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_AL) )		;	# TRTP + AL + 3
@@ -4139,7 +4208,7 @@ scom 0x800(0,1)3C030301143f {	# DIR1_P[0:1]_[0:4] via broadcast
 
 # ---------------------------------------------------------------------------------------
 # ADR Output Driver Force and ATEST Control Register
-# 
+#
 # DPHY01_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0	0x035	0x800080350301143f
 #scom 0x800(0,1)(80,84)350301143f {	# P[0:1]_ADR32S[0:1]
 scom 0x800(0,1)BC350301143f {	# DIR1_P[0:1]_[0:4] via broadcast
@@ -4180,10 +4249,10 @@ scom 0x800(0,1)BC350301143f {	# DIR1_P[0:1]_[0:4] via broadcast
 # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0		0x800000000301143f
 # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_2		0x800008000301143f
 # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_3		0x80000C000301143f
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_0		0x800000000301183f
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_2		0x800008000301183f
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_3		0x80000C000301183f
-scom 0x800(000,008,00C)000301143f {
+# DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0		0x800000000301183f
+# DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_2		0x800008000301183f
+# DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_3		0x80000C000301183f
+scom 0x800(000,008,00C)000301143f {	# P0_0, P0_2, P0_3
 	bits	,	scom_data	,	expr			;
 #	0:47	,	0x000000000000,	any				;	# reserved
 	48:63	,	0xFFFF		,	(def_valid_p0)	;	# enable DATA_BIT_ENABLE_0_15
@@ -4193,10 +4262,10 @@ scom 0x800(000,008,00C)000301143f {
 # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_0		0x800100000301143f
 # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_3		0x80010C000301143f
 # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_4		0x800110000301143f
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_0		0x800100000301183f
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_3		0x80010C000301183f
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_4		0x800110000301183f
-scom 0x800(100,10C,110)000301143f {
+# DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_0		0x800100000301183f
+# DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_3		0x80010C000301183f
+# DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_4		0x800110000301183f
+scom 0x800(100,10C,110)000301143f { # P1_0, P1_2, P1_3
 	bits	,	scom_data	,	expr			;
 #	0:47	,	0x000000000000,	any				;	# reserved
 	48:63	,	0xFFFF		,	(def_valid_p1)	;	# enable DATA_BIT_ENABLE_0_15
@@ -4247,8 +4316,8 @@ scom 0x800108000301143f {
 	bits	,	scom_data	,	expr												;	# spare = 8_15
 #	0:47	,	0x000000000000,	any													;	# reserved
 	48:63	,	0xFFFF		,	((def_is_mba01) && (def_valid_p1) && (def_p1_has_spare_full))	;	# PortB DATA_BIT_ENABLE_0_15
-	48:63	,	0xFFF0		,	((def_is_mba01) && (def_valid_p1) && (def_p1_has_spare_upper))	;	# PortB disable lower dq0:3*
-	48:63	,	0xFF0F		,	((def_is_mba01) && (def_valid_p1) && (def_p1_has_spare_lower))	;	# PortB disable upper dq4:7*
+	48:63	,	0xFFF0		,	((def_is_mba01) && (def_valid_p1) && (def_p1_has_spare_upper))	;	# PortB disable lower dq0:3
+	48:63	,	0xFF0F		,	((def_is_mba01) && (def_valid_p1) && (def_p1_has_spare_lower))	;	# PortB disable upper dq4:7
 	48:63	,	0xFF00		,	((def_is_mba01) && (def_valid_p1) && (def_p1_no_spare))			;	# PortB disable spare byte
 # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_2		0x800108000301183f
 	48:63	,	0xFFFF		,	((def_is_mba23) && (def_valid_p1))					;	# P3_2
@@ -4258,14 +4327,15 @@ scom 0x800108000301143f {
 # ---------------------------------------------------------------------------------------
 # DP18 Data Bit Enable 1	(defaults to 0's)
 #
-# Centaur has mapped DP18 data bits 16:23 to be DQS, so 0's for this register is fine.
+# Centaur has mapped DP18 data bits 16:23 to be DQS, but this register bits 48:55 are for
+# changing these lanes to be dq bits, so we should leave them at 0's. (per Dave Stauffer)
 #
 # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0		0x001	0x800000010301143f
 #PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_ENABLE1_L2
 #scom 0x800(0,1)(00,04,08,0C,10)010301143f {	# ENABLE1_P[0:1]_[0:4]
-# scom 0x800(0,1)3C010301143f {	# ENABLE0_P[0:1]_[0:4] via broadcast
+# scom 0x800(0,1)3C010301143f {	# ENABLE1_P[0:1]_[0:4] via broadcast
 # 	bits	,	scom_data		;
-#	0:47	,	0x000000000000	;	# reserved
+##	0:47	,	0x000000000000	;	# reserved
 # 	48:55	,	0b00000000		;	# data_bit_enable_16_23
 # 	56		,	0b0				;	# DFT_FORCE_OUTPUTS
 # 	57		,	0b0				;	# DFT_PRBS7_GEN_EN
@@ -4303,8 +4373,8 @@ scom 0x800108000301143f {
 # DPHY01_DDRPHY_ADR_BIT_ENABLE_P0_ADR0		0x000	0x800040000301143f
 # PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.P_REG_A_00_L2
 scom 0x800(040,044,140,144)000301143F {	# _P[0:1]_ADR[0:1]
-#	0:47	,	0x000000000000	;	# reserved
 	bits	,	scom_data		;
+#	0:47	,	0x000000000000	;	# reserved
 	48:63	,	0xFFF0			;	# bits 12:15 not used in ADR[0:1]
 }
 scom 0x800(048,04C,148,14C)000301143F {	# _P[0:1]_ADR[2:3]
@@ -4341,7 +4411,7 @@ scom 0x800(048,04C,148,14C)000301143F {	# _P[0:1]_ADR[2:3]
 # DPHY01_DDRPHY_ADR_DELAY0_P0_ADR0		0x004-00B	0x800040040301143f
 # PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_A_09_L2
 #====================================================================================
-#   PORT 0 / 2 
+#   PORT 0 / 2
 #====================================================================================
 #-- Port 0/2  ADR 0 ------------------------------------------------------------
 scom 0x800040040301143F {	# DPHY01_DDRPHY_ADR_DELAY0_P0_ADR0
@@ -4447,7 +4517,6 @@ scom 0x800048040301143F {	# DPHY01_DDRPHY_ADR_DELAY0_P0_ADR2
 #	0:47	,	0x000000000000		,	any										;	# reserved
 	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12[0])		,	(def_is_mba01)	;	# P0 L0	, A_A12
 	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[0])		,	(def_is_mba01)	;	# P0 L1	, A_A0	centerlane
-#	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[0] | (def_CL_adj))		,	(def_is_mba01)	;	# P0 L1	, A_A0	centerlane
 	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1[0])		,	(def_is_mba23)	;	# P2 L0	, C_A1
 	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6[0])		,	(def_is_mba23)	;	# P2 L1	, C_A6
 }
@@ -4557,7 +4626,7 @@ scom 0x80004C0A0301143F {	# DPHY01.DDRPHY_ADR_DELAY6_P0_ADR3
 	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3[0])	,	(def_is_mba23)	;	# P2 L13, C0_CS3n
 }
 #====================================================================================
-#   PORT 1 / 3 
+#   PORT 1 / 3
 #====================================================================================
 #-- Port 1/3  ADR 0------------------------------------------------------------
 scom 0x800140040301143F {	# DPHY01_DDRPHY_ADR_DELAY0_P1_ADR0
@@ -5043,12 +5112,17 @@ scom 0x800(0,1)3C070301143F {					#_P[0:1]_[0:4] via broadcast
 #       ----------------------------------
 #       bits	0 1 2 3   4 5  6 7   8 9  10 11 (10:15 unused)
 #       ==============================================================
-#     possible spare (x4)
+#     possible spare (x4) Full[both nibbles]
 #       0x8640  1 0 0 0   0 1  1 0   0 1  0 0  = x4 no-swizzle, 			q0=16, q1=18, q2=20, q3=22
 #       0x4A40  0 1 0 0   1 0  1 0   0 1  0 0  = x4 swizzle quad0/1,		q0=18, q1=16, q2=20, q3=22
 #       0x8580  1 0 0 0   0 1  0 1   1 0  0 0  = x4 swizzle quad2/3,		q0=16, q1=18, q2=22, q3=20
 #       0x4980  0 1 0 0   1 0  0 1   1 0  0 0  = x4 swizzle quad0/1 & 2/3,	q0=18, q1=16, q2=22, q3=20
 #
+#       0x8600  1 0 0 0   0 1  1 0   0 0  0 0  = x4 no swizzle, disable upper nibble
+#       0x8440  1 0 0 0   0 1  0 0   0 1  0 0  = x4 no swizzle, disable lower nibble
+#       0x8480  1 0 0 0   0 1  0 0   1 0  0 0  = x4 swizzle quad2/3, disable upper nibble
+#       0x8500  1 0 0 0   0 1  0 1   0 0  0 0  = x4 swizzle quad2/3, disable lower nibble
+#
 #	  no spare (x4)
 #       0x8400  1 0 0 0   0 1  0 0   0 0  0 0  = x4 no-swizzle,				q0=16, q1=18, q2=n/a, q3=n/a
 #       0x4800  0 1 0 0   1 0  0 0   0 0  0 0  = x4 swizzle quad0/1,		q0=18, q1=16, q2=n/a, q3=n/a
@@ -5110,12 +5184,26 @@ scom 0x8000008(4,5)0301143F {	# _RP[0:3] via broadcast bit
 }
 
 #   RANK_PAIR[0:3], RP[0:3] _P0_1
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1		0x800004840301143F
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_1				0x800004850301143F
-scom 0x8000048(4,5)0301143F {	# _RP[0:3] via broadcast bit
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1		0x800004040301143F
+scom 0x800004840301143F {	# _RP[0:3] via broadcast bit
 # P0_1
 	bits	,	scom_data	,	expr														;
-#	0:47	,	0x000000000000,	any															;	# reserved
+#	0:47	,	0x000000000000,	any															;	# reserved		PORT A
+	48:63	,	0x8400		,	((def_is_mba01) && (def_p0_no_spare) && (def_is_x4))		;	# x4 no-spare no swizzle
+#	48:63	,	0x8580		,	((def_is_mba01) && (def_is_x4))								;	# x4 any spare swizzle quad2/3
+	48:63	,	0x8580		,	((def_is_mba01) && (def_is_x4) && ((def_p0_has_spare_upper) || (def_p0_has_spare_lower)));	# x4 spare set
+	48:63	,	0x0CC0		,	((def_is_mba01) && (def_p0_has_spare_full) && (def_is_x8))	;	# x8 swizzle quad0/1 & 2/3
+	48:63	,	0x0C00		,	((def_is_mba01) && (def_p0_no_spare) && (def_is_x8))		;	# x8 swizzle quad0/1
+# P2_1
+	48:63	,	0x8580		,	((def_is_mba23) && (def_is_x4))					;	# x4 swizzle quad2/3
+	48:63	,	0xC300		,	((def_is_mba23) && (def_is_x8))					;	# x8 no swizzle
+	48:63	,	0x0000		,	any												;
+}
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_1				0x800004050301143F
+scom 0x800004850301143F {	# _RP[0:3] via broadcast bit
+# P0_1
+	bits	,	scom_data	,	expr														;
+#	0:47	,	0x000000000000,	any															;	# reserved		PORT A
 	48:63	,	0x8580		,	((def_is_mba01) && (def_p0_has_spare_full) && (def_is_x4))	;	# x4 spare swizzle quad2/3
 	48:63	,	0x8500		,	((def_is_mba01) && (def_p0_has_spare_upper) && (def_is_x4))	;	# disable lower dqs
 	48:63	,	0x8480		,	((def_is_mba01) && (def_p0_has_spare_lower) && (def_is_x4))	;	# disable upper dqs
@@ -5129,8 +5217,8 @@ scom 0x8000048(4,5)0301143F {	# _RP[0:3] via broadcast bit
 }
 
 #   RANK_PAIR[0:3], RP[0:3] _P0_2
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2		0x800008840301143F
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_2				0x800008850301143F
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2		0x800008040301143F
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_2				0x800008050301143F
 scom 0x8000088(4,5)0301143F {	# _RP[0:3] via broadcast bit
 # P0_2
 	bits	,	scom_data	,	expr							;
@@ -5144,8 +5232,8 @@ scom 0x8000088(4,5)0301143F {	# _RP[0:3] via broadcast bit
 }
 
 #   RANK_PAIR[0:3], RP[0:3] _P0_3
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3		0x80000C840301143F
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_3				0x80000C850301143F
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3		0x80000C040301143F
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_3				0x80000C050301143F
 scom 0x80000C8(4,5)0301143F {	# _RP[0:3] via broadcast bit
 # P0_3
 	bits	,	scom_data	,	expr												;
@@ -5160,16 +5248,29 @@ scom 0x80000C8(4,5)0301143F {	# _RP[0:3] via broadcast bit
 }
 
 #   RANK_PAIR[0:3], RP[0:3] _P0_4
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4		0x800010840301143F
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_4				0x800010850301143F
-scom 0x8000108(4,5)0301143F {	# _RP[0:3] via broadcast bit
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4		0x800010040301143F
+scom 0x800010840301143F {	# _RP[0:3] via broadcast bit
+# P0_4
+	bits	,	scom_data	,	expr											;
+#	0:47	,	0x000000000000,	any												;	# reserved
+	48:63	,	0x8640		,	((def_is_mba01) && (def_is_x4))					;	# x4 no swizzle
+	48:63	,	0x0F00		,	((def_is_mba01) && (def_is_x8))					;	# x8 swizzle quad0/1
+# P2_4
+	48:63	,	0x8400		,	((def_is_mba23) && (def_p0_no_spare) && (def_is_x4))	;	# x4 no-spare no swizzle
+	48:63	,	0x8640		,	((def_is_mba23) && (def_is_x4) && ((def_p0_has_spare_upper) || (def_p0_has_spare_lower)));	# x4 spare no swizzle  PORT C
+	48:63	,	0x0F00		,	((def_is_mba23) && (def_p0_has_spare_full) && (def_is_x8))	;	# x8 swizzle quad0/1
+	48:63	,	0x0C00		,	((def_is_mba23) && (def_p0_no_spare) && (def_is_x8))	;	# x8 swizzle quad0/1
+	48:63	,	0x0000		,	any													;
+}
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_4				0x800010050301143F
+scom 0x800010850301143F {	# _RP[0:3] via broadcast bit
 # P0_4
 	bits	,	scom_data	,	expr											;
 #	0:47	,	0x000000000000,	any												;	# reserved
 	48:63	,	0x8640		,	((def_is_mba01) && (def_is_x4))					;	# x4 no swizzle
 	48:63	,	0x0F00		,	((def_is_mba01) && (def_is_x8))					;	# x8 swizzle quad0/1
 # P2_4
-	48:63	,	0x8640		,	((def_is_mba23) && (def_p0_has_spare_full) && (def_is_x4))	;	# x4 spare no swizzle
+	48:63	,	0x8640		,	((def_is_mba23) && (def_p0_has_spare_full) && (def_is_x4))	;	# x4 spare no swizzle  PORT C
 	48:63	,	0x8440		,	((def_is_mba23) && (def_p0_has_spare_upper) && (def_is_x4))	;	# disable lower dqs
 	48:63	,	0x8600		,	((def_is_mba23) && (def_p0_has_spare_lower) && (def_is_x4))	;	# disable upper dqs
 	48:63	,	0x8400		,	((def_is_mba23) && (def_p0_no_spare) && (def_is_x4))	;	# x4 no-spare no swizzle
@@ -5195,9 +5296,23 @@ scom 0x8001008(4,5)0301143F {	# _RP[0:3] via broadcast bit
 }
 
 #   RANK_PAIR[0:3]_, P1_1
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1		0x800104840301143F
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_1				0x800104850301143F
-scom 0x8001048(4,5)0301143F {	# _RP[0:3] via broadcast bit
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1		0x800104040301143F
+scom 0x800104840301143F {	# _RP[0:3] via broadcast bit
+# P1_1
+	bits	,	scom_data	,	expr												;
+#	0:47	,	0x000000000000,	any													;	# reserved
+	48:63	,	0x8640		,	((def_is_mba01) && (def_is_x4) && (def_is_type1))	;	# x4 no swizzle
+	48:63	,	0x4A40		,	((def_is_mba01) && (def_is_x4))						;	# x4 swizzle quad0/1
+	48:63	,	0xC300		,	((def_is_mba01) && (def_is_x8))						;	# x8 no swizzle
+# P3_1
+	48:63	,	0x8400		,	((def_is_mba23) && (def_p1_no_spare) && (def_is_x4))	;	# x4 no-spare no swizzle
+	48:63	,	0x8640		,	((def_is_mba23) && (def_is_x4) && ((def_p1_has_spare_upper) || (def_p1_has_spare_lower)));	# x4 spare no swizzle  PORT D
+	48:63	,	0xC300		,	((def_is_mba23) && (def_p1_has_spare_full) && (def_is_x8))	;	# x8 no swizzle
+	48:63	,	0xC000		,	((def_is_mba23) && (def_p1_no_spare) && (def_is_x8))	;	# x8 no swizzle
+	48:63	,	0x0000		,	any													;
+}
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_1				0x800104050301143F
+scom 0x800104850301143F {	# _RP[0:3] via broadcast bit
 # P1_1
 	bits	,	scom_data	,	expr												;
 #	0:47	,	0x000000000000,	any													;	# reserved
@@ -5205,7 +5320,7 @@ scom 0x8001048(4,5)0301143F {	# _RP[0:3] via broadcast bit
 	48:63	,	0x4A40		,	((def_is_mba01) && (def_is_x4))						;	# x4 swizzle quad0/1
 	48:63	,	0xC300		,	((def_is_mba01) && (def_is_x8))						;	# x8 no swizzle
 # P3_1
-	48:63	,	0x8640		,	((def_is_mba23) && (def_p1_has_spare_full) && (def_is_x4))	;	# x4 spare no swizzle
+	48:63	,	0x8640		,	((def_is_mba23) && (def_p1_has_spare_full) && (def_is_x4))	;	# x4 spare no swizzle  PORT D
 	48:63	,	0x8440		,	((def_is_mba23) && (def_p1_has_spare_upper) && (def_is_x4))	;	# disable lower dqs
 	48:63	,	0x8600		,	((def_is_mba23) && (def_p1_has_spare_lower) && (def_is_x4))	;	# disable upper dqs
 	48:63	,	0x8400		,	((def_is_mba23) && (def_p1_no_spare) && (def_is_x4))	;	# x4 no-spare no swizzle
@@ -5215,9 +5330,22 @@ scom 0x8001048(4,5)0301143F {	# _RP[0:3] via broadcast bit
 }
 
 #   RANK_PAIR[0:3], RP[0:3] _P1_2
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2		0x800108840301143F
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_2				0x800108850301143F
-scom 0x8001088(4,5)0301143F {	# _RP[0:3] via broadcast bit
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2		0x800108040301143F
+scom 0x800108840301143F {	# _RP[0:3] via broadcast bit
+# P1_2
+	bits	,	scom_data	,	expr											;
+#	0:47	,	0x000000000000,	any												;	# reserved
+	48:63	,	0x8400		,	((def_is_mba01) && (def_p1_no_spare) && (def_is_x4))		;	# x4 no-spare no swizzle
+	48:63	,	0x8640		,	((def_is_mba01) && (def_is_x4) && ((def_p1_has_spare_upper) || (def_p1_has_spare_lower)));	# x4 spare no swizzle
+	48:63	,	0x0CC0		,	((def_is_mba01) && (def_p1_has_spare_full) && (def_is_x8))	;	# x8 swizzle quad0/1 & 2/3
+	48:63	,	0x0C00		,	((def_is_mba01) && (def_p1_no_spare) && (def_is_x8))		;	# x8 swizzle quad0/1
+# P3_2
+	48:63	,	0x8580		,	((def_is_mba23) && (def_is_x4))					;	# x4 swizzle quad2/3
+	48:63	,	0x0F00		,	((def_is_mba23) && (def_is_x8))					;	# x8 swizzle quad0/1
+	48:63	,	0x0000		,	any												;
+}
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_2				0x800108050301143F
+scom 0x800108850301143F {	# _RP[0:3] via broadcast bit
 # P1_2
 	bits	,	scom_data	,	expr											;
 #	0:47	,	0x000000000000,	any												;	# reserved
@@ -5234,8 +5362,8 @@ scom 0x8001088(4,5)0301143F {	# _RP[0:3] via broadcast bit
 }
 
 #   RANK_PAIR[0:3], RP[0:3] _P1_3
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3		0x80010C840301143F
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_3				0x80010C850301143F
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3		0x80010C040301143F
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_3				0x80010C050301143F
 scom 0x80010C8(4,5)0301143F {	# _RP[0:3] via broadcast bit
 # P1_3
 	bits	,	scom_data	,	expr												;
@@ -5250,8 +5378,8 @@ scom 0x80010C8(4,5)0301143F {	# _RP[0:3] via broadcast bit
 }
 
 #   RANK_PAIR[0:3], RP[0:3] _P1_4
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4		0x800110840301143F
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_4				0x800110850301143F
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4		0x800110040301143F
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_4				0x800110050301143F
 scom 0x8001108(4,5)0301143F {	# _RP[0:3] via broadcast bit
 # P1_4
 	bits	,	scom_data	,	expr							;
@@ -5263,4 +5391,3 @@ scom 0x8001108(4,5)0301143F {	# _RP[0:3] via broadcast bit
 	48:63	,	0x0CC0		,	((def_is_mba23) && (def_is_x8))	;	# x8 swizzle quad0/1 & 2/3
 	48:63	,	0x0000		,	any								;
 }
-
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config.xml b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config.xml
new file mode 100644
index 000000000..2b78bb57f
--- /dev/null
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config.xml
@@ -0,0 +1,30 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+<!-- $Id: memory_mss_eff_config.xml,v 1.1 2013/06/19 18:27:53 bellows Exp $ -->
+<!-- For file ../../ipl/fapi/mss_eff_config.C -->
+<!-- // *! OWNER NAME  : Anuwat Saetow     Email: asaetow@us.ibm.com -->
+<!-- // *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com -->
+
+
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_cke_map.xml b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_cke_map.xml
new file mode 100644
index 000000000..04bd016dd
--- /dev/null
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_cke_map.xml
@@ -0,0 +1,30 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_cke_map.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+<!-- $Id: memory_mss_eff_config_cke_map.xml,v 1.1 2013/06/19 18:27:55 bellows Exp $ -->
+<!-- For file ../../ipl/fapi/mss_eff_config_cke_map.C -->
+<!-- // *! OWNER NAME  : Anuwat Saetow     Email: asaetow@us.ibm.com -->
+<!-- // *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com -->
+
+
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_rank_group.xml b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_rank_group.xml
new file mode 100644
index 000000000..e643c0456
--- /dev/null
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_rank_group.xml
@@ -0,0 +1,37 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_rank_group.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+<!-- $Id: memory_mss_eff_config_rank_group.xml,v 1.1 2013/06/19 18:27:57 bellows Exp $ -->
+<!-- For file ../../ipl/fapi/mss_eff_config_rank_group.C -->
+<!-- // *! OWNER NAME  : Anuwat Saetow     Email: asaetow@us.ibm.com -->
+<!-- // *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com -->
+<!-- //         |          |         | Changed BACKUP to Mark Bellows. -->
+
+<!-- Original Source for RC_ERROR_001A memory_errors.xml -->
+  <hwpError>
+    <rc>RC_MSS_EFF_CONFIG_RC_ERROR_001A</rc>
+    <description>Plug rule violation in EFF_CONFIG.</description>
+</hwpError>
+
+
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_termination.xml b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_termination.xml
new file mode 100644
index 000000000..3fb194ac6
--- /dev/null
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_termination.xml
@@ -0,0 +1,30 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_termination.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+<!-- $Id: memory_mss_eff_config_termination.xml,v 1.1 2013/06/19 18:27:59 bellows Exp $ -->
+<!-- For file ../../ipl/fapi/mss_eff_config_termination.C -->
+<!-- // *! OWNER NAME  : Dave Cadigan      Email: dcadiga@us.ibm.com -->
+<!-- // *! BACKUP NAME : Anuwat Saetow     Email: asaetow@us.ibm.com -->
+
+
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C
index 6d250915a..3daec80bd 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.H
index 6656efad5..532e50f6e 100755
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.H
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C
index 3c3c7b309..86037b676 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_shmoo.C,v 1.5 2013/05/20 08:43:21 sauchadh Exp $
+// $Id: mss_eff_config_shmoo.C,v 1.6 2013/06/06 05:45:16 sauchadh Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_shmoo.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -44,7 +44,8 @@
 //   1.2   | sauchadh |13-Mar-13| Added Schmoo related attributes from mss_eff_config.C 
 //   1.3   | sauchadh |17-Apr-13| Changed mcbist_addr_modes value to 1
 //   1.4   | sauchadh |10-May-13| Fixed FW comments
-//   1.5   | sauchadh |15-May-13| Fixed FW comments  
+//   1.5   | sauchadh |15-May-13| Fixed FW comments
+//   1.6   | sauchadh |6-Jun-13 | Added some more attributes
 
 //----------------------------------------------------------------------
 //  My Includes
@@ -109,8 +110,18 @@ fapi::ReturnCode mss_eff_config_shmoo(const fapi::Target & i_target_mba) {
    uint8_t cen_slew_rate_cntl_schmoo[2] = { 0x00, 0x00 };
    uint8_t cen_slew_rate_addr_schmoo[2] = { 0x00, 0x00 };
    uint8_t cen_slew_rate_clk_schmoo[2] = { 0x00, 0x00 };
-   uint8_t cen_slew_rate_spcke_schmoo[2] = { 0x00, 0x00 }; 
-      
+   uint8_t cen_slew_rate_spcke_schmoo[2] = { 0x00, 0x00 };
+   uint8_t mcb_print_disable=0;
+   uint8_t mcb_data_en=0;
+   uint8_t mcb_user_rank=0;
+   uint8_t mcb_user_bank=0;
+   uint8_t shmoo_mul_setup_call=0;
+   
+   rc = FAPI_ATTR_SET(ATTR_MCBIST_PRINTING_DISABLE, &i_target_mba, mcb_print_disable); if(rc) return rc; 
+   rc = FAPI_ATTR_SET(ATTR_MCBIST_DATA_ENABLE, &i_target_mba, mcb_data_en); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_MCBIST_USER_RANK, &i_target_mba, mcb_user_rank); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_MCBIST_USER_BANK, &i_target_mba, mcb_user_bank); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_SCHMOO_MULTIPLE_SETUP_CALL, &i_target_mba,shmoo_mul_setup_call); if(rc) return rc;
    rc = FAPI_ATTR_SET(ATTR_MCBIST_PATTERN, &i_target_mba, datapattern); if(rc) return rc; 
    rc = FAPI_ATTR_SET(ATTR_MCBIST_TEST_TYPE, &i_target_mba, testtype); if(rc) return rc;
    rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_MODES, &i_target_mba, addr_modes); if(rc) return rc;
@@ -150,7 +161,9 @@ fapi::ReturnCode mss_eff_config_shmoo(const fapi::Target & i_target_mba) {
    rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CNTL_SCHMOO, &i_target_mba, cen_slew_rate_cntl_schmoo); if(rc) return rc;
    rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_ADDR_SCHMOO, &i_target_mba, cen_slew_rate_addr_schmoo); if(rc) return rc;
    rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CLK_SCHMOO, &i_target_mba, cen_slew_rate_clk_schmoo); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_SPCKE_SCHMOO, &i_target_mba, cen_slew_rate_spcke_schmoo); if(rc) return rc; 
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_SPCKE_SCHMOO, &i_target_mba, cen_slew_rate_spcke_schmoo); if(rc) return rc;
+   
+
        
    FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString());
    return rc;
diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile
index 608f4d082..316d73f59 100644
--- a/src/usr/hwpf/makefile
+++ b/src/usr/hwpf/makefile
@@ -102,7 +102,20 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml   \
     hwp/dram_training/mss_scominit/memory_mss_scominit.xml \
     hwp/dram_training/mss_draminit_trainadv/memory_mss_mcbist_common.xml \
     hwp/dram_initialization/proc_setup_bars/memory_mss_setup_bars.xml \
-    hwp/slave_sbe/proc_cen_ref_clk_enable/proc_cen_ref_clk_enable_errors.xml
+    hwp/slave_sbe/proc_cen_ref_clk_enable/proc_cen_ref_clk_enable_errors.xml \
+    hwp/dmi_training/mss_getecid/memory_mss_get_cen_ecid.xml \
+    hwp/dram_initialization/mss_extent_setup/memory_mss_extent_setup.xml \
+    hwp/dram_initialization/mss_thermal_init/memory_mss_thermal_init.xml \
+    hwp/dram_training/mss_draminit/memory_mss_draminit.xml \
+    hwp/dram_training/mss_draminit_mc/memory_mss_draminit_mc.xml \
+    hwp/dram_training/mss_draminit_trainadv/memory_mss_access_delay_reg.xml \
+    hwp/dram_training/mss_draminit_trainadv/memory_mss_draminit_training_advanced.xml \
+    hwp/dram_training/mss_draminit_trainadv/memory_mss_generic_shmoo.xml \
+    hwp/dram_training/mss_draminit_trainadv/memory_mss_mcbist.xml \
+    hwp/mc_config/mss_eff_config/memory_mss_eff_config.xml \
+    hwp/mc_config/mss_eff_config/memory_mss_eff_config_cke_map.xml \
+    hwp/mc_config/mss_eff_config/memory_mss_eff_config_rank_group.xml \
+    hwp/mc_config/mss_eff_config/memory_mss_eff_config_termination.xml
 
 ## these get generated into obj/genfiles/AttributeIds.H
 HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \