SW310968: INITPROC: FSP&Hostboot - procedure updates for DDR4 and TSV (HWP Revie

CQ:SW310968
Change-Id: I39a02bea0981a8dd0336707524016a4b0eda268b
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19293
Reviewed-by: PRACHI GUPTA <pragupta@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Elizabeth Liner <eliner@us.ibm.com>
Tested-by: Elizabeth Liner <eliner@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19930
Tested-by: Jenkins Server
Tested-by: Jenkins OP Build CI
Tested-by: Jenkins OP HW
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

3 files changed, 130 insertions, 49 deletions

diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C
index 7e02eed24..0cb18e1f1 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_mcbist_address.C,v 1.18 2015/02/16 19:55:40 sglancy Exp $
+// $Id: mss_mcbist_address.C,v 1.21 2015/06/08 16:39:04 lwmulkey Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998, 2013
 // *!           All Rights Reserved -- Property of IBM
@@ -40,6 +40,7 @@
 //-------------------------------------------------------------------------------
 // Version:|Author: | Date:   | Comment:
 // --------|--------|---------|--------------------------------------------------
+// 1.20    |lwmulkey|06-JUN-15| Add slave rank support
 // 1.17    |sglancy |16-FEB-15| Merged FW comments with lab debugging needs
 // 1.17    |preeragh|15-Dec-14| Fix FW Review Comments
 // 1.16    |rwheeler|10-Nov-14| Update to address_generation for custom address string
@@ -86,7 +87,8 @@ fapi::ReturnCode address_generation(const fapi::Target & i_target_mba,
     uint8_t l_addr_inter = 0;
     uint8_t l_num_ranks_p0_dim0, l_num_ranks_p0_dim1, l_num_ranks_p1_dim0,
         l_num_ranks_p1_dim1;
-    uint8_t mr3_valid, mr2_valid, mr1_valid;
+    uint8_t l_master_ranks_p0_dim0;
+    uint8_t mr3_valid, mr2_valid, mr1_valid,sl0_valid,sl1_valid,sl2_valid;
     uint32_t rc_num;
     char S0[] = "b";
     //Choose a default buffer for the below
@@ -140,11 +142,16 @@ fapi::ReturnCode address_generation(const fapi::Target & i_target_mba,
     l_num_ranks_p0_dim1 = l_num_ranks_per_dimm[0][1];
     l_num_ranks_p1_dim0 = l_num_ranks_per_dimm[1][0];
     l_num_ranks_p1_dim1 = l_num_ranks_per_dimm[1][1];
+    l_master_ranks_p0_dim0 = l_num_master_ranks[0][0];
+
 
     //Initial all ranks are invalid
     mr3_valid = 0;
     mr2_valid = 0;
     mr1_valid = 0;
+    sl2_valid = 0;
+    sl1_valid = 0;
+    sl0_valid = 0;
 
     if ((l_num_ranks_p0_dim0 == 1 && l_num_ranks_p0_dim1 == 0) ||
         (l_num_ranks_p1_dim0 == 1 && l_num_ranks_p1_dim1 == 0)) //Single Rank case   -- default0
@@ -185,6 +192,24 @@ fapi::ReturnCode address_generation(const fapi::Target & i_target_mba,
         mr2_valid = 1;
         mr1_valid = 1;
     }
+    else if (((l_num_ranks_p0_dim0 == 4 && l_num_ranks_p0_dim1 == 0) ||
+              (l_num_ranks_p1_dim0 == 4 && l_num_ranks_p1_dim1 == 0)) &&
+               l_master_ranks_p0_dim0 == 1) //1r 4h stack
+    {
+        mr1_valid = 0;
+        sl1_valid = 1;
+        sl2_valid = 1; 
+    } 
+
+    else if (((l_num_ranks_p0_dim0 == 8 && l_num_ranks_p0_dim1 == 0) || 
+              (l_num_ranks_p1_dim0 == 8 && l_num_ranks_p1_dim1 == 0)) && 
+              (l_master_ranks_p0_dim0 == 2)) //2rx4 4h ddr4 3ds
+    {
+        mr3_valid = 1;
+        sl1_valid = 1;
+        sl2_valid = 1;
+    }
+
     else
     {
         FAPI_INF("-- Error ---- mcbist_addr_Check dimm_Config ----- ");
@@ -201,13 +226,13 @@ fapi::ReturnCode address_generation(const fapi::Target & i_target_mba,
     //custom addressing string is not to be used
     if(l_addr_inter != 4) {
        rc = parse_addr(i_target_mba, S0, mr3_valid, mr2_valid, mr1_valid,
-                    l_dram_rows, l_dram_cols, l_addr_inter);
+                    l_dram_rows, l_dram_cols, l_addr_inter,sl2_valid,sl1_valid,sl0_valid);
        if (rc) return rc;
     }
     else {
        FAPI_DBG("Custom addressing flag was selected");
        rc = parse_addr(i_target_mba, l_str_cust_addr, mr3_valid, mr2_valid, mr1_valid,
-                    l_dram_rows, l_dram_cols, l_addr_inter);
+                    l_dram_rows, l_dram_cols, l_addr_inter,sl2_valid,sl1_valid,sl0_valid);
        if (rc) return rc;
     }
 
@@ -221,12 +246,14 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba,
                             uint8_t mr1_valid,
                             uint8_t l_dram_rows,
                             uint8_t l_dram_cols,
-                            uint8_t l_addr_inter)
+                            uint8_t l_addr_inter,
+			    uint8_t sl2_valid,
+                            uint8_t sl1_valid,
+                            uint8_t sl0_valid)
 {
     fapi::ReturnCode rc;
     uint8_t i = MAX_ADDR_BITS;
 
-    uint8_t l_slave_rank = 0;
     uint8_t l_value;
     uint32_t l_value32 = 0;
     uint32_t l_sbit, rc_num;
@@ -1377,67 +1404,102 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba,
     l_value = i;
     rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64);
     if (rc) return rc;
-    //------- Enable these for later --- for now constant map to zero
-    if (l_slave_rank == 0)
+    if(sl2_valid==1)
     {
-        l_value = 0;
+
+      rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);
+      if (rc_num)
+      {
+         FAPI_ERR( "Error in function  parse_addr:");
+         rc.setEcmdError(rc_num);
+         return rc;
+      }
+      rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64);
+      if(rc) return rc;
     }
-    rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-    if (rc_num)
+    else
     {
-        FAPI_ERR("Error in function  parse_addr:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-    //FAPI_INF("sl2 Invalid");
-   
-    ////FAPI_INF("Value of i = %d",i);
+        rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);
+        if (rc_num)
+        {
+            FAPI_ERR( "Error in function  parse_addr:");rc.setEcmdError(rc_num);
+            return rc;
+        }
+        rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64);
+        if(rc) return rc;
+        FAPI_DBG("%s:sl2 Invalid",i_target_mba.toEcmdString());
+        i--;
+        //FAPI_DBG("%s:Value of i = %d",i);
+     }
+
     ////FAPI_INF("Inside strcmp sl1");
     l_sbit = 30;
     l_value = i;
     rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64);
     if (rc) return rc;
     //------- Enable these for later --- for now constant map to zero
-    if (l_slave_rank == 0)
+    if(sl1_valid==1)
     {
-        l_value = 0;
+
+      rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);
+      if (rc_num)
+      {
+         FAPI_ERR( "Error in function  parse_addr:");
+         rc.setEcmdError(rc_num);
+         return rc;
+      }
+      rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64);
+      if(rc) return rc;
     }
-    rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-    if (rc_num)
+    else
     {
-        FAPI_ERR("Error in function  parse_addr:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-    
-    //FAPI_INF("sl1 Invalid");
-    ////FAPI_INF("Value of i = %d",i);
+        rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);
+        if (rc_num)
+        {
+            FAPI_ERR( "Error in function  parse_addr:");rc.setEcmdError(rc_num);
+            return rc;
+        }
+        rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64);
+        if(rc) return rc;
+        FAPI_DBG("%s:sl1 Invalid",i_target_mba.toEcmdString());
+        i--;
+        //FAPI_DBG("%s:Value of i = %d",i);
+     }
     FAPI_INF("Inside strcmp sl0");
     l_sbit = 24;
     l_value = i;
     rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64);
     if (rc) return rc;
     //------- Enable these for later --- for now constant map to zero
-    if (l_slave_rank == 0)
+    if(sl0_valid==1)
     {
-        l_value = 0;
+
+      rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);
+      if (rc_num)
+      {
+         FAPI_ERR( "Error in function  parse_addr:");
+         rc.setEcmdError(rc_num);
+         return rc;
+      }
+      rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64);  
+      if(rc) return rc;
     }
-    rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-    if (rc_num)
+    else
     {
-        FAPI_ERR("Error in function  parse_addr:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-    //FAPI_INF("sl0 Invalid");
-    
-    ////FAPI_INF("Value of i = %d",i);
+        rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);
+        if (rc_num)
+        {
+            FAPI_ERR( "Error in function  parse_addr:");rc.setEcmdError(rc_num);
+            return rc;
+        }
+        rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64);  
+        if(rc) return rc;
+        FAPI_DBG("%s:sl0 Invalid",i_target_mba.toEcmdString());
+        i--;
+        //FAPI_DBG("%s:Value of i = %d",i);
+     }
+
+
 
     //------ Setting Start and end addr counters
 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H
index aef8c3d56..ecf6f2ed9 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_mcbist_address.H,v 1.8 2015/02/16 19:54:23 sglancy Exp $
+// $Id: mss_mcbist_address.H,v 1.9 2015/06/03 15:09:03 lwmulkey Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998, 2013
 // *!           All Rights Reserved -- Property of IBM
@@ -88,7 +88,7 @@ fapi::ReturnCode parse_addr(const fapi:: Target & i_target_mba,
                             uint8_t mr1_valid,
                             uint8_t l_dram_rows,
                             uint8_t l_dram_cols,
-                            uint8_t l_addr_inter);
+                            uint8_t l_addr_inter,uint8_t sl2_valid,uint8_t sl1_valid,uint8_t sl0_valid);
 
 }
 #endif
diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
index 2c55020c3..f9229dfd7 100755
--- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_scom_addresses.H,v 1.71 2015/02/12 22:05:07 gollub Exp $
+// $Id: cen_scom_addresses.H,v 1.72 2015/06/03 14:04:20 sglancy Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -46,6 +46,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.72   | sglancy  |03-JUN-15| Updated to include DQS_OFFSET registers - needed for DDR4 training
 //  1.71   | gollub   |12-FEB-15| Added MBACALFIR_OR, MBACALFIR_AND
 //         |          |         | Added MBA_DSM0
 //         |          |         | Added MBA_FARB0
@@ -1343,6 +1344,21 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_DFT_WRAP_STATUS_P1_4_0x8001101D0301143F , ULL
 //------------------------------------------------------------------------------
 //      ADR Output Force ATEST Control Registers
 //------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_0_0x800000370301143F , ULL(0x800000370301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_1_0x800004370301143F , ULL(0x800004370301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_2_0x800008370301143F , ULL(0x800008370301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_3_0x80000C370301143F , ULL(0x80000C370301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_4_0x800010370301143F , ULL(0x800010370301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_0_0x800100370301143F , ULL(0x800100370301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_1_0x800104370301143F , ULL(0x800104370301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_2_0x800108370301143F , ULL(0x800108370301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_3_0x80010C370301143F , ULL(0x80010C370301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_4_0x800110370301143F , ULL(0x800110370301143F) );
+
+
+//------------------------------------------------------------------------------
+//      ADR Output Force ATEST Control Registers
+//------------------------------------------------------------------------------
 CONST_UINT64_T( DPHY01_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_0x800080350301143F , ULL(0x800080350301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_0x800084350301143F , ULL(0x800084350301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0_0x800180350301143F , ULL(0x800180350301143F) );
@@ -1871,6 +1887,9 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: cen_scom_addresses.H,v $
+Revision 1.72  2015/06/03 14:04:20  sglancy
+Added DQS_OFFSET registers for training.C
+
 Revision 1.71  2015/02/12 22:05:07  gollub
 
 /!/  1.71   | gollub   |12-FEB-15| Added MBACALFIR_OR, MBACALFIR_AND