SW312753: INITPROC: add initialization for PCIE NEST FIR Action2 Register (HWP R

CQ:SW312753
Change-Id: I1161d21ccb2577f941bf780ede6eaf225a19d572
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19204
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: PRACHI GUPTA <pragupta@us.ibm.com>
Tested-by: PRACHI GUPTA <pragupta@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19285
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

4 files changed, 81 insertions, 11 deletions

diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C
index fd008021b..f189f668e 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_pcie_config.C,v 1.10 2014/11/18 17:41:59 jmcgill Exp $
+// $Id: proc_pcie_config.C,v 1.11 2015/06/29 01:47:49 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_config.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -135,7 +135,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir(
                      i, PROC_PCIE_CONFIG_PCIE_NEST_FIR[i]);
             break;
         }
-    
+
         // clear FIR WOF
         rc = fapiPutScom(i_target,
                          PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[i],
@@ -146,7 +146,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir(
                      i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[i]);
             break;
         }
-    
+
         // set action0
         rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0_VAL);
         if (rc_ecmd)
@@ -156,7 +156,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir(
             rc.setEcmdError(rc_ecmd);
             break;
         }
-    
+
         rc = fapiPutScom(i_target,
                          PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0[i],
                          data);
@@ -166,7 +166,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir(
                      i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0[i]);
             break;
         }
-    
+
         // set action1
         rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1_VAL);
         if (rc_ecmd)
@@ -176,7 +176,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir(
             rc.setEcmdError(rc_ecmd);
             break;
         }
-    
+
         rc = fapiPutScom(i_target,
                          PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[i],
                          data);
@@ -186,7 +186,37 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir(
                      i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[i]);
             break;
         }
-    
+
+        // set action2
+        fapi::ATTR_CHIP_EC_FEATURE_PCI_NEST_FIR_ACTION2_PRESENT_Type action2_present = 0;
+        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_PCI_NEST_FIR_ACTION2_PRESENT, &i_target, action2_present);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_pcie_config_pbcq_fir: fapiGetAttribute of ATTR_CHIP_EC_FEATURE_PCI_NEST_FIR_ACTION2_PRESENT failed");
+            break;
+        }
+        if (action2_present)
+        {
+            rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION2_VAL);
+            if (rc_ecmd)
+            {
+                FAPI_ERR("proc_pcie_config_pbcq_fir: Error 0x%x setting up PCIE Nest FIR Action2 register data buffer",
+                         rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+
+            rc = fapiPutScom(i_target,
+                             PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION2[i],
+                             data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%zd_FIR_ACTION2_0x%08X)",
+                         i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION2[i]);
+                break;
+            }
+        }
+
         // set mask
         rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK_VAL);
         if (rc_ecmd)
@@ -196,7 +226,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir(
             rc.setEcmdError(rc_ecmd);
             break;
         }
-    
+
         rc = fapiPutScom(i_target,
                          PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[i],
                          data);
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H
index 564471d99..63339f41d 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_pcie_config.H,v 1.5 2014/11/18 17:41:59 jmcgill Exp $
+// $Id: proc_pcie_config.H,v 1.7 2015/07/01 21:15:04 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_config.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -91,6 +91,14 @@ const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[PROC_PCIE_CONFIG_NUM_PHB]
     PCIE3_FIR_ACTION1_0x02012C07
 };
 
+const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION2[PROC_PCIE_CONFIG_NUM_PHB] =
+{
+    PCIE0_FIR_ACTION2_0x02012020,
+    PCIE1_FIR_ACTION2_0x02012420,
+    PCIE2_FIR_ACTION2_0x02012820,
+    PCIE3_FIR_ACTION2_0x02012C20
+};
+
 const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[PROC_PCIE_CONFIG_NUM_PHB] =
 {
     PCIE0_FIR_MASK_0x02012003,
@@ -101,6 +109,7 @@ const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[PROC_PCIE_CONFIG_NUM_PHB] =
 
 const uint64_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0_VAL = 0x5B0F819000000000ULL;
 const uint64_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1_VAL = 0x7F0F819000000000ULL;
+const uint64_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION2_VAL = 0xEFF07E0800000000ULL;
 const uint64_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK_VAL = 0x0030006E00000000ULL;
 
 
diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
index 16c3dc9eb..ba6ef0d27 100755
--- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_scom_addresses.H,v 1.195 2015/05/01 17:40:55 belldi Exp $
+// $Id: p8_scom_addresses.H,v 1.197 2015/06/29 01:43:56 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -441,6 +441,9 @@ CONST_UINT64_T( OCC_ITP_DEBUG_HALT_EN0_0x0006A00E     , ULL(0x0006A00E) );
 CONST_UINT64_T( OCC_ITP_DEBUG_HALT_EN1_0x0006A01E     , ULL(0x0006A01E) );
 CONST_UINT64_T( OCC_ITP_UNCOND_DEBUG_EN0_0x0006A00C   , ULL(0x0006A00C) );
 CONST_UINT64_T( OCC_ITP_UNCOND_DEBUG_EN1_0x0006A01C   , ULL(0x0006A01C) );
+CONST_UINT64_T( OCC_ITP_MISC_0x0006A020               , ULL(0x0006A020) );
+CONST_UINT64_T( OCC_ITP_MISC_AND_0x0006A021           , ULL(0x0006A021) );
+CONST_UINT64_T( OCC_ITP_MISC_OR_0x0006A022            , ULL(0x0006A022) );
 CONST_UINT64_T( OCC_ITP_TIMER0_0x0006A100             , ULL(0x0006A100) );
 CONST_UINT64_T( OCC_ITP_TIMER1_0x0006A101             , ULL(0x0006A101) );
 
@@ -1078,6 +1081,7 @@ CONST_UINT64_T( PCIE0_FIR_AND_0x02012001              , ULL(0x02012001) );
 CONST_UINT64_T( PCIE0_FIR_MASK_0x02012003             , ULL(0x02012003) );
 CONST_UINT64_T( PCIE0_FIR_ACTION0_0x02012006          , ULL(0x02012006) );
 CONST_UINT64_T( PCIE0_FIR_ACTION1_0x02012007          , ULL(0x02012007) );
+CONST_UINT64_T( PCIE0_FIR_ACTION2_0x02012020          , ULL(0x02012020) );
 CONST_UINT64_T( PCIE0_FIR_WOF_0x02012008              , ULL(0x02012008) );
 CONST_UINT64_T( PCIE0_NODAL_BAR0_0x02012010           , ULL(0x02012010) );
 CONST_UINT64_T( PCIE0_NODAL_BAR1_0x02012011           , ULL(0x02012011) );
@@ -1099,6 +1103,7 @@ CONST_UINT64_T( PCIE1_FIR_AND_0x02012401              , ULL(0x02012401) );
 CONST_UINT64_T( PCIE1_FIR_MASK_0x02012403             , ULL(0x02012403) );
 CONST_UINT64_T( PCIE1_FIR_ACTION0_0x02012406          , ULL(0x02012406) );
 CONST_UINT64_T( PCIE1_FIR_ACTION1_0x02012407          , ULL(0x02012407) );
+CONST_UINT64_T( PCIE1_FIR_ACTION2_0x02012420          , ULL(0x02012420) );
 CONST_UINT64_T( PCIE1_FIR_WOF_0x02012408              , ULL(0x02012408) );
 CONST_UINT64_T( PCIE1_NODAL_BAR0_0x02012410           , ULL(0x02012410) );
 CONST_UINT64_T( PCIE1_NODAL_BAR1_0x02012411           , ULL(0x02012411) );
@@ -1120,6 +1125,7 @@ CONST_UINT64_T( PCIE2_FIR_AND_0x02012801              , ULL(0x02012801) );
 CONST_UINT64_T( PCIE2_FIR_MASK_0x02012803             , ULL(0x02012803) );
 CONST_UINT64_T( PCIE2_FIR_ACTION0_0x02012806          , ULL(0x02012806) );
 CONST_UINT64_T( PCIE2_FIR_ACTION1_0x02012807          , ULL(0x02012807) );
+CONST_UINT64_T( PCIE2_FIR_ACTION2_0x02012820          , ULL(0x02012820) );
 CONST_UINT64_T( PCIE2_FIR_WOF_0x02012808              , ULL(0x02012808) );
 CONST_UINT64_T( PCIE2_NODAL_BAR0_0x02012810           , ULL(0x02012810) );
 CONST_UINT64_T( PCIE2_NODAL_BAR1_0x02012811           , ULL(0x02012811) );
@@ -1141,6 +1147,7 @@ CONST_UINT64_T( PCIE3_FIR_AND_0x02012C01              , ULL(0x02012C01) );
 CONST_UINT64_T( PCIE3_FIR_MASK_0x02012C03             , ULL(0x02012C03) );
 CONST_UINT64_T( PCIE3_FIR_ACTION0_0x02012C06          , ULL(0x02012C06) );
 CONST_UINT64_T( PCIE3_FIR_ACTION1_0x02012C07          , ULL(0x02012C07) );
+CONST_UINT64_T( PCIE3_FIR_ACTION2_0x02012C20          , ULL(0x02012C20) );
 CONST_UINT64_T( PCIE3_FIR_WOF_0x02012C08              , ULL(0x02012C08) );
 CONST_UINT64_T( PCIE3_NODAL_BAR0_0x02012C10           , ULL(0x02012C10) );
 CONST_UINT64_T( PCIE3_NODAL_BAR1_0x02012C11           , ULL(0x02012C11) );
@@ -2255,6 +2262,12 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: p8_scom_addresses.H,v $
+Revision 1.197  2015/06/29 01:43:56  jmcgill
+add definition for PCIE NEST FIR Action2 Registers (Naples only)
+
+Revision 1.196  2015/05/19 19:19:40  jmcgill
+add OCC core external interrupt register
+
 Revision 1.195  2015/05/01 17:40:55  belldi
 
 - Added constant: CONST_UINT64_T( CAPP_APC_MASTER_CAPI_CTL_0x02013019   , ULL(0x02013019) );
diff --git a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml
index 40e0b694d..2151ef8f5 100644
--- a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml
+++ b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml
@@ -22,7 +22,7 @@
 <!-- permissions and limitations under the License.                         -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-<!-- $Id: proc_chip_ec_feature.xml,v 1.61 2014/11/18 17:48:26 jmcgill Exp $ -->
+<!-- $Id: proc_chip_ec_feature.xml,v 1.62 2015/06/29 01:45:13 jmcgill Exp $ -->
 <!-- Defines the attributes that are based on EC level -->
 <attributes>
   <!-- ********************************************************************* -->
@@ -124,6 +124,24 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_PCI_NEST_FIR_ACTION2_PRESENT</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Returns if a chip contains PCI Nest FIR Action2 register.  True if:
+      Naples EC 0x10 or greater
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>