diff options
author | Matt Ploetz <maploetz@us.ibm.com> | 2013-11-08 15:24:29 -0600 |
---|---|---|
committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-11-08 20:20:06 -0600 |
commit | c2f709814c7b031e09c0aba66a201f0d63698674 (patch) | |
tree | d73e2dfa4ec15f025a68a60cfacd9ffe4865f318 /src | |
parent | f60b3727eb2af1217b6dd32a5828db4819a94dc2 (diff) | |
download | talos-hostboot-c2f709814c7b031e09c0aba66a201f0d63698674.tar.gz talos-hostboot-c2f709814c7b031e09c0aba66a201f0d63698674.zip |
INITPROC: Hostboot - SW229144 HOT P8 DD 2.0 bringup fixes
Change-Id: I4978dd4cf63d43d28ce2bd6bf9c1d0443a62de61
CMVC-Coreq: 902451
CQ: SW229144
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7134
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile | 96 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C | 26 |
2 files changed, 101 insertions, 21 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile index 0cb2aa567..d659aa828 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.a_x_pci_dmi_fir.scom.initfile,v 1.4 2013/09/30 16:54:36 jmcgill Exp $ +#-- $Id: p8.a_x_pci_dmi_fir.scom.initfile,v 1.5 2013/10/28 06:56:28 jmcgill Exp $ #------------------------------------------------------------------------------- #-- #-- (C) Copyright International Business Machines Corp. 2011 @@ -21,10 +21,13 @@ SyntaxVersion = 1 define mcl_enabled = ((ATTR_CHIP_REGIONS_TO_ENABLE[2] & 0x0080000000000000) != 0); define mcr_enabled = ((ATTR_CHIP_REGIONS_TO_ENABLE[2] & 0x0040000000000000) != 0); + define xbus_enabled = (ATTR_PROC_X_ENABLE == ENUM_ATTR_PROC_X_ENABLE_ENABLE); define abus_enabled = (ATTR_PROC_A_ENABLE == ENUM_ATTR_PROC_A_ENABLE_ENABLE); define pcie_enabled = (ATTR_PROC_PCIE_ENABLE == ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE); + define trace_on_scom = (ATTR_CHIP_EC_FEATURE_TRACE_CONTROL_ON_SCOM != 0); +define is_venice = (ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC != 0); #-------------------------------------------------------------------------------- #-- SCOM initializations @@ -43,13 +46,13 @@ scom 0x02011A06 { #-- IOMC0.BUSCTL.SCOM.FIR_ACTION1_REG scom 0x02011A07 { bits, scom_data, expr; - 0:63, 0xE07070707000C000, (mcl_enabled); + 0:63, 0x207878787800C000, (mcl_enabled); } #-- IOMC0.BUSCTL.SCOM.FIR_MASK_REG scom 0x02011A03 { bits, scom_data, expr; - 0:63, 0x1FFFFFFFFFFF0000, (mcl_enabled); + 0:63, 0xDFFFFFFFFFFF0000, (mcl_enabled); } #-- IOMC1.BUSCTL.SCOM.FIR_ACTION0_REG @@ -61,13 +64,13 @@ scom 0x02011E06 { #-- IOMC1.BUSCTL.SCOM.FIR_ACTION1_REG scom 0x02011E07 { bits, scom_data, expr; - 0:63, 0xE07070707000C000, (mcr_enabled); + 0:63, 0x207878787800C000, (mcr_enabled); } #-- IOMC1.BUSCTL.SCOM.FIR_MASK_REG scom 0x02011E03 { bits, scom_data, expr; - 0:63, 0x1FFFFFFFFFFF0000, (mcr_enabled); + 0:63, 0xDFFFFFFFFFFF0000, (mcr_enabled); } @@ -75,24 +78,87 @@ scom 0x02011E03 { #-- XBUS IO (EI4) #-- set base configuration for FIR, leaving link specific FIR bits *masked* #-- (will be unmasked by IO training procedure) + +#-- X0 +#-- XBUS01.X0.BUSCTL.SCOM.FIR_ACTION0_REG +scom 0x04011006 { + bits, scom_data, expr; + 0:63, 0x0000000000000000, ((xbus_enabled) && (is_venice)); +} + +#-- XBUS01.X0.BUSCTL.SCOM.FIR_ACTION1_REG +scom 0x04011007 { + bits, scom_data, expr; + 0:63, 0x207800000000C000, ((xbus_enabled) && (is_venice)); +} + +#-- XBUS01.X0.BUSCTL.SCOM.FIR_MASK_REG +scom 0x04011003 { + bits, scom_data, expr; + 0:63, 0xDFFFFFFFFFFF0000, ((xbus_enabled) && (is_venice)); +} + +#-- X1 #-- XBUS1.BUSCTL.SCOM.FIR_ACTION0_REG +#-- XBUS01.X1.BUSCTL.SCOM.FIR_ACTION0_REG scom 0x04011406 { bits, scom_data, expr; 0:63, 0x0000000000000000, (xbus_enabled); } #-- XBUS1.BUSCTL.SCOM.FIR_ACTION1_REG +#-- XBUS01.X1.BUSCTL.SCOM.FIR_ACTION1_REG scom 0x04011407 { bits, scom_data, expr; - 0:63, 0xE07070707070C000, (xbus_enabled); + 0:63, 0x207800000000C000, (xbus_enabled); } #-- XBUS1.BUSCTL.SCOM.FIR_MASK_REG +#-- XBUS01.X1.BUSCTL.SCOM.FIR_MASK_REG scom 0x04011403 { bits, scom_data, expr; - 0:63, 0x1FFFFFFFFFFF0000, (xbus_enabled); + 0:63, 0xDFFFFFFFFFFF0000, (xbus_enabled); } +#-- X3 +#-- XBUS23.X0.BUSCTL.SCOM.FIR_ACTION0_REG +scom 0x04011806 { + bits, scom_data, expr; + 0:63, 0x0000000000000000, ((xbus_enabled) && (is_venice)); +} + +#-- XBUS23.X0.BUSCTL.SCOM.FIR_ACTION1_REG +scom 0x04011807 { + bits, scom_data, expr; + 0:63, 0x207800000000C000, ((xbus_enabled) && (is_venice)); +} + +#-- XBUS23.X0.BUSCTL.SCOM.FIR_MASK_REG +scom 0x04011803 { + bits, scom_data, expr; + 0:63, 0xDFFFFFFFFFFF0000, ((xbus_enabled) && (is_venice)); +} + +#-- X2 +#-- XBUS23.X1.BUSCTL.SCOM.FIR_ACTION0_REG +scom 0x04011C06 { + bits, scom_data, expr; + 0:63, 0x0000000000000000, ((xbus_enabled) && (is_venice)); +} + +#-- XBUS23.X1.BUSCTL.SCOM.FIR_ACTION1_REG +scom 0x04011C07 { + bits, scom_data, expr; + 0:63, 0x207800000000C000, ((xbus_enabled) && (is_venice)); +} + +#-- XBUS23.X1.BUSCTL.SCOM.FIR_MASK_REG +scom 0x04011C03 { + bits, scom_data, expr; + 0:63, 0xDFFFFFFFFFFF0000, ((xbus_enabled) && (is_venice)); +} + + #-- XBUS PB (PBEN) #-- set base configuration for FIR, leaving link specific FIR bits *masked* #-- (will be unmasked by iovalid procedure) @@ -124,13 +190,13 @@ scom 0x04040010 { #-- EN.PB.TPC.EPS.FIR.LOCAL_FIR_ACTION1 scom 0x04040011 { bits, scom_data, expr; - 0:63, 0xFFFE000000000000, (xbus_enabled); + 0:63, 0x8002000000000000, (xbus_enabled); } #-- EN.PB.TPC.EPS.FIR.LOCAL_FIR_MASK scom 0x0404000D { bits, scom_data, expr; - 0:63, 0x0001FFFFFF800000, (xbus_enabled); + 0:63, 0x7FFDFFFFFF800000, (xbus_enabled); } #-- XBUS chiplet XFIR @@ -164,13 +230,13 @@ scom 0x08010C06 { #-- ABUS.BUSCTL.SCOM.FIR_ACTION1_REG scom 0x08010C07 { bits, scom_data, expr; - 0:63, 0xE07070707070C000, (abus_enabled); + 0:63, 0x207878787878C000, (abus_enabled); } #-- ABUS.BUSCTL.SCOM.FIR_MASK_REG scom 0x08010C03 { bits, scom_data, expr; - 0:63, 0x1FFFFFFFFFFF0000, (abus_enabled); + 0:63, 0xDFFFFFFFFFFF0000, (abus_enabled); } #-- ABUS PB (PBES) @@ -204,13 +270,13 @@ scom 0x08040010 { #-- ES.PBES_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION1 scom 0x08040011 { bits, scom_data, expr; - 0:63, 0xFFF0000000000000, (abus_enabled); + 0:63, 0x8000000000000000, (abus_enabled); } #-- ES.PBES_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_MASK scom 0x0804000D { bits, scom_data, expr; - 0:63, 0x000FFFFFFF800000, (abus_enabled); + 0:63, 0x7FFFFFFFFF800000, (abus_enabled); } #-- ABUS chiplet XFIR @@ -262,13 +328,13 @@ scom 0x09040010 { #-- ES.PE_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION1 scom 0x09040011 { bits, scom_data, expr; - 0:63, 0xFFF0000000000000, (pcie_enabled); + 0:63, 0x8000000000000000, (pcie_enabled); } #-- ES.PE_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_MASK scom 0x0904000D { bits, scom_data, expr; - 0:63, 0x000FFFFFFF800000, (pcie_enabled); + 0:63, 0x7FFFFFFFFF800000, (pcie_enabled); } #-- PCIE chiplet XFIR diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C index af09b1947..90ad8d69b 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_a_x_pci_dmi_pll_utils.C,v 1.4 2013/09/30 16:09:57 jmcgill Exp $ +// $Id: proc_a_x_pci_dmi_pll_utils.C,v 1.5 2013/10/28 06:45:46 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_utils.C,v $ //------------------------------------------------------------------------------ // *| @@ -110,6 +110,7 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_bndy( // return codes uint32_t rc_ecmd = 0; fapi::ReturnCode rc; + bool unmask_scan_collision = false; // mark function entry FAPI_DBG("Start"); @@ -122,7 +123,17 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_bndy( if (i_mask_scan_collision) { + FAPI_DBG("Reading value of Pervasive LFIR scan collision mask bit ..."); + rc = fapiGetScom(i_target, i_chiplet_base_scom_addr | GENERIC_PERV_LFIR_MASK_0x0004000D, data); + if (!rc.ok()) + { + FAPI_ERR("Error reading Pervasive LFIR Mask OR Register."); + break; + } + unmask_scan_collision = data.isBitClear(PERV_LFIR_SCAN_COLLISION_BIT); + FAPI_DBG("Masking Pervasive LFIR scan collision bit ..."); + rc_ecmd |= data.flushTo0(); rc_ecmd |= data.setBit(PERV_LFIR_SCAN_COLLISION_BIT); if (rc_ecmd) { @@ -271,12 +282,15 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_bndy( break; } - FAPI_DBG("Unmasking Pervasive LFIR scan collision bit ..."); - rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_PERV_LFIR_MASK_AND_0x0004000E, data); - if (!rc.ok()) + if (unmask_scan_collision) { - FAPI_ERR("Error writing Pervasive LFIR Mask And Register."); - break; + FAPI_DBG("Unmasking Pervasive LFIR scan collision bit ..."); + rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_PERV_LFIR_MASK_AND_0x0004000E, data); + if (!rc.ok()) + { + FAPI_ERR("Error writing Pervasive LFIR Mask And Register."); + break; + } } } } while(0); |