TULETA Bring Up - HW procedures update - Centaur PLL init 03/13/2013

Change-Id: If6c83a0b678e7007f78cf041916d36ab9504b927
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3537
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

9 files changed, 714 insertions, 296 deletions

diff --git a/src/include/usr/hwpf/istepreasoncodes.H b/src/include/usr/hwpf/istepreasoncodes.H
index 5706831e8..1d8c27e6d 100644
--- a/src/include/usr/hwpf/istepreasoncodes.H
+++ b/src/include/usr/hwpf/istepreasoncodes.H
@@ -115,6 +115,7 @@ enum istepModuleId
     ISTEP_PROC_XBUS_SCOMINIT                            = 0x43,
     ISTEP_PROC_ABUS_SCOMINIT                            = 0x44,
     ISTEP_PROC_DMI_SCOMINIT                             = 0x45,
+    ISTEP_MEM_PLL_INITF                                 = 0x46,
 };
 
 /**
diff --git a/src/usr/hwpf/hwp/dram_training/dram_training.C b/src/usr/hwpf/hwp/dram_training/dram_training.C
index ed3167def..3ffda2e3e 100644
--- a/src/usr/hwpf/hwp/dram_training/dram_training.C
+++ b/src/usr/hwpf/hwp/dram_training/dram_training.C
@@ -164,26 +164,6 @@ void*    call_mem_pll_initf( void *io_pArgs )
 
     TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mem_pll_initf entry" );
 
-    // call cen_mem_pll_initf.C
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mem_pll_initf exit" );
-
-    return  l_err;      // remove this when HWP is implemented
-    // return l_StepError.getErrorHandle();
-}
-
-
-//
-//  Wrapper function to call mem_pll_setup
-//
-void*    call_mem_pll_setup( void *io_pArgs )
-{
-    errlHndl_t l_err = NULL;
-
-    IStepError l_StepError;
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mem_pll_setup entry" );
-
     // Get all Centaur targets
     TARGETING::TargetHandleList l_membufTargetList;
     getAllChips(l_membufTargetList, TYPE_MEMBUF);
@@ -197,7 +177,7 @@ void*    call_mem_pll_setup( void *io_pArgs )
         const TARGETING::Target* l_pCentaur = *l_membuf_iter;
 
         TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "Running mem_pll_setup HWP on "
+                "Running cen_mem_pll_initf HWP on "
                 "target HUID %.8X", TARGETING::get_huid(l_pCentaur));
 
         // Cast to a FAPI type of target.
@@ -210,7 +190,7 @@ void*    call_mem_pll_setup( void *io_pArgs )
         if (l_err)
         {
             TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "ERROR 0x%.8X: mem_pll_initf HWP returns error",
+                      "ERROR 0x%.8X: cen_mem_pll_initf HWP returns error",
                       l_err->reasonCode());
 
             // capture the target data in the elog
@@ -221,8 +201,66 @@ void*    call_mem_pll_setup( void *io_pArgs )
         else
         {
             TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "SUCCESS: mem_pll_initf HWP( )" );
+                       "SUCCESS: cen_mem_pll_initf HWP( )" );
         }
+    }
+
+    if( l_err )
+    {
+        /*@
+         * @errortype
+         * @reasoncode  ISTEP_DRAM_TRAINING_FAILED
+         * @severity    ERRORLOG::ERRL_SEV_UNRECOVERABLE
+         * @moduleid    ISTEP_MEM_PLL_INITF
+         * @userdata1   bytes 0-1: plid identifying first error
+         *              bytes 2-3: reason code of first error
+         * @userdata2   bytes 0-1: total number of elogs included
+         *              bytes 2-3: N/A
+         * @devdesc     call to cen_mem_pll_initf has failed
+         */
+        l_StepError.addErrorDetails(ISTEP_DRAM_TRAINING_FAILED,
+                                    ISTEP_MEM_PLL_INITF,
+                                    l_err);
+
+        errlCommit( l_err, HWPF_COMP_ID );
+    }
+
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mem_pll_initf exit" );
+
+    return l_StepError.getErrorHandle();
+}
+
+
+//
+//  Wrapper function to call mem_pll_setup
+//
+void*    call_mem_pll_setup( void *io_pArgs )
+{
+    errlHndl_t l_err = NULL;
+
+    IStepError l_StepError;
+
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mem_pll_setup entry" );
+
+    // Get all Centaur targets
+    TARGETING::TargetHandleList l_membufTargetList;
+    getAllChips(l_membufTargetList, TYPE_MEMBUF);
+
+    for (TargetHandleList::const_iterator
+            l_membuf_iter = l_membufTargetList.begin();
+            l_membuf_iter != l_membufTargetList.end();
+            ++l_membuf_iter)
+    {
+        //  make a local copy of the target for ease of use
+        const TARGETING::Target* l_pCentaur = *l_membuf_iter;
+
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                "Running mem_pll_setup HWP on "
+                "target HUID %.8X", TARGETING::get_huid(l_pCentaur));
+
+        // Cast to a FAPI type of target.
+        const fapi::Target l_fapi_centaur( TARGET_TYPE_MEMBUF_CHIP,
+                 (const_cast<TARGETING::Target*>(l_pCentaur)));
 
         //  call cen_mem_pll_setup to verify lock
         FAPI_INVOKE_HWP(l_err, cen_mem_pll_setup, l_fapi_centaur);
diff --git a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C
index 21dcbdb7c..b052e3faa 100644
--- a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C
+++ b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_mem_pll_initf.C,v 1.3 2012/11/07 23:22:44 mfred Exp $
+// $Id: cen_mem_pll_initf.C,v 1.5 2013/03/04 17:56:24 mfred Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_pll_initf.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -31,6 +31,7 @@
 // *! DESCRIPTION : see additional comments below
 // *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
 // *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
+// *! SCREEN      : pervasive_screen
 // #! ADDITIONAL COMMENTS :
 //
 // The purpose of this procedure is scan the correct values into the Centaur chip MEM PLL controller.
@@ -74,7 +75,9 @@
 #include <cen_scom_addresses.H>
 #include <cen_mem_pll_initf.H>
 
-#define RING_LENGTH_TP_PLL_BNDY    442
+#include <p8_delta_scan_rw.h>
+#include <p8_ring_identification.H>
+
 
 //  Constants
 
@@ -86,278 +89,31 @@ const uint64_t CLK_REGION_FOR_SETPULSE = 0x0010040000000000ull;
 
 
 
-// The supported frequencies are 800, 1066, 1333, 1600, 1866, and 2133 MHz  (These are the DDR frequencies and the PLL output B frequencies.)
-
-// Here are the bit definitions for the Analog PLL controller:  (Checked with values from T.Diemoz Nov.7,2012)
-//
-//  Bits        Purpose                Value to be used for OutB=1600MHz (when using real HW PLL)
-// -------      --------------         ------------------------
-// 0 to 2       bypmode                000
-// 3            bypassn                1
-// 4 to 5       charmode               00
-// 6 to 8       cp_tune                101
-// 9 to 11      duty_adj               000
-// 12           fbkmode                0
-// 13 to 14     iref_tune              00
-// 15 to 34     jit_cntl               00000000000000000000
-// 35 to 45     lock_tune              01010000000
-// 46 to 54     mult                   011000000   (put different values here for different freqs)
-// 55 to 56     outsel                 00
-// 57 to 58     phasedet_tune          10
-// 59           fbksel                 0
-// 60 to 63     rangea                 0001        (put different values here for different freqs)
-// 64 to 67     rangeb                 0011        (put different values here for different freqs)
-// 68           refdiv                 0
-// 69 to 75     a2d_tune               0000000
-// 76 to 81     analogout_tune         000000
-// 82 to 83     vreg_tune              00
-// 84           ctst_tune              0
-// 85           lock_sel               0
-// 86           tstmode_en             0
-// 87           tstmode_ncap_lt        0
-// 88           tstmode_iref_lt        0
-// 89           tstmode_dt_lt          0
-// 90           tstmode_aout_lt        0
-// 91           tstmode_vcocmp_lt      0
-// 92           tstmode_ctst_lt        0
-// 93           tstmode_vco_sel        0
-// 94           cphase                 1
-// 95           e_mode_enable          0
-// 96 to 126    tune                   0000000000000000000000000000000
-// 127          outa_disable           0
-// 128          outb_disable           0
-// 129 to 130   vcodiv                 00
-// 131          digtestout             0
-// 132          reset                  0
-// 133 to 135   unused                 000
-
-// Take the above bit string and convert it to hex for the scan chain data.
-
-// Scan chain data for MEM PLL controller:
-
-//------------------------------
-// SIMULATION-ONLY PLL SETTINGS:
-//------------------------------
-// SIMULATION-ONLY Setting for PLL OutputB = 1600 Mhz  (Output B = 6up/6down)
-const uint64_t MEM_PLL_CNTRL0_SIM_FREQ_1600  = 0x128000000A0060D3ull;
-const uint64_t MEM_PLL_CNTRL1_SIM_FREQ_1600  = 0x7000000200000000ull;
-//const uint64_t MEM_PLL_CNTRL2_SIM_FREQ_1600  = 0x00;   //  TODO:  Put this value back in and remove temp value on the next line.
-const uint64_t MEM_PLL_CNTRL2_SIM_FREQ_1600  = 0x0F;   // Temp value:  Put F into some unused bits to make unique value. (For testing the putRing).
-
-//------------------------------
-// HARDWARE-ONLY PLL SETTINGS:
-//------------------------------
-// TODO adjust this HW setting for PLL OutputB = 800 Mhz
-const uint64_t MEM_PLL_CNTRL0_FREQ_800   = 0x128000000A018041ull;
-const uint64_t MEM_PLL_CNTRL1_FREQ_800   = 0x3000000200000000ull;
-const uint64_t MEM_PLL_CNTRL2_FREQ_800   = 0x00;
-
-// TODO adjust this HW setting for PLL OutputB = 1066 Mhz
-const uint64_t MEM_PLL_CNTRL0_FREQ_1066  = 0x128000000A018041ull;
-const uint64_t MEM_PLL_CNTRL1_FREQ_1066  = 0x3000000200000000ull;
-const uint64_t MEM_PLL_CNTRL2_FREQ_1066  = 0x00;
-
-// HW Setting for PLL OutputB = 1333 Mhz (Checked with values from T.Diemoz Nov.7,2012)
-const uint64_t MEM_PLL_CNTRL0_FREQ_1333  = 0x128000000A028041ull;
-const uint64_t MEM_PLL_CNTRL1_FREQ_1333  = 0x3000000200000000ull;
-const uint64_t MEM_PLL_CNTRL2_FREQ_1333  = 0x00;
-
-// HW Setting for PLL OutputB = 1600 Mhz (Checked with values from T.Diemoz Nov.7,2012)
-const uint64_t MEM_PLL_CNTRL0_FREQ_1600  = 0x128000000A018041ull;
-const uint64_t MEM_PLL_CNTRL1_FREQ_1600  = 0x3000000200000000ull;
-const uint64_t MEM_PLL_CNTRL2_FREQ_1600  = 0x00;
-
-// HW Setting for PLL OutputB = 1866 Mhz (Checked with values from T.Diemoz Nov.7,2012)
-const uint64_t MEM_PLL_CNTRL0_FREQ_1866  = 0x128000000A038045ull;
-const uint64_t MEM_PLL_CNTRL1_FREQ_1866  = 0xB000000200000000ull;
-const uint64_t MEM_PLL_CNTRL2_FREQ_1866  = 0x00;
-
-// TODO adjust this HW setting for PLL OutputB = 2133 Mhz
-const uint64_t MEM_PLL_CNTRL0_FREQ_2133  = 0x128000000A018041ull;
-const uint64_t MEM_PLL_CNTRL1_FREQ_2133  = 0x3000000200000000ull;
-const uint64_t MEM_PLL_CNTRL2_FREQ_2133  = 0x00;
-
-
 extern "C" {
 
 using namespace fapi;
 
-fapi::ReturnCode cen_mem_pll_initf(const fapi::Target & i_target)
-{
-    // Target is centaur
-
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase scom_data(64);
-    ecmdDataBufferBase pll_data(136);
-    ecmdDataBufferBase ring_data;
-
-    uint8_t   is_simulation        = 0;
-    uint32_t  mss_freq             = 0;
-    // uint8_t  mss_pll_lab_override = 0;
 
 
+//------------------------------------------------------------------------------
+// cen_load_pll_ring_from_buffer
+//------------------------------------------------------------------------------
+fapi::ReturnCode cen_load_pll_ring_from_buffer(const fapi::Target & i_target,
+                                               ecmdDataBufferBase i_scan_ring_data
+                                               )
+{
 
+    // Target is centaur
 
+    fapi::ReturnCode    rc;
+    uint32_t            rc_ecmd = 0;
+    ecmdDataBufferBase  scom_data(64);
 
 
-    FAPI_INF("********* cen_mem_pll_initf start *********");
+    FAPI_INF("Starting subroutine: cen_load_pll_ring_from_buffer...");
     do
     {
 
-        FAPI_DBG("Setting up the Centaur MEM PLL.");
-
-
-        //------------------------------------------
-        //  Read attributes for setting the PLL data
-        //------------------------------------------
-
-        // The code that loads the PLL scan ring data should choose the correct data to load based on
-        // the DDR frequency and voltage settings and a lab override value.
-        // The supported frequencies are 800, 1066, 1333, 1600, 1866, and 2133 MHz  (These are the DDR frequencies and the PLL output B frequencies.)
-        // The DDR frequency can be determined from attribute ATTR_MSS_FREQ  (in MHz)
-        // The DDR voltage can be determined from attribute ATTR_MSS_VOLT  (in millivolts)
-        // Get another attribute for selecting the "override" ring.    Use CQ to request an attribute.
-        // (The selection of rings should include an "override ring that can be used in the lab")
-
-
-        // Read the attributes
-        rc = FAPI_ATTR_GET( ATTR_IS_SIMULATION, NULL, is_simulation);
-        if (rc)
-        {
-            FAPI_ERR("Failed to get attribute: ATTR_IS_SIMULATION.");
-            break;
-        }
-//        rc = FAPI_ATTR_GET( ATTR_MSS_LAB_OVERRIDE_FOR_MEM_PLL, &i_target, mss_pll_lab_override);
-//        if (rc)
-//        {
-//            FAPI_ERR("Failed to get attribute: ATTR_MSS_LAB_OVERRIDE_FOR_MEM_PLL.");
-//            break;
-//        }
-        rc = FAPI_ATTR_GET( ATTR_MSS_FREQ, &i_target, mss_freq);
-        if (rc)
-        {
-            FAPI_ERR("Failed to get attribute: ATTR_MSS_FREQ.");
-            break;
-        }
-
-        FAPI_DBG("ATTR_IS_SIMULATION attribute is set to : %d.", is_simulation);
-//        FAPI_DBG("Lab override attribute is set to : %d.", mss_pll_lab_override);
-        FAPI_DBG("DDR frequency is set to : %d.", mss_freq);
-
-
-
-        //-----------------------------------------------
-        //  Set PLL control ring data based on attributes
-        //-----------------------------------------------
-
-        // TODO - How do we set the scan ring data for a lab override?
-
-        if (is_simulation)
-        {
-            rc_ecmd |= pll_data.setDoubleWord( 0, MEM_PLL_CNTRL0_SIM_FREQ_1600 );
-            rc_ecmd |= pll_data.setDoubleWord( 1, MEM_PLL_CNTRL1_SIM_FREQ_1600 );
-            rc_ecmd |= pll_data.setByte(      16, MEM_PLL_CNTRL2_SIM_FREQ_1600 );
-        }
-        else
-        {
-            // Use the attribute values to select the right PLL controller settings
-            // The supported frequencies are 800, 1066, 1333, 1600, 1866, and 2133 MHz  (These are the DDR frequencies and the PLL output B frequencies.)
-            if (mss_freq == 800)
-            {
-FAPI_ERR("PLL settings not specified for this frequency.  Defaulting to 1600MHz..");
-                rc_ecmd |= pll_data.setDoubleWord( 0, MEM_PLL_CNTRL0_FREQ_800 );
-                rc_ecmd |= pll_data.setDoubleWord( 1, MEM_PLL_CNTRL1_FREQ_800 );
-                rc_ecmd |= pll_data.setByte(      16, MEM_PLL_CNTRL2_FREQ_800 );
-            }
-            else if (mss_freq == 1066)
-            {
-FAPI_ERR("PLL settings not specified for this frequency.  Defaulting to 1600MHz..");
-                rc_ecmd |= pll_data.setDoubleWord( 0, MEM_PLL_CNTRL0_FREQ_1066 );
-                rc_ecmd |= pll_data.setDoubleWord( 1, MEM_PLL_CNTRL1_FREQ_1066 );
-                rc_ecmd |= pll_data.setByte(      16, MEM_PLL_CNTRL2_FREQ_1066 );
-            }
-            else if (mss_freq == 1333)
-            {
-                rc_ecmd |= pll_data.setDoubleWord( 0, MEM_PLL_CNTRL0_FREQ_1333 );
-                rc_ecmd |= pll_data.setDoubleWord( 1, MEM_PLL_CNTRL1_FREQ_1333 );
-                rc_ecmd |= pll_data.setByte(      16, MEM_PLL_CNTRL2_FREQ_1333 );
-            }
-            else if (mss_freq == 1600)
-            {
-                rc_ecmd |= pll_data.setDoubleWord( 0, MEM_PLL_CNTRL0_FREQ_1600 );
-                rc_ecmd |= pll_data.setDoubleWord( 1, MEM_PLL_CNTRL1_FREQ_1600 );
-                rc_ecmd |= pll_data.setByte(      16, MEM_PLL_CNTRL2_FREQ_1600 );
-            }
-            else if (mss_freq == 1866)
-            {
-                rc_ecmd |= pll_data.setDoubleWord( 0, MEM_PLL_CNTRL0_FREQ_1866 );
-                rc_ecmd |= pll_data.setDoubleWord( 1, MEM_PLL_CNTRL1_FREQ_1866 );
-                rc_ecmd |= pll_data.setByte(      16, MEM_PLL_CNTRL2_FREQ_1866 );
-            }
-            else if (mss_freq == 2133)
-            {
-FAPI_ERR("PLL settings not specified for this frequency.  Defaulting to 1600MHz..");
-                rc_ecmd |= pll_data.setDoubleWord( 0, MEM_PLL_CNTRL0_FREQ_2133 );
-                rc_ecmd |= pll_data.setDoubleWord( 1, MEM_PLL_CNTRL1_FREQ_2133 );
-                rc_ecmd |= pll_data.setByte(      16, MEM_PLL_CNTRL2_FREQ_2133 );
-            }
-            else
-            {
-                FAPI_ERR("Unexpected frequency value specified using ATTR_MSS_FREQ attribute!");
-                FAPI_ERR("Specified value = %u.  Supported values are 800, 1066, 1333, 1600, 1866, and 2133 MHz", mss_freq);
-                FAPI_SET_HWP_ERROR(rc, RC_MSS_UNSUPPORTED_FREQ_CALCULATED);
-                break;
-            }
-        }
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x loading ecmd data buffer with 136 bits of data for MEM PLL control ring.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-
-
-        //---------------------------------------------------------------------------
-        //  Scan out the original contents from ring and modify it with new settings.
-        //---------------------------------------------------------------------------
-        FAPI_DBG("Loading PLL settings into scan ring tp_pll_bndy for MEM PLL.");
-
-        // We need to load 136 bits of control data into this scan chain:  Name = tp_pll_bndy  Address = {0x00030088}
-        // The scan chain is 442 bits long.  The bits need to go into positions 295 - 430
-        rc_ecmd |= ring_data.setBitLength(RING_LENGTH_TP_PLL_BNDY);   // This length needs to match the length in the scandef file (Required for hostboot.)
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiGetRing(i_target, 0x00030088, ring_data);
-        if (rc)
-        {
-            FAPI_ERR("fapiGetRing failed with rc = 0x%x", (uint32_t)rc);
-            break;
-        }
-        // Reverse the bits in the pll data buffer so they match the order of the bits in the scan chain
-        rc_ecmd |= pll_data.reverse( );
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error (0x%x) reversing the bits in the pll data buffer", rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        // Insert the PLL settings in to the scan ring.
-        rc_ecmd |= ring_data.insert( pll_data, 295, 136);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error (0x%x) inserting config bits into ring_data buffer", rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-
-
         //-------------------------------------------
         //  Set the OPCG to generate the setpulse
         //------------------------------------------
@@ -427,16 +183,16 @@ FAPI_ERR("PLL settings not specified for this frequency.  Defaulting to 1600MHz.
 
 
 
-        //-----------------------------------------------------
-        //  Scan new ring data back into tp_pll_bndy scan ring.
-        //-----------------------------------------------------
-        rc = fapiPutRing(i_target, 0x00030088, ring_data, RING_MODE_SET_PULSE);
+        //------------------------------------------------
+        //  Scan new ring data into tp_pll_bndy scan ring.
+        //------------------------------------------------
+        rc = fapiPutRing(i_target, 0x00030088, i_scan_ring_data, RING_MODE_SET_PULSE);
         if (rc)
         {
             FAPI_ERR("fapiPutRing failed with rc = 0x%x", (uint32_t)rc);
             break;
         }
-        FAPI_DBG("Loading of the config bits for MEM PLL is done.\n");
+        FAPI_DBG("Loading of the scan ring data for ring tp_pll_bndy is done.\n");
 
 
 
@@ -476,6 +232,124 @@ FAPI_ERR("PLL settings not specified for this frequency.  Defaulting to 1600MHz.
         }
 
 
+    } while(0);
+
+    FAPI_INF("Finished executing subroutine: cen_load_pll_ring_from_buffer");
+    return rc;
+}
+
+
+
+
+
+
+//------------------------------------------------------------------------------
+// cen_mem_pll_initf
+//------------------------------------------------------------------------------
+fapi::ReturnCode cen_mem_pll_initf(const fapi::Target & i_target)
+{
+    // Target is centaur
+
+    fapi::ReturnCode    rc;
+    uint32_t            rc_ecmd         = 0;
+    uint8_t             is_simulation   = 0;
+    uint32_t            mss_freq        = 0;
+    uint32_t            ring_length     = 0;
+    uint8_t             attrRingData[80]={0};   // Set to 80 bytes to match length in XML file, not actual scan ring length.
+    ecmdDataBufferBase  ring_data;
+
+
+    FAPI_INF("********* cen_mem_pll_initf start *********");
+    do
+    {
+
+        FAPI_DBG("Setting up the Centaur MEM PLL.");
+
+
+        //------------------------------------------
+        //  Read attributes for setting the PLL data
+        //------------------------------------------
+
+        // The code that loads the PLL scan ring data should choose the correct data to load based on
+        // the DDR frequency and voltage settings and a lab override value.
+        // The supported frequencies are 800, 1066, 1333, 1600, 1866, and 2133 MHz  (These are the DDR frequencies and the PLL output B frequencies.)
+        // The DDR frequency can be determined from attribute ATTR_MSS_FREQ  (in MHz)
+        // The DDR voltage can be determined from attribute ATTR_MSS_VOLT  (in millivolts)
+        // Get another attribute for selecting the "override" ring.    Use CQ to request an attribute.
+        // (The selection of rings should include an "override ring that can be used in the lab")
+
+
+        // Read the attributes
+        rc = FAPI_ATTR_GET( ATTR_IS_SIMULATION, NULL, is_simulation);
+        if (rc)
+        {
+            FAPI_ERR("Failed to get attribute: ATTR_IS_SIMULATION.");
+            break;
+        }
+        rc = FAPI_ATTR_GET( ATTR_MSS_FREQ, &i_target, mss_freq);
+        if (rc)
+        {
+            FAPI_ERR("Failed to get attribute: ATTR_MSS_FREQ.");
+            break;
+        }
+
+        FAPI_DBG("ATTR_IS_SIMULATION attribute is set to : %d.", is_simulation);
+        FAPI_DBG("DDR frequency is set to : %d.", mss_freq);
+
+
+
+
+
+
+// Note to Pete Thomsen .... you need to copy the code below and change the attribute names.....
+
+        // Read the ring length attribute value.
+        rc = FAPI_ATTR_GET( ATTR_MEMB_TP_BNDY_PLL_LENGTH, &i_target, ring_length);
+        if (rc)
+        {
+            FAPI_ERR("Failed to get attribute: ATTR_MEMB_TP_BNDY_PLL_LENGTH.");
+            break;
+        }
+        FAPI_DBG("ATTR_MEMB_TP_BNDY_PLL_LENGTH attribute is set to : %d.", ring_length);
+
+
+        // Read the ring data attribute value.
+        rc = FAPI_ATTR_GET( ATTR_MEMB_TP_BNDY_PLL_DATA, &i_target, attrRingData);
+        if (rc)
+        {
+            FAPI_ERR("Failed to get attribute: ATTR_MEMB_TP_BNDY_PLL_DATA.");
+            break;
+        }
+
+
+        // Set the ring_data buffer to the right length for the ring data
+        rc_ecmd |= ring_data.setBitLength(ring_length);   // This length needs to match the real scan length in the scandef file (Required for hostboot.)
+        if (rc_ecmd)
+        {
+            FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.",  rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+
+        // Put the ring data from the attribute into the buffer
+        rc_ecmd |= ring_data.insert(attrRingData, 0, ring_length, 0);
+        if (rc_ecmd)
+        {
+            FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.",  rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+
+        // Call the subroutine to load the data into the simulation or HW model
+        rc = cen_load_pll_ring_from_buffer ( i_target, ring_data );
+        if (rc)
+        {
+            FAPI_ERR("Subroutine: cen_load_pll_ring_from_buffer failed!");
+            break;
+        }
+
 
 
     } while(0);
@@ -493,6 +367,12 @@ FAPI_ERR("PLL settings not specified for this frequency.  Defaulting to 1600MHz.
 This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 $Log: cen_mem_pll_initf.C,v $
+Revision 1.5  2013/03/04 17:56:24  mfred
+Add some header comments for BACKUP and SCREEN.
+
+Revision 1.4  2013/01/29 21:50:52  mfred
+Use new PLL ring attributes.
+
 Revision 1.3  2012/11/07 23:22:44  mfred
 Updated MEM PLL settings for HW with values from Tim Diemoz.
 
diff --git a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.H b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.H
index 5f47ed950..f69cbdb48 100644
--- a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.H
+++ b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_mem_pll_initf.H,v 1.1 2012/08/13 17:16:13 mfred Exp $
+// $Id: cen_mem_pll_initf.H,v 1.2 2013/01/29 21:50:56 mfred Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_pll_initf.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -55,17 +55,32 @@ extern "C"
 {
     // Target is centaur
 
+
 /**
- * @brief cen_mem_pll_initf procedure.  The purpose of this procedure is to scan the right values in to the Centaur MEM PLL controller..
+ * @brief cen_load_pll_ring_from_attribute procedure.  The purpose of this procedure is to scan the right values in to the Centaur PLL scan chain.
  *
  * @param[in]  i_target  Reference to centaur target
- *
  * @return ReturnCode
  */
+    fapi::ReturnCode cen_load_pll_ring_from_buffer(const fapi::Target& i_target,
+                                                   ecmdDataBufferBase i_scan_ring_data
+                                                   );
+
+    // Target is centaur
+
 
+/**
+ * @brief cen_mem_pll_initf procedure.  The purpose of this procedure is to scan the right values in to the Centaur MEM PLL controller..
+ *
+ * @param[in]  i_target  Reference to centaur target
+ * @return ReturnCode
+ */
     fapi::ReturnCode cen_mem_pll_initf(const fapi::Target& i_target);
     // Target is centaur
 
+
+
+
 } // extern "C"
 
 #endif // CEN_MEM_PLL_INITFHWPB_H_
diff --git a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/memb_pll_ring_attributes.xml b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/memb_pll_ring_attributes.xml
new file mode 100644
index 000000000..eb1d2455b
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/memb_pll_ring_attributes.xml
@@ -0,0 +1,193 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dram_training/mem_pll_setup/memb_pll_ring_attributes.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<attributes>
+  <attribute>
+    <id>ATTR_MEMB_TP_BNDY_PLL_DATA</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Ring image for Centaur tp_bndy_pll ring
+      creator: platform
+      firmware notes:
+    </description>
+    <valueType>uint8</valueType>
+    <array>80</array>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_MEMB_TP_BNDY_PLL_FLUSH</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Ring flush image for Centaur tp_bndy_pll ring
+      creator: platform
+      firmware notes:
+    </description>
+    <valueType>uint8</valueType>
+    <array>80</array>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_MEMB_TP_BNDY_PLL_FOR_DCCAL_DATA</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Ring image for Centaur tp_bndy_pll ring
+      creator: platform
+      firmware notes:
+    </description>
+    <valueType>uint8</valueType>
+    <array>80</array>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_MEMB_TP_BNDY_PLL_LENGTH</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Length of data in ring image for Centaur tp_bndy_pll ring
+      creator: platform
+      firmware notes:
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_MEMB_TP_BNDY_PLL_SCAN_SELECT</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Scan select for ring image for Centaur tp_bndy_pll ring
+      creator: platform
+      firmware notes:
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4000 mem=1066
+      creator: platform
+      firmware notes:
+    </description>
+    <valueType>uint8</valueType>
+    <array>80</array>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4000 mem=1333
+      creator: platform
+      firmware notes:
+    </description>
+    <valueType>uint8</valueType>
+    <array>80</array>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4000 mem=1600
+      creator: platform
+      firmware notes:
+    </description>
+    <valueType>uint8</valueType>
+    <array>80</array>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4000 mem=1866
+      creator: platform
+      firmware notes:
+    </description>
+    <valueType>uint8</valueType>
+    <array>80</array>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4800 mem=1066
+      creator: platform
+      firmware notes:
+    </description>
+    <valueType>uint8</valueType>
+    <array>80</array>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4800 mem=1333
+      creator: platform
+      firmware notes:
+    </description>
+    <valueType>uint8</valueType>
+    <array>80</array>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4800 mem=1600
+      creator: platform
+      firmware notes:
+    </description>
+    <valueType>uint8</valueType>
+    <array>80</array>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4800 mem=1866
+      creator: platform
+      firmware notes:
+    </description>
+    <valueType>uint8</valueType>
+    <array>80</array>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+
+</attributes>
+
diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile
index 714143032..cd8f4ffae 100644
--- a/src/usr/hwpf/makefile
+++ b/src/usr/hwpf/makefile
@@ -111,7 +111,8 @@ HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \
                      hwp/poreve_memory_attributes.xml \
                      hwp/mcbist_attributes.xml \
                      hwp/proc_winkle_scan_override_attributes.xml \
-                     hwp/erepair_thresholds.xml
+                     hwp/erepair_thresholds.xml \
+                     hwp/dram_training/mem_pll_setup/memb_pll_ring_attributes.xml
 
 #------------------------------------------------------------------------------
 # Initfiles
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 02e6e4ce2..25a6207e4 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -10793,4 +10793,280 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
 </attribute>
 <!-- ===== End Attributes supporting erepair_thresholds.xml HWPF Attributes ===== -->
 
+<!-- Mem PLL attributes ===== -->
+<attribute>
+    <id>MEMB_TP_BNDY_PLL_DATA</id>
+    <description>Ring image for Centaur tp_bndy_pll ring
+      creator: platform
+      firmware notes:
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>
+                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                 0x00, 0x00, 0xFD, 0x10, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
+                 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, 0x70, 0x00,
+                 0x00, 0x52, 0xC0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                 0x00, 0x00, 0x80, 0x00, 0x00, 0x19, 0x04, 0x03, 0x00, 0xA0,
+                 0x00, 0x00, 0x02, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+            </default>
+        </uint8_t>
+        <array>80</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MEMB_TP_BNDY_PLL_DATA</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MEMB_TP_BNDY_PLL_FLUSH</id>
+    <description>Ring flush image for Centaur tp_bndy_pll ring
+      creator: platform
+      firmware notes:
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>80</array>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MEMB_TP_BNDY_PLL_FLUSH</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MEMB_TP_BNDY_PLL_FOR_DCCAL_DATA</id>
+    <description>Ring image for Centaur tp_bndy_pll ring
+      creator: platform
+      firmware notes:
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>80</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MEMB_TP_BNDY_PLL_FOR_DCCAL_DATA</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MEMB_TP_BNDY_PLL_LENGTH</id>
+    <description>Length of data in ring image for Centaur tp_bndy_pll ring
+      creator: platform
+      firmware notes:
+    </description>
+    <simpleType>
+      <uint32_t>
+            <default>0x000001ba</default>
+      </uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MEMB_TP_BNDY_PLL_LENGTH</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MEMB_TP_BNDY_PLL_SCAN_SELECT</id>
+    <description>Scan select for ring image for Centaur tp_bndy_pll ring
+      creator: platform
+      firmware notes:
+    </description>
+    <simpleType>
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MEMB_TP_BNDY_PLL_SCAN_SELECT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA</id>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4000 mem=1066
+      creator: platform
+      firmware notes:
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>80</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA</id>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4000 mem=1333
+      creator: platform
+      firmware notes:
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>80</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA</id>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4000 mem=1600
+      creator: platform
+      firmware notes:
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>80</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA</id>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4000 mem=1866
+      creator: platform
+      firmware notes:
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>80</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA</id>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4800 mem=1066
+      creator: platform
+      firmware notes:
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>80</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA</id>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4800 mem=1333
+      creator: platform
+      firmware notes:
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>80</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA</id>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4800 mem=1600
+      creator: platform
+      firmware notes:
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>80</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA</id>
+    <description>Ring image for Centaur tp_bndy_pll ring for nest=4800 mem=1866
+      creator: platform
+      firmware notes:
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>80</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
 </attributes>
diff --git a/src/usr/targeting/common/xmltohb/common.mk b/src/usr/targeting/common/xmltohb/common.mk
index db772c7e6..4ded1af0e 100644
--- a/src/usr/targeting/common/xmltohb/common.mk
+++ b/src/usr/targeting/common/xmltohb/common.mk
@@ -84,7 +84,8 @@ FAPI_ATTR_SOURCES =          \
     poreve_memory_attributes.xml \
     mcbist_attributes.xml \
     proc_winkle_scan_override_attributes.xml \
-    erepair_thresholds.xml
+    erepair_thresholds.xml \
+    dram_training/mem_pll_setup/memb_pll_ring_attributes.xml
 
 XMLTOHB_GENERIC_XML     = generic.xml
 XMLTOHB_FAPI_XML        = fapiattrs.xml
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 9362f5085..fd2c3468b 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -1042,6 +1042,19 @@
     <attribute><id>MSS_NWELL_MISPLACEMENT</id></attribute>
     <attribute><id>EI_BUS_TX_MSBSWAP</id></attribute>
     <attribute><id>MSS_FREQ_OVERRIDE</id></attribute>
+    <attribute><id>MEMB_TP_BNDY_PLL_DATA</id></attribute>
+    <attribute><id>MEMB_TP_BNDY_PLL_FLUSH</id></attribute>
+    <attribute><id>MEMB_TP_BNDY_PLL_FOR_DCCAL_DATA</id></attribute>
+    <attribute><id>MEMB_TP_BNDY_PLL_LENGTH</id></attribute>
+    <attribute><id>MEMB_TP_BNDY_PLL_SCAN_SELECT</id></attribute>
+    <attribute><id>MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA</id></attribute>
+    <attribute><id>MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA</id></attribute>
+    <attribute><id>MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA</id></attribute>
+    <attribute><id>MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA</id></attribute>
+    <attribute><id>MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA</id></attribute>
+    <attribute><id>MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA</id></attribute>
+    <attribute><id>MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA</id></attribute>
+    <attribute><id>MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA</id></attribute>
 </targetType>
 
 <!-- Centaur MBS -->