Add in L1 draminit_training_adv files

Change-Id: I1a79898572e675242f0c572bd708bbc05b63039d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44604
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44609
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>

5 files changed, 265 insertions, 0 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index 745011c1d..8c60d8e35 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -9366,6 +9366,96 @@ fapi_try_exit:
 }
 
 ///
+/// @brief ATTR_MSS_CUSTOM_TRAINING_ADV_PATTERNS getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
+/// @param[out] ref to the value uint32_t
+/// @note Generated by gen_accessors.pl generateParameters (D)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Special training pattern used for draminit_training_advance. Used for read
+/// centering There can be two patterns used here. The first 0-15 bits are for
+/// PATTERN1, bits 16-32 are for PATTERN2. If this attribute is set to 0, using the
+/// default values of: 0x952D for PATTERN1 0x594A for
+/// PATTERN2
+///
+inline fapi2::ReturnCode custom_training_adv_pattern(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+        uint32_t& o_value)
+{
+    uint32_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_CUSTOM_TRAINING_ADV_PATTERNS, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+                            l_value) );
+    o_value = l_value[mss::index(i_target)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_CUSTOM_TRAINING_ADV_PATTERNS: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_CUSTOM_TRAINING_ADV_PATTERNS getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
+/// @param[out] ref to the value uint32_t
+/// @note Generated by gen_accessors.pl generateParameters (D.1)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Special training pattern used for draminit_training_advance. Used for read
+/// centering There can be two patterns used here. The first 0-15 bits are for
+/// PATTERN1, bits 16-32 are for PATTERN2. If this attribute is set to 0, using the
+/// default values of: 0x952D for PATTERN1 0x594A for
+/// PATTERN2
+///
+inline fapi2::ReturnCode custom_training_adv_pattern(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        uint32_t& o_value)
+{
+    uint32_t l_value[2];
+    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_CUSTOM_TRAINING_ADV_PATTERNS, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+                            l_value) );
+    o_value = l_value[mss::index(l_mca)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_CUSTOM_TRAINING_ADV_PATTERNS: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_CUSTOM_TRAINING_ADV_PATTERNS getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[out] uint32_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (E)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Special training pattern used for draminit_training_advance. Used for read
+/// centering There can be two patterns used here. The first 0-15 bits are for
+/// PATTERN1, bits 16-32 are for PATTERN2. If this attribute is set to 0, using the
+/// default values of: 0x952D for PATTERN1 0x594A for
+/// PATTERN2
+///
+inline fapi2::ReturnCode custom_training_adv_pattern(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+        uint32_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint32_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_CUSTOM_TRAINING_ADV_PATTERNS, i_target, l_value) );
+    memcpy(o_array, &l_value, 8);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_CUSTOM_TRAINING_ADV_PATTERNS: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
 /// @brief ATTR_MSS_VREF_CAL_ENABLE getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint16_t
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C
new file mode 100644
index 000000000..98795e185
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C
@@ -0,0 +1,65 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C $ */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2017                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_mss_draminit_training_adv.C
+/// @brief Train dram
+///
+// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: FSP:HB
+
+#include <fapi2.H>
+#include <mss.H>
+#include <vector>
+
+#include <p9_mss_draminit_training.H>
+#include <lib/utils/count_dimm.H>
+#include <lib/shared/mss_const.H>
+#include <lib/workarounds/dp16_workarounds.H>
+#include <lib/workarounds/dqs_align_workarounds.H>
+#include <lib/fir/unmask.H>
+#include <lib/dimm/ddr4/zqcal.H>
+
+using fapi2::TARGET_TYPE_MCBIST;
+using fapi2::TARGET_TYPE_MCA;
+
+extern "C"
+{
+    ///
+    /// @brief Train dram
+    /// @param[in] i_target, the McBIST of the ports of the dram you're training
+    /// @param[in] i_special_training, optional CAL_STEP_ENABLE override. Used in sim, debug
+    /// @param[in] i_abort_on_error, optional CAL_ABORT_ON_ERROR override. Used in sim, debug
+    /// @return FAPI2_RC_SUCCESS iff ok
+    ///
+    fapi2::ReturnCode p9_mss_draminit_training_adv( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target,
+            const uint32_t i_special_training,
+            const uint8_t i_abort_on_error)
+    {
+        return fapi2::FAPI2_RC_SUCCESS;
+    }
+}
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.H
new file mode 100644
index 000000000..634742a8f
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.H
@@ -0,0 +1,62 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.H $ */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2017                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file p9_mss_draminit_trainingi_adv.H
+/// @brief Train DRAM
+///
+// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: FSP:HB
+
+#ifndef __P9_MSS_DRAMINIT_TRAINING_ADV__
+#define __P9_MSS_DRAMINIT_TRAINING_ADV__
+
+#include <fapi2.H>
+
+typedef fapi2::ReturnCode (*p9_mss_draminit_training_adv_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>&,
+        const uint32_t,
+        const uint8_t);
+
+// Use a special sentinal to let you know you need to read the attribute (which is 1/0)
+constexpr uint8_t CAL_ABORT_SENTINAL = 3;
+
+extern "C"
+{
+
+    ///
+    /// @brief Train dram, assumes effective config has run
+    /// @param[in] i_target the McBIST of the ports of the dram you're training
+    /// @param[in] i_special_training optional CAL_STEP_ENABLE override. Used in sim, debug
+    /// @param[in] i_abort_on_error, optional CAL_ABORT_ON_ERROR override. Used in sim, debug
+    /// @return FAPI2_RC_SUCCESS iff ok
+    ///
+    fapi2::ReturnCode p9_mss_draminit_training_adv( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target,
+            const uint32_t i_special_training = 0,
+            const uint8_t i_abort_on_error = CAL_ABORT_SENTINAL);
+}
+
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.mk b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.mk
new file mode 100644
index 000000000..40ae33464
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.mk
@@ -0,0 +1,29 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.mk $
+#
+# OpenPOWER HostBoot Project
+#
+# Contributors Listed Below - COPYRIGHT 2017
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+-include 00common.mk
+
+PROCEDURE=p9_mss_draminit_training_adv
+$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE)))
+$(call BUILD_PROCEDURE)
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
index 95790c137..cb104abf2 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
@@ -1968,6 +1968,25 @@
     </attribute>
 
     <attribute>
+        <id>ATTR_MSS_CUSTOM_TRAINING_ADV_PATTERNS</id>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>
+            Special training pattern used for draminit_training_advance. Used for read centering
+            There can be two patterns used here.
+            The first 0-15 bits are for PATTERN1,
+            bits 16-32 are for PATTERN2.
+            If this attribute is set to 0, using the default values of:
+            0x952D for PATTERN1
+            0x594A for PATTERN2
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint32</valueType>
+        <writeable/>
+        <array>2</array>
+        <mssAccessorName>custom_training_adv_pattern</mssAccessorName>
+    </attribute>
+
+    <attribute>
         <id>ATTR_MSS_VREF_CAL_ENABLE</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>