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authorStephen Glancy <sglancy@us.ibm.com>2017-05-05 16:13:42 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-05-22 23:41:49 -0400
commit1844c9f7ade671bb49800600e11eff5da1b03cba (patch)
tree3d94e704900d51e1433efe3076f3f03790755e9e /src
parentdf39972b03daae39beaf59c80fedde34cc001066 (diff)
downloadtalos-hostboot-1844c9f7ade671bb49800600e11eff5da1b03cba.tar.gz
talos-hostboot-1844c9f7ade671bb49800600e11eff5da1b03cba.zip
Adds DCD calibration control attributes
Change-Id: I2c3783eba2e5638e20136494ad897b420737566e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40178 Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40180 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H46
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C7
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C7
-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml17
-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/memory_workarounds_attributes.xml13
-rw-r--r--src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml5
-rw-r--r--src/usr/targeting/common/xmltohb/attribute_types.xml17
-rwxr-xr-xsrc/usr/targeting/common/xmltohb/target_types.xml1
8 files changed, 113 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H
index abdceefb2..64a1f693c 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H
@@ -360,6 +360,52 @@ fapi_try_exit:
}
///
+/// @brief ATTR_CHIP_EC_FEATURE_DCD_WORKAROUND getter
+/// @tparam T the fapi2 target type of the target
+/// @param[in] const ref to the target
+/// @return bool true iff feature is enabled
+///
+template< fapi2::TargetType T >
+inline bool chip_ec_feature_dcd_workaround(const fapi2::Target<T>& i_target)
+{
+ const auto l_chip = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(i_target);
+ uint8_t l_value = 0;
+
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_DCD_WORKAROUND, l_chip, l_value) );
+
+ return l_value != 0;
+
+fapi_try_exit:
+ FAPI_ERR("failed accessing ATTR_CHIP_EC_FEATURE_DCD_WORKAROUND: 0x%lx (target: %s)",
+ uint64_t(fapi2::current_err), mss::c_str(i_target));
+ fapi2::Assert(false);
+ return false;
+}
+
+///
+/// @brief ATTR_MSS_RUN_DCD_CALIBRATION getter
+/// @tparam T the fapi2 target type of the target
+/// @param[in] const ref to the target
+/// @return bool true iff feature is enabled
+///
+template< fapi2::TargetType T >
+inline bool run_dcd_calibration(const fapi2::Target<T>& i_target)
+{
+ const auto l_chip = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(i_target);
+ uint8_t l_value = 0;
+
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_RUN_DCD_CALIBRATION, l_chip, l_value) );
+
+ return l_value != 0;
+
+fapi_try_exit:
+ FAPI_ERR("failed accessing ATTR_MSS_RUN_DCD_CALIBRATION: 0x%lx (target: %s)",
+ uint64_t(fapi2::current_err), mss::c_str(i_target));
+ fapi2::Assert(false);
+ return false;
+}
+
+///
/// @brief ATTR_SKIP_RD_VREF_VREFSENSE_OVERRIDE getter
/// @tparam T the fapi2 target type of the target
/// @param[in] const ref to the target
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C
index 4bf0a1572..c7cc1f525 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C
@@ -103,6 +103,13 @@ fapi2::ReturnCode duty_cycle_distortion_calibration( const fapi2::Target<fapi2::
return FAPI2_RC_SUCCESS;
}
+ // If we're supposed to skip DCD, just return success
+ if (!mss::run_dcd_calibration(i_target))
+ {
+ FAPI_INF("%s Skipping DCD calibration algorithm per ATTR set", mss::c_str(i_target));
+ return FAPI2_RC_SUCCESS;
+ }
+
// Do a quick check to make sure this chip doesn't have the DCD logic built in (e.g., DD1 Nimbus)
// TODO RTC:159687 For DD2 all we need to do is kick off the h/w cal and wait. We can check any ADR_DCD
// register, they all should reflect the inclusion of the DCD logic.
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C
index 4bea16d61..7050e07f4 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C
@@ -370,6 +370,13 @@ fapi2::ReturnCode duty_cycle_distortion_calibration( const fapi2::Target<fapi2::
const auto l_mca = mss::find_targets<TARGET_TYPE_MCA>(i_target);
+ // Skips DCD calibration if we're a DD2 part
+ if (!mss::chip_ec_feature_dcd_workaround(i_target))
+ {
+ FAPI_INF("%s Skipping DCD calibration algorithm due to part revision", mss::c_str(i_target));
+ return FAPI2_RC_SUCCESS;
+ }
+
// Clears the FIRs created by DCD calibration, if needed
FAPI_TRY(mss::workarounds::adr32s::clear_dcd_firs(i_target));
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index 5f76afda0..a6cd0a5cc 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -2895,6 +2895,23 @@
</attribute>
<attribute>
+ <id>ATTR_CHIP_EC_FEATURE_DCD_WORKAROUND</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+ In DD1 Nimbus, the sofware DCD calibration needs to be run, as it does not exist in HW
+ </description>
+ <chipEcFeature>
+ <chip>
+ <name>ENUM_ATTR_NAME_NIMBUS</name>
+ <ec>
+ <value>0x20</value>
+ <test>LESS_THAN</test>
+ </ec>
+ </chip>
+ </chipEcFeature>
+ </attribute>
+
+ <attribute>
<id>ATTR_CHIP_EC_FEATURE_MSS_DQS_POLARITY</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_workarounds_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_workarounds_attributes.xml
index 93f3316ae..db700ec52 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_workarounds_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_workarounds_attributes.xml
@@ -92,4 +92,17 @@
<enum>NO = 0, YES = 1</enum>
<writeable/>
</attribute>
+
+ <attribute>
+ <id>ATTR_MSS_RUN_DCD_CALIBRATION</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+ Selects whether or not DCD should be run
+ </description>
+ <initToZero></initToZero>
+ <valueType>uint8</valueType>
+ <enum>NO = 0, YES = 1</enum>
+ <writeable/>
+ </attribute>
+
</attributes>
diff --git a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
index b67a5ac68..bb5943d40 100644
--- a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
+++ b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
@@ -242,6 +242,11 @@
</attribute>
<attribute>
+ <id>ATTR_MSS_RUN_DCD_CALIBRATION</id>
+ <default>0x00</default>
+ </attribute>
+
+ <attribute>
<id>ATTR_MSS_INTERLEAVE_GRANULARITY</id>
<default>0x00</default>
</attribute>
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index b364f697e..27fc6b616 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -34007,4 +34007,21 @@ Measured in GB</description>
</hwpfToHbAttrMap>
</attribute>
+<attribute>
+ <id>MSS_RUN_DCD_CALIBRATION</id>
+ <description>
+ Selects whether or not DCD should be run
+ </description>
+ <simpleType>
+ <uint8_t></uint8_t>
+ </simpleType>
+ <persistency>volatile-zeroed</persistency>
+ <readable/>
+ <writeable/>
+ <hwpfToHbAttrMap>
+ <id>ATTR_MSS_RUN_DCD_CALIBRATION</id>
+ <macro>DIRECT</macro>
+ </hwpfToHbAttrMap>
+</attribute>
+
</attributes>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index c8ba6b39f..5646a7916 100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -1329,6 +1329,7 @@
<attribute><id>PM_SPWUP_IGNORE_XSTOP_FLAG</id></attribute>
<attribute><id>SECUREBOOT_PROTECT_DECONFIGURED_TPM</id></attribute>
<attribute><id>CME_INSTRUCTION_TRACE_ENABLE</id></attribute>
+ <attribute><id>MSS_RUN_DCD_CALIBRATION</id></attribute>
<!-- START memory workaround for DD1.02 -->
<attribute><id>DO_MSS_WR_VREF</id></attribute>
<attribute><id>DO_MSS_VREF_DAC</id></attribute>
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