diff options
author | Thi Tran <thi@us.ibm.com> | 2011-11-11 11:01:41 -0600 |
---|---|---|
committer | Thi N. Tran <thi@us.ibm.com> | 2011-11-11 12:13:28 -0600 |
commit | 1595ed5f5602346579dba1f8714d3092f50e928f (patch) | |
tree | 2d58a72a8936ff6eb87eab8e3418b76a536f9b32 /src | |
parent | c4c52d57c809bc9b6c8a94a8d9fb66489f246a18 (diff) | |
download | talos-hostboot-1595ed5f5602346579dba1f8714d3092f50e928f.tar.gz talos-hostboot-1595ed5f5602346579dba1f8714d3092f50e928f.zip |
Modifications to run Sprint 6 code on VBU
Change-Id: I28b4c114bdfb00a8f252bc4ce12a725f292c266b
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/495
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/usr/fsi/test/fsiddtest.H | 32 | ||||
-rw-r--r-- | src/usr/hwas/hwas.C | 20 | ||||
-rwxr-xr-x | src/usr/hwpf/hwp/initfiles/sample.initfile | 100 | ||||
-rw-r--r-- | src/usr/hwpf/test/hwpftest.H | 38 | ||||
-rwxr-xr-x | src/usr/i2c/test/i2ctest.H | 15 | ||||
-rw-r--r-- | src/usr/testcore/kernel/vmmbasetest.H | 17 | ||||
-rw-r--r-- | src/usr/xscom/xscom.C | 6 |
7 files changed, 162 insertions, 66 deletions
diff --git a/src/usr/fsi/test/fsiddtest.H b/src/usr/fsi/test/fsiddtest.H index 50750df6f..49b8de5c4 100644 --- a/src/usr/fsi/test/fsiddtest.H +++ b/src/usr/fsi/test/fsiddtest.H @@ -115,6 +115,21 @@ class FsiDDTest : public CxxTest::TestSuite */ void test_readWrite(void) { + //@todo + //@VBU workaround - Disable test case + //Temporarily disable this test case in VBU because of + //an MFSI/CFSI XSCOM hardware bug. + TARGETING::EntityPath syspath(TARGETING::EntityPath::PATH_PHYSICAL); + syspath.addLast(TARGETING::TYPE_SYS,0); + TARGETING::Target* sys = TARGETING::targetService().toTarget(syspath); + uint8_t vpo_mode = 0; + if( sys + && sys->tryGetAttr<TARGETING::ATTR_VPO_MODE>(vpo_mode) + && (vpo_mode == 1) ) + { + return; + } + TRACFCOMP( g_trac_fsi, "FsiDDTest::test_readWrite> Start" ); uint64_t fails = 0; uint64_t total = 0; @@ -389,6 +404,23 @@ class FsiDDTest : public CxxTest::TestSuite */ void test_badTargets(void) { + + //@todo + //@VBU workaround - Disable test case + //Temporarily disable this test case in VBU because of + //an MFSI/CFSI XSCOM hardware bug. + TARGETING::EntityPath syspath(TARGETING::EntityPath::PATH_PHYSICAL); + syspath.addLast(TARGETING::TYPE_SYS,0); + TARGETING::Target* sys = TARGETING::targetService().toTarget(syspath); + uint8_t vpo_mode = 0; + if( sys + && sys->tryGetAttr<TARGETING::ATTR_VPO_MODE>(vpo_mode) + && (vpo_mode == 1) ) + { + return; + } + + TRACFCOMP( g_trac_fsi, "FsiDDTest::test_badTargets> Start" ); uint64_t fails = 0; uint64_t total = 0; diff --git a/src/usr/hwas/hwas.C b/src/usr/hwas/hwas.C index c7872d033..f5948e859 100644 --- a/src/usr/hwas/hwas.C +++ b/src/usr/hwas/hwas.C @@ -39,8 +39,7 @@ #include <trace/interface.H> #include <initservice/taskargs.H> #include <errl/errlentry.H> -#include <targeting/target.H> // targeting - +#include <targeting/targetservice.H> #include <fsi/fsiif.H> #include <hwas/hwas.H> @@ -71,6 +70,23 @@ namespace HWAS TRACDCOMP( g_trac_hwas, "init_fsi entry" ); // printkd("init_fsi\n"); + //@todo + //@VBU workaround - Disable init_fsi + //Temporarily disable the FSI initialization in VBU because of + //an MFSI/CFSI XSCOM hardware bug. + TARGETING::EntityPath syspath(TARGETING::EntityPath::PATH_PHYSICAL); + syspath.addLast(TARGETING::TYPE_SYS,0); + TARGETING::Target* sys = TARGETING::targetService().toTarget(syspath); + uint8_t vpo_mode = 0; + if( sys + && sys->tryGetAttr<TARGETING::ATTR_VPO_MODE>(vpo_mode) + && (vpo_mode == 1) ) + { + TASKARGS_WAIT_AND_ENDTASK(); + TRACFCOMP( g_trac_hwas, "HWBUG Workaround - No FSI initialization"); + return; + } + l_errl = FSI::initializeHardware( ); if ( l_errl ) { diff --git a/src/usr/hwpf/hwp/initfiles/sample.initfile b/src/usr/hwpf/hwp/initfiles/sample.initfile index 17ee552a5..e4a537878 100755 --- a/src/usr/hwpf/hwp/initfiles/sample.initfile +++ b/src/usr/hwpf/hwp/initfiles/sample.initfile @@ -33,7 +33,7 @@ define def_not_equal_test = (ATTR_SCRATCH_UINT64_1 != ATTR_SCRATCH_UINT64_2); #--****************************************************************************** scom 0x0000000013010002 { scom_data ; - 0x0000000000000181 ; + 0xAABBC00000000000 ; } #--****************************************************************************** @@ -42,7 +42,7 @@ scom 0x0000000013010002 { scom 0x0000000013030007 { scom_data, expr ; - 0x0000000000000182, ATTR_SCRATCH_UINT8_1 == ATTR_SCRATCH_UINT8_2 ; + 0x00000CDE00000000, ATTR_SCRATCH_UINT8_1 == ATTR_SCRATCH_UINT8_2 ; } #--****************************************************************************** @@ -75,77 +75,83 @@ scom 0x000000000006800c { #--****************************************************************************** #-- Basic SCOM with bits #--****************************************************************************** +#@todo +#@VBU workaround - Disable sample addresses +#All SCR reg addresses below are only supported from chip release 052 and beyond. +#Release 051, which is used by current VBU model, contain different addresses for +#these registers. +#Disable them for now, needs to re-enable them when VBU upgrade to use chip release 052 -scom 0x0000000013013283 { - bits , scom_data ; - 0:11 , 0b001111001001 ; - 12 , 0b1 ; - 13 , 0b1 ; - 14:59, 0b0000001100000110010000000000010000010010000000 ; -} +#scom 0x0000000013013283 { +# bits , scom_data ; +# 0:11 , 0b001111001001 ; +# 12 , 0b1 ; +# 13 , 0b1 ; +# 14:59, 0b0000001100000110010000000000010000010010000000 ; +#} #--****************************************************************************** #-- Complext SCOM with Bit Support, define, and attributes #--****************************************************************************** -scom 0x0000000013013284 { - bits , scom_data, expr ; - 0:11 , 0b001111001001, any ; - 12 , 0b1, def_equal_test ; - 12 , 0b0, def_not_equal_test ; - 13 , 0b1, ATTR_SCRATCH_UINT8_1 > ATTR_SCRATCH_UINT8_2 ; - 14:59, 0b0000001100000110010000000000010000010010000000, ATTR_SCRATCH_UINT64_1 == ATTR_SCRATCH_UINT64_2 ; -} +#scom 0x0000000013013284 { +# bits , scom_data, expr ; +# 0:11 , 0b001111001001, any ; +# 12 , 0b1, def_equal_test ; +# 12 , 0b0, def_not_equal_test ; +# 13 , 0b1, ATTR_SCRATCH_UINT8_1 > ATTR_SCRATCH_UINT8_2 ; +# 14:59, 0b0000001100000110010000000000010000010010000000, ATTR_SCRATCH_UINT64_1 == ATTR_SCRATCH_UINT64_2 ; +#} #--****************************************************************************** #-- Complex SCOM with Bit Support, and logical operators #--****************************************************************************** -scom 0x0000000013013285 { - bits , scom_data, expr ; - 12 , 0b1, def_equal_test && def_not_equal_test ; - 12 , 0b0, def_equal_test || def_not_equal_test ; - 14 , 0b1, ATTR_SCRATCH_UINT32_1 < ATTR_SCRATCH_UINT32_2 ; - 15 , 0b1, ATTR_SCRATCH_UINT32_1 > ATTR_SCRATCH_UINT32_2 ; - 16 , 0b1, ATTR_SCRATCH_UINT32_1 >= ATTR_SCRATCH_UINT32_2 ; - 17 , 0b1, ATTR_SCRATCH_UINT32_1 <= ATTR_SCRATCH_UINT32_2 ; - 18 , 0b1, ATTR_SCRATCH_UINT32_1 == ATTR_SCRATCH_UINT32_2 ; - 19 , 0b1, ATTR_SCRATCH_UINT32_1 != ATTR_SCRATCH_UINT32_2 ; - 20 , 0b1, (ATTR_SCRATCH_UINT32_1 + ATTR_SCRATCH_UINT32_2) == 4 ; - 21:59, 0b000000110000011001000000000001000001001, ATTR_SCRATCH_UINT8_1 == ATTR_SCRATCH_UINT8_2 ; -} +#scom 0x0000000013013285 { +# bits , scom_data, expr ; +# 12 , 0b1, def_equal_test && def_not_equal_test ; +# 12 , 0b0, def_equal_test || def_not_equal_test ; +# 14 , 0b1, ATTR_SCRATCH_UINT32_1 < ATTR_SCRATCH_UINT32_2 ; +# 15 , 0b1, ATTR_SCRATCH_UINT32_1 > ATTR_SCRATCH_UINT32_2 ; +# 16 , 0b1, ATTR_SCRATCH_UINT32_1 >= ATTR_SCRATCH_UINT32_2 ; +# 17 , 0b1, ATTR_SCRATCH_UINT32_1 <= ATTR_SCRATCH_UINT32_2 ; +# 18 , 0b1, ATTR_SCRATCH_UINT32_1 == ATTR_SCRATCH_UINT32_2 ; +# 19 , 0b1, ATTR_SCRATCH_UINT32_1 != ATTR_SCRATCH_UINT32_2 ; +# 20 , 0b1, (ATTR_SCRATCH_UINT32_1 + ATTR_SCRATCH_UINT32_2) == 4 ; +# 21:59, 0b000000110000011001000000000001000001001, ATTR_SCRATCH_UINT8_1 == ATTR_SCRATCH_UINT8_2 ; +#} #--****************************************************************************** #-- SCOM with 'ec' column - Use scratch for now since all attributes work #--****************************************************************************** -scom 0x0000000013013286 { - scom_data, ATTR_SCRATCH_UINT32_1 ; - 0x0000000000000192, 1 ; -} +#scom 0x0000000013013286 { +# scom_data, ATTR_SCRATCH_UINT32_1 ; +# 0x0000000000000192, 1 ; +#} #--****************************************************************************** #-- Basic SCOM with an array #--****************************************************************************** -scom 0x0000000013013287 { - scom_data, expr ; - 0x0000000000000182, ATTR_SCRATCH_UINT8_ARRAY_1[2] == ATTR_SCRATCH_UINT8_1 ; -} +#scom 0x0000000013013287 { +# scom_data, expr ; +# 0x0000000000000182, ATTR_SCRATCH_UINT8_ARRAY_1[2] == ATTR_SCRATCH_UINT8_1 ; +#} #--****************************************************************************** #-- SCOM with 'ec' & expr column - Use scratch for now since all attributes work #--****************************************************************************** -scom 0x0000000013013288 { - scom_data, ATTR_SCRATCH_UINT32_1 expr; - 0x0000000000000192, 3, ATTR_SCRATCH_UINT8_ARRAY_1[2] == ATTR_SCRATCH_UINT8_1; -} +#scom 0x0000000013013288 { +# scom_data, ATTR_SCRATCH_UINT32_1 expr; +# 0x0000000000000192, 3, ATTR_SCRATCH_UINT8_ARRAY_1[2] == ATTR_SCRATCH_UINT8_1; +#} #--****************************************************************************** #-- Complex SCOM with Bit Support, logical operators and 'ec' column #--****************************************************************************** -scom 0x0000000013013289 { - bits , scom_data ATTR_SCRATCH_UINT32_1 expr; - 23 , 0b1, any, ATTR_SCRATCH_UINT8_ARRAY_1[2] == ATTR_SCRATCH_UINT8_1; - 23 , 0b0, 1, any; -} +#scom 0x0000000013013289 { +# bits , scom_data ATTR_SCRATCH_UINT32_1 expr; +# 23 , 0b1, any, ATTR_SCRATCH_UINT8_ARRAY_1[2] == ATTR_SCRATCH_UINT8_1; +# 23 , 0b0, 1, any; +#} diff --git a/src/usr/hwpf/test/hwpftest.H b/src/usr/hwpf/test/hwpftest.H index ef497c0cc..42fdbccbf 100644 --- a/src/usr/hwpf/test/hwpftest.H +++ b/src/usr/hwpf/test/hwpftest.H @@ -175,21 +175,29 @@ public: {0x000000000006002c, 0, 0x0000000000000183}, {0x000000000006800b, 0, 0}, {0x000000000006800c, 0, 0x8000000000000000 >> 0x17}, - {0x0000000013010002, 0, 0x0000000000000181}, - {0x0000000013013283, 0, 0x3c90000000000000 | - 0x8000000000000000 >> 0x0c | - 0x8000000000000000 >> 0x0d | - 0x0306400412000000 >> 0x0e}, - {0x0000000013013284, 0, 0x3c90000000000000}, - {0x0000000013013285, 0, 0x8000000000000000 >> 0x0f | - 0x8000000000000000 >> 0x10 | - 0x8000000000000000 >> 0x13 | - 0x0306400412000000 >> 0x15 }, - {0x0000000013013286, 0, 0}, - {0x0000000013013287, 0, 0x0000000000000182}, - {0x0000000013013288, 0, 0x0000000000000192}, - {0x0000000013013289, 0, 0x8000000000000000 >> 0x17}, - {0x0000000013030007, 0, 0x0000000000000182} + {0x0000000013010002, 0, 0xAABBC00000000000}, + {0x0000000013030007, 0, 0x00000CDE00000000}, + /* + * @todo + * @VBU workaround + * All SCR reg addresses below are only supported from chip release 052 and beyond. + * Release 051, which is used by current VBU model, contain different addresses for + * these registers. + * Disable them for now, needs to re-enable them when VBU upgrade to use chip release 052 + {0x0000000013013283, 0, 0x3c90000000000000 | + 0x8000000000000000 >> 0x0c | + 0x8000000000000000 >> 0x0d | + 0x0306400412000000 >> 0x0e}, + {0x0000000013013284, 0, 0x3c90000000000000}, + {0x0000000013013285, 0, 0x8000000000000000 >> 0x0f | + 0x8000000000000000 >> 0x10 | + 0x8000000000000000 >> 0x13 | + 0x0306400412000000 >> 0x15 }, + {0x0000000013013286, 0, 0}, + {0x0000000013013287, 0, 0x0000000000000182}, + {0x0000000013013288, 0, 0x0000000000000192}, + {0x0000000013013289, 0, 0x8000000000000000 >> 0x17} + */ }; fapi::ReturnCode l_rc = fapi::FAPI_RC_SUCCESS; diff --git a/src/usr/i2c/test/i2ctest.H b/src/usr/i2c/test/i2ctest.H index bb4453d68..dca02d4e5 100755 --- a/src/usr/i2c/test/i2ctest.H +++ b/src/usr/i2c/test/i2ctest.H @@ -76,6 +76,21 @@ class I2CTest: public CxxTest::TestSuite { errlHndl_t err = NULL; + //@todo + //@VBU workaround - Disable I2C test case on fake target + //Test case use fake targets, which will fail when running + //on VBU. Need to fix this. + TARGETING::EntityPath syspath(TARGETING::EntityPath::PATH_PHYSICAL); + syspath.addLast(TARGETING::TYPE_SYS,0); + TARGETING::Target* sys = TARGETING::targetService().toTarget(syspath); + uint8_t vpo_mode = 0; + if( sys + && sys->tryGetAttr<TARGETING::ATTR_VPO_MODE>(vpo_mode) + && (vpo_mode == 1) ) + { + return; + } + TS_TRACE( "I2C Test 1: its running!" ); do diff --git a/src/usr/testcore/kernel/vmmbasetest.H b/src/usr/testcore/kernel/vmmbasetest.H index 52802fee7..884a91373 100644 --- a/src/usr/testcore/kernel/vmmbasetest.H +++ b/src/usr/testcore/kernel/vmmbasetest.H @@ -33,6 +33,7 @@ #include <arch/ppc.H> #include <sys/mm.h> #include <usr/vmmconst.h> +#include <targeting/targetservice.H> class VmmBaseTest : public CxxTest::TestSuite { @@ -91,7 +92,7 @@ class VmmBaseTest : public CxxTest::TestSuite void testCastOutPages() { - uint64_t l_testAddr = VMM_VADDR_RMVPAGE_TEST; + uint64_t l_testAddr = VMM_VADDR_RMVPAGE_TEST; uint64_t l_testSize = VMM_SIZE_RMVPAGE_TEST; uint64_t vaddr = l_testAddr+l_testSize; uint64_t vsize = PageManager::availPages()*PAGESIZE; @@ -119,7 +120,19 @@ class VmmBaseTest : public CxxTest::TestSuite } (*(volatile uint64_t *)i); sync(); } - nanosleep(1,0); + + // Don't delay in VPO because it will take VERY long to + // run the simulator + TARGETING::EntityPath syspath(TARGETING::EntityPath::PATH_PHYSICAL); + syspath.addLast(TARGETING::TYPE_SYS,0); + TARGETING::Target* sys = TARGETING::targetService().toTarget(syspath); + uint8_t vpo_mode = 0; + if( sys + && sys->tryGetAttr<TARGETING::ATTR_VPO_MODE>(vpo_mode) + && (vpo_mode == 0) ) + { + nanosleep(1,0); + } } private: diff --git a/src/usr/xscom/xscom.C b/src/usr/xscom/xscom.C index 0f84b1da0..adbb87ac7 100644 --- a/src/usr/xscom/xscom.C +++ b/src/usr/xscom/xscom.C @@ -475,6 +475,11 @@ errlHndl_t xscomPerformOp(DeviceFW::OperationType i_opType, // Get the offset uint64_t l_offset = l_mmioAddr.offset(); + TRACDCOMP(g_trac_xscom, "xscomPerformOp: OpType 0x%.16llX, Address 0x%llX, l_virtAddr+l_offset %p", + static_cast<uint64_t>(i_opType), + l_addr, + l_virtAddr + l_offset); + // Keep MMIO access until XSCOM successfully done or error uint64_t l_data = 0; do @@ -485,6 +490,7 @@ errlHndl_t xscomPerformOp(DeviceFW::OperationType i_opType, // The dereferencing should handle Cache inhibited internally // Use local variable and memcpy to avoid unaligned memory access l_data = 0; + if (i_opType == DeviceFW::READ) { l_data = *(l_virtAddr + l_offset); |