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author | Andre Marin <aamarin@us.ibm.com> | 2018-01-27 06:27:56 -0600 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-02-19 09:44:53 -0500 |
commit | f595ecf7f9d00b2f89f72fb462913a151f9383b4 (patch) | |
tree | bd8b0a4dd367cd4b5636ce40a3f6ce7cafd6d18a /src | |
parent | 8d28433bcc3c927ee76cdc4231099660545b1bfa (diff) | |
download | talos-hostboot-f595ecf7f9d00b2f89f72fb462913a151f9383b4.tar.gz talos-hostboot-f595ecf7f9d00b2f89f72fb462913a151f9383b4.zip |
Add address translation (xlate) support for 4Gbx8 and unit tests
Change-Id: I2539fa5237fcae61d334362e54325368c9b12a2a
CQ:SW415468
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52442
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52457
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
7 files changed, 945 insertions, 202 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C index ed291f248..87dd3db08 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -57,6 +57,19 @@ namespace mc /// A little vector of translators. We have one of these for each DIMM we support static const std::vector<xlate_setup> xlate_map = { + // 1R 4Gbx8 DDR4 RDIMM + { + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM15, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_4GB), + xlate_dimm_1R1T4Gbx8 + }, + // 1R 4Gbx4 DDR4 RDIMM { dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, @@ -122,6 +135,19 @@ static const std::vector<xlate_setup> xlate_map = xlate_dimm_1R1T16Gbx4 }, + // 2R 4Gbx8 DDR4 RDIMM + { + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM15, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_8GB), + xlate_dimm_2R2T4Gbx8 + }, + // 2R 4Gbx4 DDR4 RDIMM { dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, @@ -213,6 +239,19 @@ static const std::vector<xlate_setup> xlate_map = xlate_dimm_4R4T8Gbx8 }, + // 4R 4Gbx8 DDR4 RDIMM + { + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM16, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_16GB), + xlate_dimm_4R4T4Gbx8 + }, + // 4R 8Gbx4 DDR4 RDIMM { dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, @@ -258,6 +297,19 @@ static const std::vector<xlate_setup> xlate_map = // 3DS RDIMM // + // 1R 2H 3DS 4Gbx8 DDR4 RDIMM + { + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM15, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_8GB), + xlate_dimm_1R2T4Gbx8 + }, + // 1R 2H 3DS 4Gbx4 DDR4 RDIMM { dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, @@ -323,6 +375,19 @@ static const std::vector<xlate_setup> xlate_map = xlate_dimm_1R2T16Gbx4 }, + // 1R 4H 3DS 4Gbx8 DDR4 RDIMM + { + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM15, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_16GB), + xlate_dimm_1R4T4Gbx8 + }, + // 1R 4H 3DS 4Gbx4 DDR4 RDIMM { dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, @@ -388,6 +453,19 @@ static const std::vector<xlate_setup> xlate_map = xlate_dimm_1R4T16Gbx4 }, + // 1R 8H 3DS 4Gbx8 DDR4 RDIMM + { + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM15, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_32GB), + xlate_dimm_1R8T4Gbx8 + }, + // 1R 8H 3DS 4Gbx4 DDR4 RDIMM { dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, @@ -453,6 +531,18 @@ static const std::vector<xlate_setup> xlate_map = xlate_dimm_1R8T16Gbx4 }, + // 2R 2H 3DS 4Gbx8 DDR4 RDIMM + { + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM15, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_16GB), + xlate_dimm_2R4T4Gbx8 + }, // 2R 2H 3DS 4Gbx4 DDR4 RDIMM { @@ -519,6 +609,18 @@ static const std::vector<xlate_setup> xlate_map = xlate_dimm_2R4T16Gbx4 }, + // 2R 4H 3DS 4Gbx8 DDR4 RDIMM + { + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM15, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_32GB), + xlate_dimm_2R8T4Gbx8 + }, // 2R 4H 3DS 4Gbx4 DDR4 RDIMM { @@ -585,6 +687,18 @@ static const std::vector<xlate_setup> xlate_map = xlate_dimm_2R8T16Gbx4 }, + // 2R 8H 3DS 4Gbx8 DDR4 RDIMM + { + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_16R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM15, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_64GB), + xlate_dimm_2R16T4Gbx8 + }, // 2R 8H 3DS 4Gbx4 DDR4 RDIMM { @@ -1167,8 +1281,8 @@ fapi2::ReturnCode xlate_dimm_2R8T16Gbx4( const dimm::kind& i_kind, constexpr uint64_t R17_MAP(PORT_ADDRESS_2); constexpr uint64_t DBIT_MAP(PORT_ADDRESS_1); - // We're just like a 2R 2H 3DS 8Gbx4 so lets start there and modify - FAPI_TRY( xlate_dimm_2R4T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + // We're just like a 2R 4H 3DS 8Gbx4 so lets start there and modify + FAPI_TRY( xlate_dimm_2R8T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); // We're a 18 row DIMM, so ROW17 is valid. FAPI_TRY( set_xlate_row<ROW17>(R17_MAP, i_offset, io_xlate0) ); @@ -1307,7 +1421,7 @@ fapi2::ReturnCode xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, // this DIMM in the vector, so this is always safe. FAPI_TRY(set_xlate_dimm_slot(i_offset, io_xlate0) ); - // If we have all the slots filled in with 1R SDP DIMM, we build a very differnt mapping. + // If we have all the slots filled in with 1R SDP DIMM, we build a very different mapping. if (l_all_slots_1R) { constexpr uint64_t R15_MAP(PORT_ADDRESS_6); @@ -1410,7 +1524,7 @@ fapi2::ReturnCode xlate_dimm_1R1T8Gbx4( const dimm::kind& i_kind, // We're more or less a 1R 4Gbx4 with an extra row. So lets setup like that and add our row in. FAPI_TRY( xlate_dimm_1R1T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); - // If we have all the slots filled in with 1R SDP DIMM, we build a differnt mapping. + // If we have all the slots filled in with 1R SDP DIMM, we build a different mapping. // We're a 17 row DIMM, so ROW16 is valid. FAPI_TRY( set_xlate_row<ROW16>(R16_MAP, i_offset, io_xlate0) ); @@ -2456,5 +2570,282 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 1R 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R1T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ) +{ + // From the Nimbus MC workbook ver 0.4 + // Chapter 5: Address Translation pg 148 + // We're just like a 1R 4Gbx4 or 1R 8Gbx8 except we don't have R15 + FAPI_TRY( xlate_dimm_1R1T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + FAPI_TRY( clear_xlate_row<ROW15>(i_offset, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 1R 2H 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R2T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ) +{ + // From the Nimbus MC workbook ver 0.4 + // Chapter 5: Address Translation pg 148 + // We're just like a 1R 2H 4Gbx4 or 1R 2H 8Gbx8 except we don't have R15 + // And the D bit is shifted over + FAPI_TRY( xlate_dimm_1R2T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + FAPI_TRY( clear_xlate_row<ROW15>(i_offset, io_xlate0) ); + + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, PORT_ADDRESS_6, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 1R 4H 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R4T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ) +{ + // From the Nimbus MC workbook ver 0.4 + // Chapter 5: Address Translation pg 148 + // We're just like a 1R 4H 4Gbx4 or 1R 4H 8Gbx8 except we don't have R15 + // And the D bit is shifted over + FAPI_TRY( xlate_dimm_1R4T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + FAPI_TRY( clear_xlate_row<ROW15>(i_offset, io_xlate0) ); + + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, PORT_ADDRESS_5, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 1R 4H 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R8T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ) +{ + // From the Nimbus MC workbook ver 0.4 + // Chapter 5: Address Translation pg 148 + // We're just like a 1R 8H 4Gbx4 or 1R 8H 8Gbx8 except we don't have R15 + // And the D bit is shifted over + FAPI_TRY( xlate_dimm_1R8T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + FAPI_TRY( clear_xlate_row<ROW15>(i_offset, io_xlate0) ); + + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, PORT_ADDRESS_4, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 2R 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R2T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ) +{ + // From the Nimbus MC workbook ver 0.4 + // Chapter 5: Address Translation pg 148 + // We're just like a 2R 4Gbx4 or 2R 8Gbx8 except we don't have R15 + // And the D bit is shifted over + FAPI_TRY( xlate_dimm_2R2T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + FAPI_TRY( clear_xlate_row<ROW15>(i_offset, io_xlate0) ); + + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, PORT_ADDRESS_6, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 2R 2H 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R4T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ) +{ + // From the Nimbus MC workbook ver 0.4 + // Chapter 5: Address Translation pg 148 + // We're just like a 2R 2H 4Gbx4 or 2R 2H 8Gbx8 except we don't have R15 + // And the D bit is shifted over + FAPI_TRY( xlate_dimm_2R4T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + FAPI_TRY( clear_xlate_row<ROW15>(i_offset, io_xlate0) ); + + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, PORT_ADDRESS_5, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 2R 4H 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R8T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ) +{ + // From the Nimbus MC workbook ver 0.4 + // Chapter 5: Address Translation pg 148 + // We're just like a 2R 4H 4Gbx4 or 2R 4H 8Gbx8 except we don't have R15 + // And the D bit is shifted over + FAPI_TRY( xlate_dimm_2R8T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + FAPI_TRY( clear_xlate_row<ROW15>(i_offset, io_xlate0) ); + + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, PORT_ADDRESS_4, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 2R 8H 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R16T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ) +{ + // From the Nimbus MC workbook ver 0.4 + // Chapter 5: Address Translation pg 148 + // We're just like a 2R 8H 4Gbx4 or 2R 8H 8Gbx8 except we don't have R15 + // And the D bit is shifted over + FAPI_TRY( xlate_dimm_2R16T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + FAPI_TRY( clear_xlate_row<ROW15>(i_offset, io_xlate0) ); + + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, PORT_ADDRESS_3, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 4R 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_4R4T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ) +{ + // From the Nimbus MC workbook ver 0.4 + // Chapter 5: Address Translation pg 148 + // We're just like a 4R 4Gbx4 or 4R 8Gbx8 except we don't have R15 + // And the D bit is shifted over + FAPI_TRY( xlate_dimm_4R4T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + FAPI_TRY( clear_xlate_row<ROW15>(i_offset, io_xlate0) ); + + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, PORT_ADDRESS_5, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; +} + + } // namespace mc } // namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H index 7b745da9a..9a168c0b5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -113,6 +113,7 @@ class rowTraits<ROW15> public: static constexpr uint64_t ROW = 15; static constexpr uint64_t MAX_MAP_VALUE = PORT_ADDRESS_7; + static constexpr uint64_t CLEAR_MAP = PORT_ADDRESS_0; enum { @@ -132,6 +133,7 @@ class rowTraits<ROW16> public: static constexpr uint64_t ROW = 16; static constexpr uint64_t MAX_MAP_VALUE = PORT_ADDRESS_7; + static constexpr uint64_t CLEAR_MAP = PORT_ADDRESS_0; enum { @@ -151,6 +153,7 @@ class rowTraits<ROW17> public: static constexpr uint64_t ROW = 17; static constexpr uint64_t MAX_MAP_VALUE = PORT_ADDRESS_7; + static constexpr uint64_t CLEAR_MAP = PORT_ADDRESS_0; enum { @@ -197,6 +200,32 @@ fapi_try_exit: } /// +/// @brief CLear row bits on the xlate register +/// @tparam T row enumerations to represent xlate master row bits +/// @tparam TT traits type defaults to rowTraits<T> +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @return FAPI2_RC_SUCCESS iff okay +/// +template< rows T, typename TT = rowTraits<T> > +inline fapi2::ReturnCode clear_xlate_row( const uint64_t i_offset, + fapi2::buffer<uint64_t>& io_xlate0 ) +{ + FAPI_TRY( io_xlate0.clearBit( TT::SLOT0_ROW_VALID + i_offset ) ); + io_xlate0.insertFromRight<TT::ROW_BIT_MAP, TT::ROW_BIT_MAP_LEN>(TT::CLEAR_MAP); + + FAPI_DBG( "Set MCP0XLT0_SLOT%d_ROW%d_VALID at bit %d. " + "Set bits for MCP0XLT0_R%d_BIT_MAP with 0x%lx (start: %d, len: %d). " + "MCP0XLT0: 0x%016lx.", + (i_offset == 0 ? 0 : 1), TT::ROW, TT::SLOT0_ROW_VALID + i_offset, TT::ROW, + TT::CLEAR_MAP, TT::ROW_BIT_MAP, TT::ROW_BIT_MAP_LEN, + uint64_t(io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// /// @class mrankTraits /// @brief a collection of traits associated with the master rank xlate registers /// @tparam T rank enumerations to represent xlate master rank bits @@ -1334,6 +1363,222 @@ fapi2::ReturnCode xlate_dimm_4R4T16Gbx8( const dimm::kind& i_kind, fapi2::buffer<uint64_t>& io_xlate0, fapi2::buffer<uint64_t>& io_xlate1, fapi2::buffer<uint64_t>& io_xlate2 ); + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 1R 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R1T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ); + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 1R 2H 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R2T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ); + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 1R 4H 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R4T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ); + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 1R 4H 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R8T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ); + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 2R 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R2T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ); + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 2R 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R2T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ); + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 2R 2H 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R4T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ); + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 2R 2H 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R4T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ); + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 2R 4H 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R8T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ); + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 2R 4H 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R8T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ); + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 2R 8H 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R16T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ); + +/// +/// @brief Perform initializations of the MC translation +/// @param[in] i_kind the DIMM to map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in] i_largest whether or not we're the largest DIMM on the port. +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify +/// @note Called for 4R 4Gbx8 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_4R4T4Gbx8( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer<uint64_t>& io_xlate0, + fapi2::buffer<uint64_t>& io_xlate1, + fapi2::buffer<uint64_t>& io_xlate2 ); } // ns mc } // ns mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H index cc580d3e7..b5305ac85 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H @@ -21534,6 +21534,28 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Switch that allows unsupported raw card references by providing a default raw +/// card +/// setting. +/// +inline fapi2::ReturnCode mrw_allow_unsupported_rcw(uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), + o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + /// /// @brief ATTR_MSS_VPD_MR_0_VERSION_LAYOUT getter diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C index f57d414c0..b77dc601a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C @@ -27,7 +27,7 @@ /// @brief SPD factory and functions /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: HB:FSP @@ -212,15 +212,15 @@ enum factory_byte_extract }; /// -/// @brief Decodes SPD Revision encoding level -/// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD data -/// @param[out] o_value encoding revision num -/// @return FAPI2_RC_SUCCESS if okay -/// @note Decodes SPD Byte 1 (3~0). -/// @note Item JC-45-2220.01x -/// @note Page 14-15 -/// @note DDR4 SPD Document Release 3 +/// @brief Decodes SPD Revision encoding level +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD data +/// @param[out] o_value encoding revision num +/// @return FAPI2_RC_SUCCESS if okay +/// @note Decodes SPD Byte 1 (3~0). +/// @note Item JC-45-2220.01x +/// @note Page 14-15 +/// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode rev_encoding_level(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data, @@ -254,15 +254,15 @@ fapi_try_exit: } /// -/// @brief Decodes SPD Revision additions level -/// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD data -/// @param[out] o_value additions revision num -/// @return FAPI2_RC_SUCCESS if okay -/// @note Decodes SPD Byte 1 (bits 7~4). -/// @note Item JC-45-2220.01x -/// @note Page 14-15 -/// @note DDR4 SPD Document Release 3 +/// @brief Decodes SPD Revision additions level +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD data +/// @param[out] o_value additions revision num +/// @return FAPI2_RC_SUCCESS if okay +/// @note Decodes SPD Byte 1 (bits 7~4). +/// @note Item JC-45-2220.01x +/// @note Page 14-15 +/// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode rev_additions_level(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data, @@ -297,15 +297,15 @@ fapi_try_exit: } /// -/// @brief Decodes hybrid type (whether or not the DIMM is a hybrid) from SPD -/// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD data +/// @brief Decodes hybrid type (whether or not the DIMM is a hybrid) from SPD +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD data /// @param[out] o_value hybrid -/// @return FAPI2_RC_SUCCESS if okay -/// @note Decodes SPD Byte 3 (bit 7) -/// @note Item JC-45-2220.01x -/// @note Page 17 -/// @note DDR4 SPD Document Release 3 +/// @return FAPI2_RC_SUCCESS if okay +/// @note Decodes SPD Byte 3 (bit 7) +/// @note Item JC-45-2220.01x +/// @note Page 17 +/// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode hybrid(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data, @@ -351,15 +351,15 @@ fapi_try_exit: } /// -/// @brief Decodes hybrid type (hybrid DIMM type) from SPD -/// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD data +/// @brief Decodes hybrid type (hybrid DIMM type) from SPD +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD data /// @param[out] o_value hybrid module type -/// @return FAPI2_RC_SUCCESS if okay -/// @note Decodes SPD Byte 3 (bits 6~4) -/// @note Item JC-45-2220.01x -/// @note Page 17 -/// @note DDR4 SPD Document Release 3 +/// @return FAPI2_RC_SUCCESS if okay +/// @note Decodes SPD Byte 3 (bits 6~4) +/// @note Item JC-45-2220.01x +/// @note Page 17 +/// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode hybrid_type(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data, @@ -405,15 +405,15 @@ fapi_try_exit: } /// -/// @brief Decodes base module type (DIMM type) from SPD -/// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD data +/// @brief Decodes base module type (DIMM type) from SPD +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD data /// @param[out] o_value base module type -/// @return FAPI2_RC_SUCCESS if okay -/// @note Decodes SPD Byte 3 (bits 3~0) -/// @note Item JC-45-2220.01x -/// @note Page 17 -/// @note DDR4 SPD Document Release 3 +/// @return FAPI2_RC_SUCCESS if okay +/// @note Decodes SPD Byte 3 (bits 3~0) +/// @note Item JC-45-2220.01x +/// @note Page 17 +/// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode base_module_type(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data, @@ -460,15 +460,15 @@ fapi_try_exit: } /// -/// @brief Decodes DRAM Device Type -/// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD data -/// @param[out] o_value dram device type enumeration -/// @return FAPI2_RC_SUCCESS if okay -/// @note Decodes SPD Byte 2 -/// @note Item JC-45-2220.01x -/// @note Page 16 -/// @note DDR4 SPD Document Release 3 +/// @brief Decodes DRAM Device Type +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD data +/// @param[out] o_value dram device type enumeration +/// @return FAPI2_RC_SUCCESS if okay +/// @note Decodes SPD Byte 2 +/// @note Item JC-45-2220.01x +/// @note Page 16 +/// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode dram_device_type(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data, @@ -726,15 +726,15 @@ fapi_try_exit: } /// -/// @brief Helper function to return RDIMM decoder -/// @param[in] i_target dimm target -/// @param[in] i_encoding_rev encoding revision -/// @param[in] i_additions_rev additions revision -/// @param[in] i_raw_card raw card reference revision -/// @param[in] i_spd_data SPD data -/// @param[out] o_fact_obj shared pointer to the factory object -/// @return FAPI2_RC_SUCCESS if okay -/// @note Factory dependent on SPD revision & dimm type +/// @brief Helper function to return RDIMM decoder +/// @param[in] i_target dimm target +/// @param[in] i_encoding_rev encoding revision +/// @param[in] i_additions_rev additions revision +/// @param[in] i_raw_card raw card reference revision +/// @param[in] i_spd_data SPD data +/// @param[out] o_fact_obj shared pointer to the factory object +/// @return FAPI2_RC_SUCCESS if okay +/// @note Factory dependent on SPD revision & dimm type /// static fapi2::ReturnCode rdimm_rev_helper(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const uint8_t i_encoding_rev, @@ -814,15 +814,15 @@ fapi_try_exit: } /// -/// @brief Helper function to return LRDIMM decoder -/// @param[in] i_target dimm target -/// @param[in] i_encoding_rev encoding revision -/// @param[in] i_additions_rev additions revision -/// @param[in] i_raw_card raw card reference revision -/// @param[in] i_spd_data SPD data -/// @param[out] o_fact_obj shared pointer to the factory object -/// @return FAPI2_RC_SUCCESS if okay -/// @note Factory dependent on SPD revision & dimm type +/// @brief Helper function to return LRDIMM decoder +/// @param[in] i_target dimm target +/// @param[in] i_encoding_rev encoding revision +/// @param[in] i_additions_rev additions revision +/// @param[in] i_raw_card raw card reference revision +/// @param[in] i_spd_data SPD data +/// @param[out] o_fact_obj shared pointer to the factory object +/// @return FAPI2_RC_SUCCESS if okay +/// @note Factory dependent on SPD revision & dimm type /// static fapi2::ReturnCode lrdimm_rev_helper(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const uint8_t i_encoding_rev, @@ -951,17 +951,19 @@ fapi2::ReturnCode raw_card_factory(const fapi2::Target<TARGET_TYPE_DIMM>& i_targ l_ref_raw_card_rev); } - o_raw_card = find_raw_card( i_target, - fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, - l_ref_raw_card_rev, - mss::rdimm::RAW_CARDS); + FAPI_TRY( find_raw_card( i_target, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + l_ref_raw_card_rev, + mss::rdimm::RAW_CARDS, + o_raw_card) ); break; case fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM: - o_raw_card = find_raw_card( i_target, - fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM, - l_ref_raw_card_rev, - mss::lrdimm::RAW_CARDS); + FAPI_TRY( find_raw_card( i_target, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM, + l_ref_raw_card_rev, + mss::lrdimm::RAW_CARDS, + o_raw_card) ); break; default: @@ -979,12 +981,12 @@ fapi_try_exit: } /// -/// @brief Object factory to select correct decoder -/// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD data -/// @param[out] o_fact_obj shared pointer to the factory object -/// @return FAPI2_RC_SUCCESS if okay -/// @note Factory dependent on SPD revision & dimm type +/// @brief Object factory to select correct decoder +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD data +/// @param[out] o_fact_obj shared pointer to the factory object +/// @return FAPI2_RC_SUCCESS if okay +/// @note Factory dependent on SPD revision & dimm type /// fapi2::ReturnCode factory(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data, @@ -1073,50 +1075,94 @@ fapi_try_exit: } /// -/// @brief Wrapper function for finding the raw card -/// @param[in] i_target the dimm target -/// @param[in] i_dimm_type -/// @param[in] i_ref_raw_card_rev for FFDC -/// @param[in] i_map raw card map -/// @return rcw_settings vector of rcw settings -/// @note This specialization is suited for creating a cache with custom -/// SPD data (e.g. testing custom SPD). +/// @brief Wrapper function for finding the raw card -- helper for testing +/// @param[in] i_target the dimm target +/// @param[in] i_dimm_type +/// @param[in] i_ref_raw_card_rev for FFDC +/// @param[in] i_mrw_supported_rc +/// @param[in] i_map raw card map +/// @param[out] o_rcw raw card setting +/// @return rcw_settings vector of rcw settings +/// @note This specialization is suited for creating a cache with custom +/// SPD data (e.g. testing custom SPD). +/// @note MRW attributes are read-only, this function provides a mechanism to test +/// different code paths. /// -rcw_settings find_raw_card( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - const uint64_t i_dimm_type, - const uint8_t i_ref_raw_card_rev, - const std::vector<std::pair<uint8_t, rcw_settings> > i_map) +fapi2::ReturnCode find_raw_card_helper( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, + const uint64_t i_dimm_type, + const uint8_t i_ref_raw_card_rev, + const uint8_t i_mrw_supported_rc, + const std::vector<std::pair<uint8_t, rcw_settings> >& i_map, + rcw_settings& o_raw_card) { - rcw_settings l_raw_card; + fapi2::ReturnCode l_rc(fapi2::FAPI2_RC_SUCCESS); + + FAPI_INF("Unsupported raw cards %s allowed for %s", + i_mrw_supported_rc ? "are" : "are NOT", + mss::c_str(i_target)); + + FAPI_ASSERT(find_value_from_key( i_map, i_ref_raw_card_rev, o_raw_card), + fapi2::MSS_INVALID_RAW_CARD(fapi2::FAPI2_ERRL_SEV_RECOVERED, l_rc) + .set_DIMM_TYPE(i_dimm_type) + .set_RAW_CARD_REV(i_ref_raw_card_rev) + .set_DIMM_TARGET(i_target), + "Invalid reference raw card received for %s: %d for %s", + (i_dimm_type == fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) ? "RDIMM" : "LRDIMM", + i_ref_raw_card_rev, + mss::c_str(i_target) ); - FAPI_ASSERT( find_value_from_key( i_map, i_ref_raw_card_rev, l_raw_card), - fapi2::MSS_INVALID_RAW_CARD() - .set_DIMM_TYPE(i_dimm_type) - .set_RAW_CARD_REV(i_ref_raw_card_rev) - .set_DIMM_TARGET(i_target), - "Invalid reference raw card received for %s: %d for %s", - (i_dimm_type == fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) ? "RDIMM" : "LRDIMM", - i_ref_raw_card_rev, - mss::c_str(i_target) ); + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: - return l_raw_card; + // If system owners or open power partners decide they want to allow unsupported RCWs, + // we'll create a hidden log for debugging purposes and continue on w/default settings. + // We want the log for debugging purposes because these settings can break + if( i_mrw_supported_rc == fapi2::ENUM_ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW_ENABLE ) + { + fapi2::logError(l_rc, fapi2::FAPI2_ERRL_SEV_RECOVERED); + l_rc = fapi2::FAPI2_RC_SUCCESS; + o_raw_card = (i_dimm_type == fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) ? rdimm_rc_default : lrdimm_rc_default; + } + + return l_rc; +} + +/// +/// @brief Wrapper function for finding the raw card +/// @param[in] i_target the dimm target +/// @param[in] i_dimm_type +/// @param[in] i_ref_raw_card_rev for FFDC +/// @param[in] i_map raw card map +/// @param[out] o_rcw raw card setting +/// @return rcw_settings vector of rcw settings +/// @note This specialization is suited for creating a cache with custom +/// SPD data (e.g. testing custom SPD). +/// +fapi2::ReturnCode find_raw_card( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, + const uint64_t i_dimm_type, + const uint8_t i_ref_raw_card_rev, + const std::vector<std::pair<uint8_t, rcw_settings> >& i_map, + rcw_settings& o_raw_card) +{ + uint8_t l_allow_unsupported_rcw = 0; + FAPI_TRY( mrw_allow_unsupported_rcw(l_allow_unsupported_rcw) ); + + FAPI_TRY( find_raw_card_helper(i_target, i_dimm_type, i_ref_raw_card_rev, l_allow_unsupported_rcw, i_map, o_raw_card), + "Failed find_raw_card_helper for %s", mss::c_str(i_target) ); -// If we got here there was a raw card we don't have values for, so putting the default fapi_try_exit: - fapi2::logError(fapi2::current_err, fapi2::FAPI2_ERRL_SEV_RECOVERED); - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; - return (i_dimm_type == fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) ? - rdimm_rc_default : lrdimm_rc_default; + return fapi2::current_err; } /// -/// @brief Creates factory object & SPD data caches -/// @param[in] i_target the dimm target -/// @param[out] o_factory_caches vector of factory objects -/// @param[in] i_pDecoder custom decoder to populate cache (nullptr default) -/// @return FAPI2_RC_SUCCESS if okay -/// @note This specialization is suited for creating a cache with custom -/// SPD data (e.g. testing custom SPD). +/// @brief Creates factory object & SPD data caches +/// @param[in] i_target the dimm target +/// @param[out] o_factory_caches vector of factory objects +/// @param[in] i_pDecoder custom decoder to populate cache (nullptr default) +/// @return FAPI2_RC_SUCCESS if okay +/// @note This specialization is suited for creating a cache with custom +/// SPD data (e.g. testing custom SPD). /// template<> fapi2::ReturnCode populate_decoder_caches( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.H b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.H index 88dbd1f03..ab9872ca6 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.H @@ -54,106 +54,129 @@ namespace spd { /// -/// @brief Decodes SPD Revision encoding level -/// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD data -/// @param[out] o_value encoding revision num -/// @return FAPI2_RC_SUCCESS if okay -/// @note Decodes SPD Byte 1 (3~0). -/// @note Item JC-45-2220.01x -/// @note Page 14-15 -/// @note DDR4 SPD Document Release 3 +/// @brief Decodes SPD Revision encoding level +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD data +/// @param[out] o_value encoding revision num +/// @return FAPI2_RC_SUCCESS if okay +/// @note Decodes SPD Byte 1 (3~0). +/// @note Item JC-45-2220.01x +/// @note Page 14-15 +/// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode rev_encoding_level(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data, uint8_t& o_value); /// -/// @brief Decodes SPD Revision additions level -/// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob -/// @param[out] o_value additions revision num -/// @return FAPI2_RC_SUCCESS if okay -/// @note Decodes SPD Byte 1 (bits 7~4). -/// @note Item JC-45-2220.01x -/// @note Page 14-15 -/// @note DDR4 SPD Document Release 3 +/// @brief Decodes SPD Revision additions level +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD blob +/// @param[out] o_value additions revision num +/// @return FAPI2_RC_SUCCESS if okay +/// @note Decodes SPD Byte 1 (bits 7~4). +/// @note Item JC-45-2220.01x +/// @note Page 14-15 +/// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode rev_additions_level(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data, uint8_t& o_value); /// -/// @brief Decodes hybrid type (whether or not the DIMM is a hybrid) from SPD -/// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD data +/// @brief Decodes hybrid type (whether or not the DIMM is a hybrid) from SPD +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD data /// @param[out] o_value hybrid -/// @return FAPI2_RC_SUCCESS if okay -/// @note Decodes SPD Byte 3 (bit 7) -/// @note Item JC-45-2220.01x -/// @note Page 17 -/// @note DDR4 SPD Document Release 3 +/// @return FAPI2_RC_SUCCESS if okay +/// @note Decodes SPD Byte 3 (bit 7) +/// @note Item JC-45-2220.01x +/// @note Page 17 +/// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode hybrid(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data, uint8_t& o_value); /// -/// @brief Decodes hybrid type (hybrid DIMM type) from SPD -/// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD data +/// @brief Decodes hybrid type (hybrid DIMM type) from SPD +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD data /// @param[out] o_value hybrid module type -/// @return FAPI2_RC_SUCCESS if okay -/// @note Decodes SPD Byte 3 (bits 6~4) -/// @note Item JC-45-2220.01x -/// @note Page 17 -/// @note DDR4 SPD Document Release 3 +/// @return FAPI2_RC_SUCCESS if okay +/// @note Decodes SPD Byte 3 (bits 6~4) +/// @note Item JC-45-2220.01x +/// @note Page 17 +/// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode hybrid_type(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data, uint8_t& o_value); /// -/// @brief Decodes base module type (DIMM type) from SPD -/// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD data +/// @brief Decodes base module type (DIMM type) from SPD +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD data /// @param[out] o_value base module type -/// @return FAPI2_RC_SUCCESS if okay -/// @note Decodes SPD Byte 3 (bits 3~0) -/// @note Item JC-45-2220.01x -/// @note Page 17 -/// @note DDR4 SPD Document Release 3 +/// @return FAPI2_RC_SUCCESS if okay +/// @note Decodes SPD Byte 3 (bits 3~0) +/// @note Item JC-45-2220.01x +/// @note Page 17 +/// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode base_module_type(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data, uint8_t& o_value); /// -/// @brief Decodes DRAM Device Type -/// @param[in] i_target dimm target -/// @param[out] o_value dram device type enumeration -/// @return FAPI2_RC_SUCCESS if okay -/// @note Decodes SPD Byte 2 -/// @note Item JC-45-2220.01x -/// @note Page 16 -/// @note DDR4 SPD Document Release 3 +/// @brief Decodes DRAM Device Type +/// @param[in] i_target dimm target +/// @param[out] o_value dram device type enumeration +/// @return FAPI2_RC_SUCCESS if okay +/// @note Decodes SPD Byte 2 +/// @note Item JC-45-2220.01x +/// @note Page 16 +/// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode dram_device_type(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data, uint8_t& o_value); /// -/// @brief Wrapper function for finding the raw card -/// @param[in] i_target the dimm target -/// @param[in] i_dimm_type -/// @param[in] i_ref_raw_card_rev for FFDC -/// @param[in] i_map raw card map -/// @return rcw_settings vector of rcw settings -/// @note This specialization is suited for creating a cache with custom -/// SPD data (e.g. testing custom SPD). -/// -rcw_settings find_raw_card( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint64_t i_dimm_type, - const uint8_t i_ref_raw_card_rev, - const std::vector<std::pair<uint8_t, rcw_settings> > i_map); +/// @brief Wrapper function for finding the raw card -- helper for testing +/// @param[in] i_target the dimm target +/// @param[in] i_dimm_type +/// @param[in] i_ref_raw_card_rev for FFDC +/// @param[in] i_mrw_supported_rc +/// @param[in] i_map raw card map +/// @param[out] o_rcw raw card setting +/// @return rcw_settings vector of rcw settings +/// @note This specialization is suited for creating a cache with custom +/// SPD data (e.g. testing custom SPD). +/// @note MRW attributes are read-only, this function provides a mechanism to test +/// different code paths. +/// +fapi2::ReturnCode find_raw_card_helper( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_dimm_type, + const uint8_t i_ref_raw_card_rev, + const uint8_t i_mrw_supported_rc, + const std::vector<std::pair<uint8_t, rcw_settings> >& i_map, + rcw_settings& o_raw_card); + +/// +/// @brief Wrapper function for finding the raw card +/// @param[in] i_target the dimm target +/// @param[in] i_dimm_type +/// @param[in] i_ref_raw_card_rev for FFDC +/// @param[in] i_map raw card map +/// @param[out] o_rcw raw card setting +/// @return rcw_settings vector of rcw settings +/// @note This specialization is suited for creating a cache with custom +/// SPD data (e.g. testing custom SPD). +/// +fapi2::ReturnCode find_raw_card( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_dimm_type, + const uint8_t i_ref_raw_card_rev, + const std::vector<std::pair<uint8_t, rcw_settings> >& i_map, + rcw_settings& o_raw_card); /// /// @brief Decodes reference raw card @@ -183,12 +206,12 @@ fapi2::ReturnCode raw_card_factory(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& rcw_settings& o_raw_card); /// -/// @brief Object factory to select correct decoder -/// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD data -/// @param[out] o_fact_obj shared pointer to the factory object -/// @return FAPI2_RC_SUCCESS if okay -/// @note Factory dependent on SPD revision & dimm type +/// @brief Object factory to select correct decoder +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD data +/// @param[out] o_fact_obj shared pointer to the factory object +/// @return FAPI2_RC_SUCCESS if okay +/// @note Factory dependent on SPD revision & dimm type /// fapi2::ReturnCode factory(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data, @@ -207,12 +230,12 @@ fapi2::ReturnCode master_ranks_per_dimm_setter(const fapi2::Target<fapi2::TARGET const std::shared_ptr<decoder>& i_pDecoder); /// -/// @brief Creates factory object & SPD data caches -/// @tparam T fapi2::TargetType, MCA, MCS, MCBIST, PROC_CHIP are possible TargetTypes -/// @param[in] i_target the fapi2 target to find DIMMs on -/// @param[out] o_factory_caches vector of factory objects -/// @param[in] i_pDecoder optional input decoder to insert custom decoder (nullptr default) -/// @return FAPI2_RC_SUCCESS if okay +/// @brief Creates factory object & SPD data caches +/// @tparam T fapi2::TargetType, MCA, MCS, MCBIST, PROC_CHIP are possible TargetTypes +/// @param[in] i_target the fapi2 target to find DIMMs on +/// @param[out] o_factory_caches vector of factory objects +/// @param[in] i_pDecoder optional input decoder to insert custom decoder (nullptr default) +/// @return FAPI2_RC_SUCCESS if okay /// template<fapi2::TargetType T> fapi2::ReturnCode populate_decoder_caches(const fapi2::Target<T>& i_target, diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml index 6b4ff1a28..9b707c20c 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml @@ -648,4 +648,20 @@ <enum> NO_NVDIMM = 0, NVDIMM_CAPABLE = 1 </enum> <mssAccessorName>mrw_nvdimm_plug_rules</mssAccessorName> </attribute> + + <attribute> + <id>ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Switch that allows unsupported raw card references by providing a + default raw card setting. + </description> + <valueType>uint8</valueType> + <platInit/> + <default> 1 </default> + <overrideOnly/> + <enum> DISABLE = 0, ENABLE = 1 </enum> + <mssAccessorName>mrw_allow_unsupported_rcw</mssAccessorName> + </attribute> + </attributes> diff --git a/src/import/generic/memory/lib/utils/find.H b/src/import/generic/memory/lib/utils/find.H index 6593c6132..3ba3b757e 100644 --- a/src/import/generic/memory/lib/utils/find.H +++ b/src/import/generic/memory/lib/utils/find.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -499,7 +499,7 @@ bool find_value_from_key(const std::vector<std::pair<T, OT> >& i_vector_of_pairs // Did you find it? Let me know. if( (l_value_iterator == i_vector_of_pairs.end()) || (i_key != l_value_iterator->first) ) { - FAPI_ERR("Did not find a mapping value to key: %d", i_key); + FAPI_INF("Did not find a mapping value to key: %d", i_key); return false; } |