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| author | Joe McGill <jmcgill@us.ibm.com> | 2016-04-12 22:06:53 -0500 |
|---|---|---|
| committer | Stephen Cprek <smcprek@us.ibm.com> | 2016-04-21 13:51:52 -0500 |
| commit | b1b08d6cefad72365688023e398d6db3fca683ff (patch) | |
| tree | 0a5e8b82b9a09b91bbd34e4e1571b1a892a73068 /src | |
| parent | a7101d5e42b267bf9399536dc09ee27ae2240882 (diff) | |
| download | talos-hostboot-b1b08d6cefad72365688023e398d6db3fca683ff.tar.gz talos-hostboot-b1b08d6cefad72365688023e398d6db3fca683ff.zip | |
L2 p9_pcie_scominit -- correct CPLT_CONF1 WOR_CLEAR usage
Change-Id: Iafb47ed1da2b64226b48ffbca49b65a2451508db
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23188
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23189
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C index ffff2b652..1cae63333 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C @@ -156,8 +156,8 @@ fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CTRL0_OR, l_buf)); // Phase1 init step 4 (PMA reset) - l_buf = ~0; - FAPI_TRY(l_buf.insertFromRight(0, PEC_IOP_PMA_RESET_START_BIT, 1)); + l_buf = 0; + FAPI_TRY(l_buf.insertFromRight(1, PEC_IOP_PMA_RESET_START_BIT, 1)); FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf()); FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CONF1_CLEAR, l_buf)); @@ -283,8 +283,8 @@ fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C PEC_PCS_RX_SIGDET_CONTROL_REG, 48, 16); // Phase1 init step 25 - l_buf = ~0; - FAPI_TRY(l_buf.insertFromRight(0, PEC_IOP_PIPE_RESET_START_BIT, 1)); + l_buf = 0; + FAPI_TRY(l_buf.insertFromRight(1, PEC_IOP_PIPE_RESET_START_BIT, 1)); FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf()); FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CONF1_CLEAR, l_buf)); |
