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author | Brian Silver <bsilver@us.ibm.com> | 2016-06-10 11:11:09 -0500 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-06-14 17:48:10 -0400 |
commit | e86e4e16585343c8e1669038b3c3c88d00799c88 (patch) | |
tree | f88290c361ca6a1af9d6e6ed92f67edb4bc98986 /src | |
parent | bed9ebebc62c28ea7116875b5a358a09d88f4eba (diff) | |
download | talos-hostboot-e86e4e16585343c8e1669038b3c3c88d00799c88.tar.gz talos-hostboot-e86e4e16585343c8e1669038b3c3c88d00799c88.zip |
Change mss lib so testing works with ATTR_IS_SIMULATION false
Add eff_config to p9_mss_ut.C so it's run for all tests
Fix the freq sync unit test to not trash mss_freq
Fix the attribute file to be in line with the base attibutes
Fix p9_msS_freq.H include guard
Fix DRAM_BL to be a 2D array in mss attribute file
Change-Id: Id18ab3eb4b60f72af64c647f5ff7afe68b7e5097
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25651
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25653
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
6 files changed, 56 insertions, 28 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C index f9ef60180..b7f95413b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C @@ -63,13 +63,8 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC FAPI_TRY( mss::eff_memcal_interval(i_target, l_memcal_interval) ); FAPI_TRY( mss::eff_zqcal_interval(i_target, l_zqcal_interval) ); - // Get out of here if this isn't sim - we haven't done the work for calculating init cal periods + // TODO RTC:155854 We haven't done the work for calculating init cal periods // in effective config yet, and the MC setup below is hard wired for sim - if (!is_sim) - { - FAPI_ERR("Did you forget to implement periodic enables for power on?"); - fapi2::Assert(false); - } FAPI_DBG("memcal interval %dck, zqcal interval %dck", l_memcal_interval, l_zqcal_interval); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C index f3e4a3908..004f36720 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C @@ -151,7 +151,7 @@ fapi_try_exit: template<> fapi2::ReturnCode operation<TARGET_TYPE_MCBIST>::multi_port_init() { - FAPI_INF("multi-port init"); + FAPI_INF("multi-port init %s", mss::c_str(iv_target)); // Deterimine which ports are functional and whether we can broadcast to them // TK on the broadcast BRS diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index 9c9b04eaa..ad0e9eb13 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -389,26 +389,27 @@ fapi2::ReturnCode bang_bang_lock( const fapi2::Target<TARGET_TYPE_MCBIST>& i_tar FAPI_DBG("Wait at least 32 memory clock cycles"); FAPI_TRY( fapi2::delay(mss::cycles_to_ns(i_target, 32), mss::cycles_to_simcycles(32)) ); - // Don't bother in cycle sim, we don't do the actual aligment - if (!is_sim) + // TODO RTC: 153954 implement bang-bang lock and other analog type things we can't do in sim +#ifdef BANG_BANG_LOCK_IMPLEMENTED + + // Check for BB lock. + for (const auto& p : i_target.getChildren<TARGET_TYPE_MCA>()) { - // Check for BB lock. - for (const auto& p : i_target.getChildren<TARGET_TYPE_MCA>()) + FAPI_DBG("Wait for BB lock in status register, bit %u", + MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_BB_LOCK); + + FAPI_ASSERT( mss::poll(p, MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0, mss::poll_parameters(DELAY_100NS), + [](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool { - FAPI_DBG("Wait for BB lock in status register, bit %u", - MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_BB_LOCK); - - FAPI_ASSERT( mss::poll(p, MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0, mss::poll_parameters(DELAY_100NS), - [](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool - { - FAPI_DBG("stat_reg 0x%llx, remaining: %d", stat_reg, poll_remaining); - return stat_reg.getBit<MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_BB_LOCK>(); - }), - fapi2::MSS_BANG_BANG_FAILED_TO_LOCK().set_MCA_IN_ERROR(p), - "MCA %s failed bang-bang alignment", mss::c_str(p) ); - } + FAPI_DBG("stat_reg 0x%llx, remaining: %d", stat_reg, poll_remaining); + return stat_reg.getBit<MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_BB_LOCK>(); + }), + fapi2::MSS_BANG_BANG_FAILED_TO_LOCK().set_MCA_IN_ERROR(p), + "MCA %s failed bang-bang alignment", mss::c_str(p) ); } +#endif + fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H index bed4e6e77..754e4c16e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H @@ -48,6 +48,8 @@ inline uint64_t freq_bitfield_helper( const uint64_t i_freq ) { fapi2::buffer<uint64_t> l_data(0b1000); + FAPI_DBG("freq_bitfield_helper seeing MT/s: %d", i_freq); + // Shift l_data over based on freq. switch(i_freq) { @@ -64,7 +66,14 @@ inline uint64_t freq_bitfield_helper( const uint64_t i_freq ) l_data >>= 1; break; - // 2666 is >> 0 + case fapi2::ENUM_ATTR_MSS_FREQ_MT2666: + l_data >>= 0; + break; + + default: + FAPI_ERR("Unkown MT/s: %d", i_freq); + fapi2::Assert(false); + break; }; return l_data; diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H index ae06a6987..fd9304dd5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H @@ -27,6 +27,9 @@ // *HWP Level: 1 // *HWP Consumed by: FSP:HB +#ifndef MSS_FREQ_H_ +#define MSS_FREQ_H_ + #include <fapi2.H> #include <lib/freq/cas_latency.H> #include <lib/freq/cycle_time.H> @@ -135,3 +138,5 @@ extern "C" fapi2::ReturnCode p9_mss_freq( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target); } + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/tests/mss_memdiags_ut.C b/src/import/chips/p9/procedures/hwp/memory/tests/mss_memdiags_ut.C index a16e3230c..eee768350 100644 --- a/src/import/chips/p9/procedures/hwp/memory/tests/mss_memdiags_ut.C +++ b/src/import/chips/p9/procedures/hwp/memory/tests/mss_memdiags_ut.C @@ -67,6 +67,10 @@ TEST_CASE_METHOD(mss::test::mcbist_target_test_fixture, "memdiags", "[memdiags]" for_each_target([l_fir_mask](const fapi2::Target<TARGET_TYPE_MCBIST>& i_target) { + uint8_t is_sim = 0; + REQUIRE_FALSE( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), is_sim) ); + SECTION("Test thresholds structure") { mss::mcbist::thresholds l_t; @@ -193,6 +197,8 @@ TEST_CASE_METHOD(mss::test::mcbist_target_test_fixture, "memdiags", "[memdiags]" mss::mcbist::constraints l_const(memdiags::PATTERN_5); + FAPI_INF("\n\n\n start sf_init\n\n\n"); + // The addresses here are calculated so that we get a few iterations // of polling on an AWAN, but not so much that we run the risk of timing out mss::mcbist::address().get_range<mss::mcbist::address::COL>(l_const.iv_end_address); @@ -420,10 +426,13 @@ TEST_CASE_METHOD(mss::test::mcbist_target_test_fixture, "memdiags", "[memdiags]" { fapi2::buffer<uint64_t> l_read; + // We use different address end boundaries if we're in sim or not. + const uint64_t l_end_expect = is_sim ? 0x1fffffe07c000000 : 0x1ffffffffc000000; + REQUIRE_FALSE( mss::getScom(i_target, MCBIST_MCBSA0Q, l_read) ); REQUIRE(l_read == 0x1fffffc000000000); REQUIRE_FALSE( mss::getScom(i_target, MCBIST_MCBEA0Q, l_read) ); - REQUIRE(l_read == 0x1fffffe07c000000); + REQUIRE(l_read == l_end_expect); } // Poll for the fir bit. We expect this to be set ... @@ -514,20 +523,26 @@ TEST_CASE_METHOD(mss::test::mcbist_target_test_fixture, "memdiags", "[memdiags]" // Address config 0 should have the start and end for a complete DIMM (in sim) fapi2::buffer<uint64_t> l_read; + // We use different address end boundaries if we're in sim or not. + const uint64_t l_end_expect = is_sim ? 0x000000207C000000 : 0x1ffffffffc000000; + REQUIRE_FALSE( mss::getScom(i_target, MCBIST_MCBSA0Q, l_read) ); REQUIRE(l_read == 0x0); REQUIRE_FALSE( mss::getScom(i_target, MCBIST_MCBEA0Q, l_read) ); - REQUIRE(l_read == 0x000000207C000000); + REQUIRE(l_read == l_end_expect); } { // Address 1 should have the start we configured and an end which is the // real end of the DIMM address range fapi2::buffer<uint64_t> l_read; + // We use different address end boundaries if we're in sim or not. + const uint64_t l_end_expect = is_sim ? 0x1fffffe07c000000 : 0x1ffffffffc000000; + REQUIRE_FALSE( mss::getScom(i_target, MCBIST_MCBSA1Q, l_read) ); REQUIRE(l_read == 0x1fffffc000000000); REQUIRE_FALSE( mss::getScom(i_target, MCBIST_MCBEA1Q, l_read) ); - REQUIRE(l_read == 0x1fffffe07c000000); + REQUIRE(l_read == l_end_expect); } // Check the subtests @@ -587,10 +602,13 @@ TEST_CASE_METHOD(mss::test::mcbist_target_test_fixture, "memdiags", "[memdiags]" // Address config 0 should have the start and end for a complete DIMM (in sim) fapi2::buffer<uint64_t> l_read; + // We use different address end boundaries if we're in sim or not. + const uint64_t l_end_expect = is_sim ? 0x000000207C000000 : 0x1ffffffffc000000; + REQUIRE_FALSE( mss::getScom(i_target, MCBIST_MCBSA0Q, l_read) ); REQUIRE(l_read == 0x0); REQUIRE_FALSE( mss::getScom(i_target, MCBIST_MCBEA0Q, l_read) ); - REQUIRE(l_read == 0x000000207C000000); + REQUIRE(l_read == l_end_expect); } // Check the subtests |