INITPROC: Hostboot SW244284 Erepair power down lanes fix

Change-Id: I0082e06b594f96b0a0e8c9ba46695aaaba8a962b
CQ:SW244284
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/8936
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

4 files changed, 73 insertions, 22 deletions

diff --git a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C
index 3705e7b18..4133f68a5 100644
--- a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C
+++ b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013                   */
+/* COPYRIGHT International Business Machines Corp. 2013,2014              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_power_down_lanes.C,v 1.10 2013/11/20 00:57:38 varkeykv Exp $
+// $Id: io_power_down_lanes.C,v 1.12 2014/02/14 09:04:48 varkeykv Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -160,8 +160,18 @@ ReturnCode io_power_down_lanes(const Target& target,const std::vector<uint8_t> &
              }
         }
         //Power down this lane
+        rc = GCR_read( target,interface,tx_mode_pl, clock_group, lane,  data);
+        if(rc){return rc;}
+        FAPI_DBG("read out tx_mode_pl successfully for clock group%d lane %d",clock_group,lane);
+        rc_ecmd=data.setBit(0);
+         if(rc_ecmd)
+          {
+              rc.setEcmdError(rc_ecmd);
+              return(rc);
+          }
         rc = GCR_write( target, interface, tx_mode_pl, clock_group,  lane,  data,mask );
         if(rc){return rc;}
+        FAPI_DBG("Wrote tx_mode_pl successfullyfor clock group%d lane %d",clock_group,lane);
       }
 
       // Process RX lane powerdown 
@@ -178,9 +188,29 @@ ReturnCode io_power_down_lanes(const Target& target,const std::vector<uint8_t> &
         else{
           clock_group=start_group;
         }
-        //Power down this lane 
+        //Power down this lane
+        rc = GCR_read( target,interface,rx_mode_pl, clock_group, lane,  data);
+        if(rc){return rc;}
+         rc_ecmd=data.setBit(0);
+         if(rc_ecmd)
+          {
+              rc.setEcmdError(rc_ecmd);
+              return(rc);
+          } 
         rc = GCR_write( target, interface, rx_mode_pl, clock_group,  lane,  data,mask );
         if(rc){return rc;}
+        FAPI_DBG("Read rx_mode_pl successfully for clock group%d lane %d",clock_group,lane);
+        // As per Gary/ Defect SW244284 , as per Design team inputs add rx_wt_lane_disabled 
+        rc = GCR_read( target,interface,  rx_wt_status_pl, clock_group, lane,  data);
+        if(rc){return rc;}
+        rc_ecmd=data.setBit(0);
+         if(rc_ecmd)
+          {
+              rc.setEcmdError(rc_ecmd);
+              return(rc);
+          }  
+        rc = GCR_write( target, interface,   rx_wt_status_pl, clock_group,  lane,  data,mask );
+        FAPI_DBG("Wrote rx_mode_pl successfully for clock group%d lane %d",clock_group,lane);
       }
   return rc;
 }
diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile
index bb48c8f0d..0b18aaf83 100644
--- a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile
@@ -1,8 +1,11 @@
-#-- $Id: cen.dmi.custom.scom.initfile,v 1.18 2013/12/04 17:43:34 jgrell Exp $
+#-- $Id: cen.dmi.custom.scom.initfile,v 1.19 2014/02/12 20:06:07 jgrell Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+
+#--     1.19|jgrell  |02/12/14|Added FIR_ACTION1 setting and changed FIR_MASK setting for SW245013
+#--                           |Added rx_wt_lane_disabled=1 on lane 17 for SW244284
 #--     1.18|jgrell  |11/21/13|Added rx_trc_grp setting at the request of Yuen Tschang
 #--                           |Set rx_eo_ddc_timeout_sel to 110 for DD2
 #--     1.17|jgrell  |10/29/13|Changed rx_ds_timeout_sel setting to 111
@@ -313,9 +316,16 @@ rx_pb_fir_err_mask_gcr_buff2,    0b1;
 }
 
 # Mask off all rx and tx parity errors in the fir register
+# SCOM_FIR_MASK_PB: setting from SW245013
 scom 0x02010403 {
 scom_data;
-0xC000000000000000;
+0xDFFFFFFFFFFFC000;
+}
+
+# SCOM_FIR_ACTION1_PB: setting from SW245013
+scom 0x02010407 {
+scom_data;
+0xFFFFFFFFFFFFC000;
 }
 
 #--**************************************************************************************************************
@@ -390,7 +400,7 @@ scom 0x800.0b(rx_timeout_sel1_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
 
 #--**************************************************************************************************************
 #----------------------------------------------------------------------------------------------------------------
-# Power Down Unused Lanes
+# Power Down & Disable Unused Lanes
 #----------------------------------------------------------------------------------------------------------------
 #--**************************************************************************************************************
 
@@ -399,6 +409,11 @@ bits,                         	scom_data;
 rx_lane_pdwn,			0b1;
 }
 
+scom 0x800.0b(rx_wt_status_pl)(rx_grp0)(lane_17).0x(cn_gcr_addr) {
+bits,                         	scom_data;
+rx_wt_lane_disabled,		0b1;
+}
+
 ############################################################################################
 # END OF FILE
 ############################################################################################
diff --git a/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile
index d659aa828..ba018573f 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.a_x_pci_dmi_fir.scom.initfile,v 1.5 2013/10/28 06:56:28 jmcgill Exp $
+#-- $Id: p8.a_x_pci_dmi_fir.scom.initfile,v 1.6 2014/02/11 23:26:33 jmcgill Exp $
 #-------------------------------------------------------------------------------
 #--
 #-- (C) Copyright International Business Machines Corp. 2011
@@ -46,13 +46,13 @@ scom 0x02011A06 {
 #-- IOMC0.BUSCTL.SCOM.FIR_ACTION1_REG
 scom 0x02011A07 {
     bits, scom_data,          expr;
-    0:63, 0x207878787800C000, (mcl_enabled);
+    0:63, 0xFFFFFFFFFFFFC000, (mcl_enabled);
 }
 
 #-- IOMC0.BUSCTL.SCOM.FIR_MASK_REG
 scom 0x02011A03 {
     bits, scom_data,          expr;
-    0:63, 0xDFFFFFFFFFFF0000, (mcl_enabled);
+    0:63, 0xDFFFFFFFFFFFC000, (mcl_enabled);
 }
 
 #-- IOMC1.BUSCTL.SCOM.FIR_ACTION0_REG
@@ -64,13 +64,13 @@ scom 0x02011E06 {
 #-- IOMC1.BUSCTL.SCOM.FIR_ACTION1_REG
 scom 0x02011E07 {
     bits, scom_data,          expr;
-    0:63, 0x207878787800C000, (mcr_enabled);
+    0:63, 0xFFFFFFFFFFFFC000, (mcr_enabled);
 }
 
 #-- IOMC1.BUSCTL.SCOM.FIR_MASK_REG
 scom 0x02011E03 {
     bits, scom_data,          expr;
-    0:63, 0xDFFFFFFFFFFF0000, (mcr_enabled);
+    0:63, 0xDFFFFFFFFFFFC000, (mcr_enabled);
 }
 
 
@@ -89,13 +89,13 @@ scom 0x04011006 {
 #-- XBUS01.X0.BUSCTL.SCOM.FIR_ACTION1_REG
 scom 0x04011007 {
     bits, scom_data,          expr;
-    0:63, 0x207800000000C000, ((xbus_enabled) && (is_venice));
+    0:63, 0xFFFFFFFFFFFFC000, ((xbus_enabled) && (is_venice));
 }
 
 #-- XBUS01.X0.BUSCTL.SCOM.FIR_MASK_REG
 scom 0x04011003 {
     bits, scom_data,          expr;
-    0:63, 0xDFFFFFFFFFFF0000, ((xbus_enabled) && (is_venice));
+    0:63, 0xDFFFFFFFFFFFC000, ((xbus_enabled) && (is_venice));
 }
 
 #-- X1
@@ -110,14 +110,14 @@ scom 0x04011406 {
 #-- XBUS01.X1.BUSCTL.SCOM.FIR_ACTION1_REG
 scom 0x04011407 {
     bits, scom_data,          expr;
-    0:63, 0x207800000000C000, (xbus_enabled);
+    0:63, 0xFFFFFFFFFFFFC000, (xbus_enabled);
 }
 
 #-- XBUS1.BUSCTL.SCOM.FIR_MASK_REG
 #-- XBUS01.X1.BUSCTL.SCOM.FIR_MASK_REG
 scom 0x04011403 {
     bits, scom_data,          expr;
-    0:63, 0xDFFFFFFFFFFF0000, (xbus_enabled);
+    0:63, 0xDFFFFFFFFFFFC000, (xbus_enabled);
 }
 
 #-- X3
@@ -130,13 +130,13 @@ scom 0x04011806 {
 #-- XBUS23.X0.BUSCTL.SCOM.FIR_ACTION1_REG
 scom 0x04011807 {
     bits, scom_data,          expr;
-    0:63, 0x207800000000C000, ((xbus_enabled) && (is_venice));
+    0:63, 0xFFFFFFFFFFFFC000, ((xbus_enabled) && (is_venice));
 }
 
 #-- XBUS23.X0.BUSCTL.SCOM.FIR_MASK_REG
 scom 0x04011803 {
     bits, scom_data,          expr;
-    0:63, 0xDFFFFFFFFFFF0000, ((xbus_enabled) && (is_venice));
+    0:63, 0xDFFFFFFFFFFFC000, ((xbus_enabled) && (is_venice));
 }
 
 #-- X2
@@ -149,13 +149,13 @@ scom 0x04011C06 {
 #-- XBUS23.X1.BUSCTL.SCOM.FIR_ACTION1_REG
 scom 0x04011C07 {
     bits, scom_data,          expr;
-    0:63, 0x207800000000C000, ((xbus_enabled) && (is_venice));
+    0:63, 0xFFFFFFFFFFFFC000, ((xbus_enabled) && (is_venice));
 }
 
 #-- XBUS23.X1.BUSCTL.SCOM.FIR_MASK_REG
 scom 0x04011C03 {
     bits, scom_data,          expr;
-    0:63, 0xDFFFFFFFFFFF0000, ((xbus_enabled) && (is_venice));
+    0:63, 0xDFFFFFFFFFFFC000, ((xbus_enabled) && (is_venice));
 }
 
 
@@ -230,13 +230,13 @@ scom 0x08010C06 {
 #-- ABUS.BUSCTL.SCOM.FIR_ACTION1_REG
 scom 0x08010C07 {
     bits, scom_data,          expr;
-    0:63, 0x207878787878C000, (abus_enabled);
+    0:63, 0xFFFFFFFFFFFFC000, (abus_enabled);
 }
 
 #-- ABUS.BUSCTL.SCOM.FIR_MASK_REG
 scom 0x08010C03 {
     bits, scom_data,          expr;
-    0:63, 0xDFFFFFFFFFFF0000, (abus_enabled);
+    0:63, 0xDFFFFFFFFFFFC000, (abus_enabled);
 }
 
 #-- ABUS PB (PBES)
diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile
index 45a3886d2..f63380a2c 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile
@@ -1,8 +1,9 @@
-#-- $Id: p8.abus.custom.scom.initfile,v 1.12 2013/12/04 17:25:28 jgrell Exp $
+#-- $Id: p8.abus.custom.scom.initfile,v 1.13 2014/02/12 20:04:14 jgrell Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.13|jgrell  |02/12/14| Added rx_wt_lane_disabled=1 on lane 17 (SW244284)
 #--     1.12|jgrell  |12/03/13| Set rx_eo_ddc_timeout_sel to 110 for DD2
 #--     1.11|jgrell  |10/29/13| Changed rx_ds_timeout_sel setting to 111
 #--     1.9 |jgrell  |10/28/13| Re-enabled recal bits for DD2+ hw
@@ -326,6 +327,11 @@ bits,                         	scom_data;
 rx_lane_pdwn,			0b1;
 }
 
+scom 0x800.0b(rx_wt_status_pl)(rx_grp0)(lane_23).0x(abus_gcr_addr) {
+bits,                         	scom_data;
+rx_wt_lane_disabled,		0b1;
+}
+
 #--**************************************************************************************************************
 #----------------------------------------------------------------------------------------------------------------
 # Venice Specific Inits