HWP: integrate official version of mss_setup_bars

  - fixed MSS_CAL_STEP_ENABLE attribute is missing in mba target type
  - make dependency to new bbuild

RTC: 43375

Change-Id: I626c4c41caa1bba54264c24c8e1d2f3de22e9ad8
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1731
Tested-by: Jenkins Server
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

5 files changed, 665 insertions, 327 deletions

diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C
index ebc941ce8..f40659140 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C
@@ -1,26 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_setup_bars.C,v 1.22 2012/10/03 13:39:03 gpaulraj Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
 // *! All Rights Reserved -- Property of IBM
@@ -38,10 +38,18 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//  1.1    | gpaulraj | 03-19-12| First drop for centaur
-//  1.2    | gpaulraj | 05-07-12| 256 group configuration in
-//  1.3    | gpaulraj | 05-22-12| 2MCS/group supported for 128GB CDIMM
+//  1.22   | gpaulraj | 10/03/12| review updates
+//  1.21   | gpaulraj | 10/02/12| review updates
+//  1.19   | bellows  | 09/25/12| review updates
+//  1.18   | bellows  | 09/06/12| updates suggested by Van
+//  1.17   | bellows  | 08/31/12| use the final 32bit attribute
+//  1.16   | bellows  | 08/29/12| remove compile error, use 32bit group info
+//         |          |         | as a temporary fix
+//  1.10   | bellows  | 07/16/12| added in Id tag
 //  1.4    | bellows  | 06-05-12| Updates to Match First Configuration, work for P8 and Murano
+//  1.3    | gpaulraj | 05-22-12| 2MCS/group supported for 128GB CDIMM
+//  1.2    | gpaulraj | 05-07-12| 256 group configuration in
+//  1.1    | gpaulraj | 03-19-12| First drop for centaur
 //----------------------------------------------------------------------
 //  Includes
 //----------------------------------------------------------------------
@@ -50,236 +58,303 @@
 
 extern "C" {
 
-// PLAN:---
-//    Parameter  of the populated Dimm details for each MCS looper
-//    Starts with Zero MCS base address. Identifies Dimm parameters belong to MCS
-//    Configure the Group primary MCS0 Registers
-//    Configure the Group seconary MCS0 Registers /// identifies it base address based on the Primary group size
-//    Identify Mirror details setup accordingly
-//    Set up each translation registry accordingly
-//    SIM configuration
-//    -------------------------|-----------------------------------|
-//    -------    MCS0 ---------|-------------MCS1------------------|
-//    -------------------------|-----------------------------------|
-//    ---  CH01  --- CH23 -----|--------  CH01  --- CH23 ----------|
-//    D0-  32GB  --- 32GB -----|---- D0-  32GB  --- 32GB ----------|
-//    D1-  32GB  --- 32GB  ----|-----D1-  32GB  --- 32GB  ---------|
-//    -------------------------|-----------------------------------|
-//    - Base address MCS0 - 0x0  Group Size - 128GB
-//    - MCS0 -  Grouping base address  - 0GB Group size - 128GB
-//    - MCS1 -  Grouping base address  - 128GB+ Group size - 128GB
-
-fapi::ReturnCode mss_setup_bars(
-    const fapi::Target& i_chip_target)
-{
-	fapi::ReturnCode rc;
-	std::vector<fapi::Target> l_mcs_chiplets;
-	ecmdDataBufferBase MCFGP_data(64);
-
-    // platform attributes which define base addresses for this chip:
-    uint64_t mem_base;
+  fapi::ReturnCode mss_setup_bars(
+                                  const fapi::Target& i_chip_target)
+  {
+    fapi::ReturnCode rc;
+    std::vector<fapi::Target> l_mcs_chiplets;
+    ecmdDataBufferBase MCFGP_data(64);
+    ecmdDataBufferBase MCFGPM_data(64);
+    ecmdDataBufferBase MCFGPA_data(64);
+    ecmdDataBufferBase MCFGPMA_data(64);
+//    uint64_t mem_base;
     uint64_t mirror_base;
-
-    // storage for output attributes:
     uint64_t mem_bases[8];
     uint64_t l_memory_sizes[8];
     uint64_t mirror_bases[4];
     uint64_t l_mirror_sizes[4];
+    uint32_t groupID[16][16];
     uint8_t groups[8];
-
     do
     {
+      rc = FAPI_ATTR_GET(ATTR_MSS_MCS_GROUP_32, &i_chip_target, groupID);
+      if (!rc.ok())
+      {
+        FAPI_ERR("Error reading ATTR_MSS_MCS_GROUP_32");
+        break;
+      }
+      rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES, &i_chip_target, l_memory_sizes);
+      if (!rc.ok())
+      {
+        FAPI_ERR("Error reading ATTR_PROC_MEM_SIZES");
+        break;
+      }
+      rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASES, &i_chip_target, mem_bases);
+      if (!rc.ok())
+      {
+        FAPI_ERR("Error reading ATTR_PROC_MEM_BASES");
+        break;
+      }
+        //base addresses for distinct non-mirrored ranges
+
         //
         // process non-mirrored ranges
         //
 
         // read chip base address attribute
-        rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASE, &i_chip_target, mem_base);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error reading ATTR_PROC_MEM_BASE");
-            break;
-        }
+        //
+        // process mirrored ranges
+        //
 
-        // base addresses for distinct non-mirrored ranges
-        mem_bases[0]=mem_base;
-        mem_bases[1]=0x0;
-        mem_bases[2]=0x0;
-        mem_bases[3]=0x0;
-        mem_bases[4]=0x0;
-        mem_bases[5]=0x0;
-        mem_bases[6]=0x0;
-        mem_bases[7]=0x0;
+        // read chip base address attribute
+      rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE, &i_chip_target, mirror_base);
+      if (!rc.ok())
+      {
+        FAPI_ERR("Error reading ATTR_PROC_MIRROR_BASE");
+        break;
+      }
 
-        FAPI_DBG("  ATTR_PROC_MEM_BASES[0]: %016llx", mem_bases[0]);
-        FAPI_DBG("  ATTR_PROC_MEM_BASES[1]: %016llx", mem_bases[1]);
-        FAPI_DBG("  ATTR_PROC_MEM_BASES[2]: %016llx", mem_bases[2]);
-        FAPI_DBG("  ATTR_PROC_MEM_BASES[3]: %016llx", mem_bases[3]);
-        FAPI_DBG("  ATTR_PROC_MEM_BASES[4]: %016llx", mem_bases[4]);
-        FAPI_DBG("  ATTR_PROC_MEM_BASES[5]: %016llx", mem_bases[5]);
-        FAPI_DBG("  ATTR_PROC_MEM_BASES[6]: %016llx", mem_bases[6]);
-        FAPI_DBG("  ATTR_PROC_MEM_BASES[7]: %016llx", mem_bases[7]);
+        // base addresses for distinct mirrored ranges
+      mirror_bases[0] = mirror_base;
+      mirror_bases[1] = 0x0;
+      mirror_bases[2] = 0x0;
+      mirror_bases[3] = 0x0;
+
+      FAPI_DBG("  ATTR_PROC_MIRROR_BASES[0]: %016llx", mirror_bases[0]);
+      FAPI_DBG("  ATTR_PROC_MIRROR_BASES[1]: %016llx", mirror_bases[1]);
+      FAPI_DBG("  ATTR_PROC_MIRROR_BASES[2]: %016llx", mirror_bases[2]);
+      FAPI_DBG("  ATTR_PROC_MIRROR_BASES[3]: %016llx", mirror_bases[3]);
+
+      rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_BASES, &i_chip_target, mirror_bases);
+      if (!rc.ok())
+      {
+        FAPI_ERR("Error writing ATTR_PROC_MIRROR_BASES");
+        break;
+      }
 
-        rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASES, &i_chip_target, mem_bases);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error writing ATTR_PROC_MEM_BASES");
-            break;
-        }
+        // sizes for distinct mirrored ranges
+      l_mirror_sizes[0]=0;
+      l_mirror_sizes[1]=0;
+      l_mirror_sizes[2]=0;
+      l_mirror_sizes[3]=0;
+
+      FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[0]: %016llx", l_mirror_sizes[0]);
+      FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[1]: %016llx", l_mirror_sizes[1]);
+      FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[2]: %016llx", l_mirror_sizes[2]);
+      FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[3]: %016llx", l_mirror_sizes[3]);
+
+      rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_SIZES, &i_chip_target, l_mirror_sizes);
+      if (!rc.ok())
+      {
+        FAPI_ERR("Error writing ATTR_PROC_MIRROR_SIZES");
+        break;
+      }
+      groups[0]=0x0C;
+      groups[1]=0x00;
+      groups[2]=0x00;
+      groups[3]=0x00;
+      groups[4]=0x00;
+      groups[5]=0x00;
+      groups[6]=0x00;
+      groups[7]=0x00;
+      rc = FAPI_ATTR_SET(ATTR_MSS_MEM_MC_IN_GROUP, &i_chip_target, groups);
+      if (!rc.ok())
+      {
+        FAPI_ERR("Error writing ATTR_MSS_MEM_MC_IN_GROUP");
+        break;
+      }
 
-        // sizes for distinct non-mirrored ranges
-        l_memory_sizes[0]=128ULL*0x40000000ULL;
-        l_memory_sizes[1]=0x0;
-        l_memory_sizes[2]=0x0;
-        l_memory_sizes[3]=0x0;
-        l_memory_sizes[4]=0x0;
-        l_memory_sizes[5]=0x0;
-        l_memory_sizes[6]=0x0;
-        l_memory_sizes[7]=0x0;
+        //
+        // write HW registers
+        //
 
-        FAPI_DBG("  ATTR_PROC_MEM_SIZES[0]: %016llx", l_memory_sizes[0]);
-        FAPI_DBG("  ATTR_PROC_MEM_SIZES[1]: %016llx", l_memory_sizes[1]);
-        FAPI_DBG("  ATTR_PROC_MEM_SIZES[2]: %016llx", l_memory_sizes[2]);
-        FAPI_DBG("  ATTR_PROC_MEM_SIZES[3]: %016llx", l_memory_sizes[3]);
-        FAPI_DBG("  ATTR_PROC_MEM_SIZES[4]: %016llx", l_memory_sizes[4]);
-        FAPI_DBG("  ATTR_PROC_MEM_SIZES[5]: %016llx", l_memory_sizes[5]);
-        FAPI_DBG("  ATTR_PROC_MEM_SIZES[6]: %016llx", l_memory_sizes[6]);
-        FAPI_DBG("  ATTR_PROC_MEM_SIZES[7]: %016llx", l_memory_sizes[7]);
+        // get child MCS chiplets
+      rc = fapiGetChildChiplets(i_chip_target,
+                                fapi::TARGET_TYPE_MCS_CHIPLET,
+                                l_mcs_chiplets,
+                                fapi::TARGET_STATE_FUNCTIONAL);
+      if (!rc.ok())
+      {
+        FAPI_ERR("Error from fapiGetChildChiplets");
+        break;
+      }
 
-        rc = FAPI_ATTR_SET(ATTR_PROC_MEM_SIZES, &i_chip_target, l_memory_sizes);
+        // loop through & set configuration of each child
+      for (std::vector<fapi::Target>::iterator iter = l_mcs_chiplets.begin();
+           iter != l_mcs_chiplets.end() && rc.ok();
+           iter++)
+      {
+        uint8_t mcs_pos = 0x0;
+        rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*iter), mcs_pos);
         if (!rc.ok())
         {
-            FAPI_ERR("Error writing ATTR_PROC_MEM_SIZES");
-            break;
+          FAPI_ERR("Error reading ATTR_CHIP_UNIT_POS");
+          break;
         }
 
-
-        //
-        // process mirrored ranges
-        //
-
-        // read chip base address attribute
-        rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE, &i_chip_target, mirror_base);
+        MCFGP_data.flushTo0();
+        MCFGPM_data.flushTo0();
+        MCFGPA_data.flushTo0();
+        MCFGPMA_data.flushTo0();
+        rc = fapiGetScom(*iter, MCS_MCFGP_0x02011800, MCFGP_data);
         if (!rc.ok())
         {
-            FAPI_ERR("Error reading ATTR_PROC_MIRROR_BASE");
-            break;
+          FAPI_ERR("Error Reading  MCS_MCFGP_0x02011800");
+          break;
         }
-
-        // base addresses for distinct mirrored ranges
-        mirror_bases[0] = mirror_base;
-        mirror_bases[1] = 0x0;
-        mirror_bases[2] = 0x0;
-        mirror_bases[3] = 0x0;
-
-        FAPI_DBG("  ATTR_PROC_MIRROR_BASES[0]: %016llx", mirror_bases[0]);
-        FAPI_DBG("  ATTR_PROC_MIRROR_BASES[1]: %016llx", mirror_bases[1]);
-        FAPI_DBG("  ATTR_PROC_MIRROR_BASES[2]: %016llx", mirror_bases[2]);
-        FAPI_DBG("  ATTR_PROC_MIRROR_BASES[3]: %016llx", mirror_bases[3]);
-
-        rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_BASES, &i_chip_target, mirror_bases);
+        MCFGP_data.setBit(9);
+        MCFGP_data.setBit(10);
+        MCFGP_data.setBit(24);
+        rc = fapiPutScom(*iter, MCS_MCFGP_0x02011800, MCFGP_data);
         if (!rc.ok())
         {
-            FAPI_ERR("Error writing ATTR_PROC_MIRROR_BASES");
-            break;
+          FAPI_ERR("Error writing  MCS_MCFGP_0x02011800");
+          break;
         }
-
-        // sizes for distinct mirrored ranges
-        l_mirror_sizes[0]=0;
-        l_mirror_sizes[1]=0;
-        l_mirror_sizes[2]=0;
-        l_mirror_sizes[3]=0;
-
-        FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[0]: %016llx", l_mirror_sizes[0]);
-        FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[1]: %016llx", l_mirror_sizes[1]);
-        FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[2]: %016llx", l_mirror_sizes[2]);
-        FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[3]: %016llx", l_mirror_sizes[3]);
-
-        rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_SIZES, &i_chip_target, l_mirror_sizes);
+        rc = fapiGetScom(*iter, MCS_MCFGPM_0x02011801, MCFGPM_data);
         if (!rc.ok())
         {
-            FAPI_ERR("Error writing ATTR_PROC_MIRROR_SIZES");
-            break;
-        }
-
-
-        //
-        // process group configuration
-        //
-
-        groups[0]=0x0C;
-        groups[1]=0x00;
-        groups[2]=0x00;
-        groups[3]=0x00;
-        groups[4]=0x00;
-        groups[5]=0x00;
-        groups[6]=0x00;
-        groups[7]=0x00;
-        rc = FAPI_ATTR_SET(ATTR_MSS_MEM_MC_IN_GROUP, &i_chip_target, groups);
+          FAPI_ERR("Error Reading  MCS_MCFGPM_0x02011801");
+          break;
+        }	       	
+        rc = fapiGetScom(*iter, MCS_MCFGPA_0x02011814, MCFGPA_data);
         if (!rc.ok())
         {
-            FAPI_ERR("Error writing ATTR_MSS_MEM_MC_IN_GROUP");
-            break;
-        }
-
-
-        //
-        // write HW registers
-        //
-
-        // get child MCS chiplets
-        rc = fapiGetChildChiplets(i_chip_target,
-                                  fapi::TARGET_TYPE_MCS_CHIPLET,
-                                  l_mcs_chiplets,
-                                  fapi::TARGET_STATE_FUNCTIONAL);
+          FAPI_ERR("Error Reading  MCS_MCFGPA_0x02011814");
+          break;
+        }	
+        rc = fapiGetScom(*iter, MCS_MCFGPMA_0x02011815, MCFGPMA_data);
         if (!rc.ok())
         {
-            FAPI_ERR("Error from fapiGetChildChiplets");
-            break;
+          FAPI_ERR("Error Reading  MCS_MCFGPMA_0x02011815");
+          break;
         }
-
-        // loop through & set configuration of each child
-        for (std::vector<fapi::Target>::iterator iter = l_mcs_chiplets.begin();
-             iter != l_mcs_chiplets.end();
-             iter++)
+        for(uint8_t i=0; (i<16)&&(rc.ok()); i++)
         {
-            uint8_t mcs_pos = 0x0;
-            rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*iter), mcs_pos);
-            if (!rc.ok())
+          uint32_t temp=0;
+          temp = groupID[i][1];
+          uint32_t b=0;
+          for(uint32_t j=4;(j<temp+4)&&(rc.ok());j++)
+          {
+            if(groupID[i][j]==mcs_pos)
             {
-                FAPI_ERR("Error reading ATTR_CHIP_UNIT_POS");
+              FAPI_INF(" Group ID of no MCS %d is %d MCS_POS  ID  found for %d as %d ",temp, i,mcs_pos,(j-4));
+                        //temp =(temp/2;
+              MCFGP_data.insertFromRight(temp/2,1,3);
+              MCFGP_data.insertFromRight((j-4),4,5);
+
+                     //b = groupID[i][2]>>3;
+              b = ((l_memory_sizes[i]>>30) / 4) - 1;
+              // 					switch ((l_memory_sizes[i]>>30))
+              // 					{
+              // 						case 4:   b = 0;
+              // 						break;
+              //                                                case 8:   b = 1;
+              //                                                break;
+              //                                                case 16:  b = 3;
+              //            l                                    break;
+              //                                                case 32:  b = 7;
+              //                                                break;
+              //                                                case 64:  b = 15;
+              //                                                break;
+              //                                                case 128: b = 31;
+              //                                                break;
+              //                                                case 256: b = 63;
+              //                                                break;
+              //                                                case 512: b = 127;
+              //                                                break;
+              //                                                case 1024:b = 255;
+              //                                                break;
+              //                                                case 2048:b = 511;
+              //                                                break;
+              //                                                case 4096:b = 1023;
+              //                                                break;
+              //                                                case 8192:b = 2047;
+              //                                                break;
+              //                                   }
+              MCFGP_data.insertFromRight(b,11,13);
+              b = mem_bases[i]>>32;
+              MCFGP_data.insertFromRight(b,26,18);
+              MCFGP_data.setBit(25);
+              rc = fapiPutScom(*iter, MCS_MCFGP_0x02011800, MCFGP_data);
+              if (!rc.ok())
+              {
+                FAPI_ERR("Error writing  MCS_MCFGP_0x02011800");
                 break;
-            }
-
-            // set configuration registers (static to match VBU model for now)
-            if (mcs_pos == 4)
-            {
-                MCFGP_data.setDoubleWord(0, 0x90601FC000000000ULL);
-            }
-            else if (mcs_pos == 5)
-            {
-                MCFGP_data.setDoubleWord(0, 0x90E01FC000000000ULL);
-            }
-            else
-            {
-                MCFGP_data.setDoubleWord(0, 0x0060008000000000ULL);
-            }
-
-            // write MCFGP register
-            FAPI_DBG("Writing MCS %d MCFGP = 0x%llx",
-                     mcs_pos, MCFGP_data.getDoubleWord(0));
-
-            rc = fapiPutScom(*iter, MCS_MCFGP_0x02011800, MCFGP_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from fapiPutScom (MCS_MCFGP_0x02011800)");
+              }		
+              rc = fapiGetScom(*iter, MCS_MCFGP_0x02011800, MCFGP_data);
+              if (!rc.ok())
+              {
+                FAPI_ERR("Error Reading  MCS_MCFGP_0x02011800");
                 break;
+              }			
+              MCFGP_data.setBit(0);  //  Read registers value and set Zero bit as per register specification
+              FAPI_DBG("Writing MCS %d MCFGP = 0x%llx",mcs_pos, MCFGP_data.getDoubleWord(0));
+              rc = fapiPutScom(*iter, MCS_MCFGP_0x02011800, MCFGP_data);
+              if (!rc.ok())
+              {
+                FAPI_ERR("Error from fapiPutScom MCS_MCFGP_0x02011800");
+                break;
+              }
+              if(groupID[i][12])
+              {
+                b = ((groupID[i][13]) / 4) - 1;
+//                            switch (groupID[i][13])
+// 				 {
+// 							case 4:   b = 0;
+// 							break;
+// 							case 8:   b = 1;
+// 							break;
+// 							case 16:  b = 3;
+// 							break;
+// 							case 32:  b = 7;
+// 							break;
+// 							case 64:  b = 15;
+// 							break;
+// 							case 128: b = 31;
+// 							break;
+// 							case 256: b = 63;
+// 							break;
+// 							case 512: b = 127;
+// 							break;
+// 							case 1024:b = 255;
+// 							break;
+// 							case 2048:b = 511;
+// 							break;
+// 							case 4096:b = 1023;
+// 							break;
+// 							case 8192:b = 2047;
+// 							break;		
+// 				 }
+                MCFGPA_data.insertFromRight(b,11,13);
+                b = groupID[i][14]>>2;
+                MCFGPA_data.insertFromRight(b,26,18);
+                rc = fapiPutScom(*iter, MCS_MCFGPA_0x02011814, MCFGPA_data);
+                if (!rc.ok())
+                {
+                  FAPI_ERR("Error writing  MCS_MCFGPA_0x02011814");
+                  break;
+                }		       		
+                rc = fapiGetScom(*iter, MCS_MCFGPA_0x02011814, MCFGPA_data);
+                if (!rc.ok())
+                {
+                  FAPI_ERR("Error reading  MCS_MCFGPA_0x02011814");
+                  break;
+                }					
+                MCFGPA_data.setBit(0);  //  Read registers value and set Zero bit as per register specification
+                rc = fapiPutScom(*iter, MCS_MCFGPA_0x02011814, MCFGPA_data);
+                if (!rc.ok())
+                {
+                  FAPI_ERR("Error writing  MCS_MCFGPA_0x02011814");
+                  break;
+                }		       		
+              }
             }
+          }
         }
-    } while(0);
-
+      }
+    }
+    while(0);
     return rc;
-}
-
-
+  }
 } // extern "C"
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H
index 2affbd35f..f86879271 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H
@@ -1,26 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_setup_bars.H,v 1.3 2012/07/17 13:23:32 bellows Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -42,6 +42,7 @@
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
 //  1.1    | gpaulraj | 03/19/12| Updated
+//  1.3    | bellows  | 07/16/12| added in Id tag
 
 #ifndef MSS_SETUP_BARS_H_
 #define MSS_SETUP_BARS_H_
diff --git a/src/usr/hwpf/hwp/include/common_scom_addresses.H b/src/usr/hwpf/hwp/include/common_scom_addresses.H
index e264dc53c..e13c4ce5b 100755
--- a/src/usr/hwpf/hwp/include/common_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/common_scom_addresses.H
@@ -1,27 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/include/common_scom_addresses.H $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-// $Id: common_scom_addresses.H,v 1.22 2012/07/24 15:52:06 koenig Exp $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/include/common_scom_addresses.H $            */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: common_scom_addresses.H,v 1.30 2012/09/13 19:55:40 mfred Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/common_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -176,6 +175,11 @@ CONST_UINT64_T( GENERIC_GP3_OR_0x000F0014             , ULL(0x000F0014) );
 CONST_UINT64_T( GENERIC_PMGP0_OR_0x000F0102           , ULL(0x000F0102) );
 
 //------------------------------------------------------------------------------
+//      GENERIC PLLLOCK REG
+//------------------------------------------------------------------------------
+CONST_UINT64_T( GENERIC_PLLLOCKREG_0x000F0019         , ULL(0x000F0019) );
+
+//------------------------------------------------------------------------------
 //      GENERIC HANG PULSE CONTROL
 //------------------------------------------------------------------------------
 CONST_UINT64_T( GENERIC_HANG_P0_0x000F0020            , ULL(0x000F0020) );
@@ -203,6 +207,14 @@ CONST_UINT32_T( CFAM_FSI_GP7_0x00001016               , ULL(0x00001016) );
 CONST_UINT32_T( CFAM_FSI_GP8_0x00001017               , ULL(0x00001017) );
 CONST_UINT32_T( CFAM_FSI_GP3_MIRROR_0x0000101B        , ULL(0x0000101B) );
 
+CONST_UINT32_T( CFAM_FSI_GP3_0x00002812               , ULL(0x00002812) );
+CONST_UINT32_T( CFAM_FSI_GP4_0x00002813               , ULL(0x00002813) );
+CONST_UINT32_T( CFAM_FSI_GP5_0x00002814               , ULL(0x00002814) );
+CONST_UINT32_T( CFAM_FSI_GP6_0x00002815               , ULL(0x00002815) );
+CONST_UINT32_T( CFAM_FSI_GP7_0x00002816               , ULL(0x00002816) );
+CONST_UINT32_T( CFAM_FSI_GP8_0x00002817               , ULL(0x00002817) );
+CONST_UINT32_T( CFAM_FSI_GP3_MIRROR_0x0000281B        , ULL(0x0000281B) );
+
 //------------------------------------------------------------------------------
 //      OTPROM
 //------------------------------------------------------------------------------
@@ -251,11 +263,14 @@ CONST_UINT64_T( MBOX_GP3MIR_0x0005001B                , ULL(0x0005001B) );
 CONST_UINT64_T( MBOX_SBEVITAL_0x0005001C              , ULL(0x0005001C) );
 CONST_UINT64_T( MBOX_SCRATCH_REG0_0x00050038          , ULL(0x00050038) );
 CONST_UINT64_T( MBOX_SCRATCH_REG1_0x00050039          , ULL(0x00050039) );
+CONST_UINT64_T( MBOX_SCRATCH_REG2_0x0005003A          , ULL(0x0005003A) );
+CONST_UINT64_T( MBOX_SCRATCH_REG3_0x0005003B          , ULL(0x0005003B) );
 
 //------------------------------------------------------------------------------
 //      TP ADDITIONAL REGISTER
 //------------------------------------------------------------------------------
 CONST_UINT64_T( TP_PLL_LOCK_0x010F0019                 , ULL(0x010F0019) );
+CONST_UINT64_T( TP_CLK_ADJ_SET_0x010F0016              , ULL(0x010F0016) );
 
 
 //------------------------------------------------------------------------------
@@ -447,16 +462,10 @@ CONST_UINT64_T( WRITE_ALL_GP0_OR_0x6B000005           , ULL(0x6B000005) );
 
 CONST_UINT64_T( READ_ALL_GP1_AND_0x4B000001           , ULL(0x4B000001) );       // and all GP1 but not PRV
 
-CONST_UINT64_T( WRITE_EX_GP3_AND_0x690F0013           , ULL(0x690F0013) );       // and all EX GP3
-CONST_UINT64_T( WRITE_EX_GP3_OR_0x690F0014            , ULL(0x690F0014) );       // or all EX GP3
-
-
-CONST_UINT64_T( WRITE_EX_PMGP0_OR_0x690F0102          , ULL(0x690F0102) );       // or all EX PMGP0
-
 CONST_UINT64_T( WRITE_ALL_CLK_REGION_0x6B030006       , ULL(0x6B030006) );       // all GP3 but not PRV
 
-CONST_UINT64_T( READ_ALL_OPCG_CNTL0_0x43030002        , ULL(0x43030002) );       // all EX OPCG0
-CONST_UINT64_T( WRITE_ALL_OPCG_CNTL0_0x6B030002       , ULL(0x6B030002) );       // all EX OPCG0
+CONST_UINT64_T( READ_ALL_OPCG_CNTL0_0x43030002        , ULL(0x43030002) );       // all OPCG0 but not PRV
+CONST_UINT64_T( WRITE_ALL_OPCG_CNTL0_0x6B030002       , ULL(0x6B030002) );       // all OPCG0 but not PRV
 
 CONST_UINT64_T( READ_ALL_OPCG_CNTL2_0x43030004        , ULL(0x43030004) );       // all OPCG2 but not PRV
 CONST_UINT64_T( WRITE_ALL_OPCG_CNTL2_0x6B030004       , ULL(0x6B030004) );       // all OPCG2 but not PRV
@@ -498,6 +507,8 @@ CONST_UINT64_T( READ_ALL_PCB_SLAVE_ATTN_INT_0x500F001A   , ULL(0x500F001A) ); //
 CONST_UINT64_T( READ_ALL_PCB_SLAVE_RECOV_INT_0x500F001B  , ULL(0x500F001B) ); // group0: all chiplets
 CONST_UINT64_T( READ_ALL_PCB_SLAVE_XSTOP_INT_0x500F001C  , ULL(0x500F001C) ); // group0: all chiplets
 
+CONST_UINT64_T( WRITE_ALL_GP0_OR_0x68000005              , ULL(0x68000005) ); // group0: all chiplets
+
 CONST_UINT64_T( WRITE_ALL_FUNC_GP0_0x6B000000            , ULL(0x6B000000) ); // group3: all except PRV: GP0
 CONST_UINT64_T( WRITE_ALL_FUNC_GP1_0x6B000001            , ULL(0x6B000001) ); // group3: all except PRV: GP1
 CONST_UINT64_T( WRITE_ALL_FUNC_GP2_0x6B000002            , ULL(0x6B000002) ); // group3: all except PRV: GP2
@@ -573,6 +584,30 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: common_scom_addresses.H,v $
+Revision 1.30  2012/09/13 19:55:40  mfred
+Move group 1 multicast definitions (EX chiplet) to p8_scom_addresses.H.
+
+Revision 1.29  2012/09/13 19:42:43  mfred
+fix misleading comment.
+
+Revision 1.28  2012/09/12 17:10:18  jmcgill
+add remainder of mailbox scratch registers
+
+Revision 1.27  2012/08/17 16:46:50  mfred
+Committing common PLL lock address for EX cores.
+
+Revision 1.26  2012/08/16 13:06:19  gweber
+added remaining CFAM-addresses 28xx
+
+Revision 1.25  2012/08/11 22:20:37  jmcgill
+add multicast GP0 OR address (all chiplets)
+
+Revision 1.24  2012/08/08 13:28:18  gweber
+added CFAM-addresses 28xx
+
+Revision 1.23  2012/08/07 09:09:43  koenig
+Added TP skewadjust register - AK
+
 Revision 1.22  2012/07/24 15:52:06  koenig
 Added EX GP3 OR codepoint - AK
 
diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
index 96875564b..280aa860d 100755
--- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
@@ -1,27 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/include/p8_scom_addresses.H $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-// $Id: p8_scom_addresses.H,v 1.82 2012/06/27 07:43:32 rkoester Exp $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/include/p8_scom_addresses.H $                */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: p8_scom_addresses.H,v 1.105 2012/09/26 17:53:25 jklazyns Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -114,11 +113,22 @@ CONST_UINT64_T( ALL_CHIPLETS_BITX_0x50000000          , ULL(0x50000000) );
 CONST_UINT64_T( ALL_CHIPLETS_COMP_0x60000000          , ULL(0x60000000) );
 CONST_UINT64_T( ALL_CHIPLETS_WRITE_0x68000000         , ULL(0x68000000) );
 
+// Group 1 : EX chiplets
 CONST_UINT64_T( ALL_EXS_OR_0x41000000                 , ULL(0x41000000) );
 CONST_UINT64_T( ALL_EXS_AND_0x49000000                , ULL(0x49000000) );
 CONST_UINT64_T( ALL_EXS_BITX_0x51000000               , ULL(0x51000000) );
 CONST_UINT64_T( ALL_EXS_COMP_0x61000000               , ULL(0x61000000) );
 CONST_UINT64_T( ALL_EXS_WRITE_0x69000000              , ULL(0x69000000) );
+CONST_UINT64_T( WRITE_ALL_EXS_GP0_AND_0x69000004      , ULL(0x69000004) );
+CONST_UINT64_T( WRITE_ALL_EXS_GP0_OR_0x69000005       , ULL(0x69000005) );
+CONST_UINT64_T( WRITE_ALL_EXS_CLK_REGION_0x69030006   , ULL(0x69030006) );
+CONST_UINT64_T( WRITE_ALL_EXS_CLK_SCANSEL_0x69030007  , ULL(0x69030007) );
+CONST_UINT64_T( READ_OR_ALL_EXS_CLK_STATUS_0x41030008 , ULL(0x41030008) );
+CONST_UINT64_T( WRITE_ALL_EXS_GP3_AND_0x690F0013      , ULL(0x690F0013) );
+CONST_UINT64_T( WRITE_ALL_EXS_GP3_OR_0x690F0014       , ULL(0x690F0014) );
+CONST_UINT64_T( WRITE_EX_GP3_AND_0x690F0013           , ULL(0x690F0013) );       // and all EX GP3
+CONST_UINT64_T( WRITE_EX_GP3_OR_0x690F0014            , ULL(0x690F0014) );       // or all EX GP3
+CONST_UINT64_T( WRITE_EX_PMGP0_OR_0x690F0102          , ULL(0x690F0102) );       // or all EX PMGP0
 
 CONST_UINT64_T( ALL_CORES_OR_0x42000000               , ULL(0x42000000) );
 CONST_UINT64_T( ALL_CORES_AND_0x4A000000              , ULL(0x4A000000) );
@@ -132,10 +142,32 @@ CONST_UINT64_T( ALL_CORES_WRITE_0x6A000000            , ULL(0x6A000000) );
 /******************************************************************************/
 
 //------------------------------------------------------------------------------
+//      FSI MBOX (CFAM)
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBOX_SCRATCH_REG0_0x00002838          , ULL(0x00002838) );
+CONST_UINT64_T( MBOX_SCRATCH_REG1_0x00002839          , ULL(0x00002839) );
+CONST_UINT64_T( MBOX_SCRATCH_REG2_0x0000283A          , ULL(0x0000283A) );
+CONST_UINT64_T( MBOX_SCRATCH_REG3_0x0000283B          , ULL(0x0000283B) );
+
+//------------------------------------------------------------------------------
 //      OTPROM
 //------------------------------------------------------------------------------
-CONST_UINT64_T( ECID_PART_0_0x00018000                   , ULL(0x00018000) );
-CONST_UINT64_T( ECID_PART_1_0x00018001                   , ULL(0x00018001) );
+CONST_UINT64_T( SECURITY_SWITCH_0x00010005            , ULL(0x00010005) );
+CONST_UINT64_T( ECID_PART_0_0x00018000                , ULL(0x00018000) );
+CONST_UINT64_T( ECID_PART_1_0x00018001                , ULL(0x00018001) );
+
+//------------------------------------------------------------------------------
+//      Time of Day (TOD)
+//------------------------------------------------------------------------------
+CONST_UINT64_T( TOD_FSM_REG_00040024                  , ULL(0x00040024) );
+
+
+//------------------------------------------------------------------------------
+//      SBE VITAL REG
+//------------------------------------------------------------------------------
+CONST_UINT64_T( PORE_SBE_VITAL_0x0005001C             , ULL(0x0005001C) );
+
+
 
 //------------------------------------------------------------------------------
 //      PORE-GPE0
@@ -299,6 +331,15 @@ CONST_UINT64_T( OCB3_UNTRUSTED_CONTROL_0x0006A237     , ULL(0x0006A237) );
 CONST_UINT64_T( OCB3_LIN_WINDOW_CONTROL_0x0006A238    , ULL(0x0006A238) );
 CONST_UINT64_T( OCB3_LIN_WINDOW_BASE_0x0006A23C       , ULL(0x0006A23C) );
 
+CONST_UINT64_T( OCC_LFIR_0x01010800                   , ULL(0x01010800) ); 
+CONST_UINT64_T( OCC_LFIR_AND_0x01010801               , ULL(0x01010801) );
+CONST_UINT64_T( OCC_LFIR_OR_0x01010802                , ULL(0x01010802) );
+CONST_UINT64_T( OCC_LFIR_MASK_0x01010803              , ULL(0x01010803) );
+CONST_UINT64_T( OCC_LFIR_MASK_AND_0x01010804          , ULL(0x01010804) );
+CONST_UINT64_T( OCC_LFIR_MASK_OR_0x01010805           , ULL(0x01010805) );
+CONST_UINT64_T( OCC_LFIR_ACT0_0x01010806              , ULL(0x01010806) );
+CONST_UINT64_T( OCC_LFIR_ACT1_0x01010807              , ULL(0x01010807) );
+
 // sram registers
 CONST_UINT64_T( OCC_SRAM_BOOT_VEC0_0x00066004         , ULL(0x00066004) );
 CONST_UINT64_T( OCC_SRAM_BOOT_VEC1_0x00066005         , ULL(0x00066005) );
@@ -308,11 +349,17 @@ CONST_UINT64_T( OCC_SRAM_BOOT_VEC3_0x00066007         , ULL(0x00066007) );
 //------------------------------------------------------------------------------
 //      PMC
 //------------------------------------------------------------------------------
-// todo:  the full set needs to be added.  The ones below are for SLW at this time
 
 // PIB Space Addresses
 
-
+CONST_UINT64_T( PMC_MODE_REG_0x00062000               , ULL(0x00062000) );
+CONST_UINT64_T( PMC_PSTATE_MONITOR_AND_CTRL_REG_0x00062002, ULL(0x00062002)) ;
+CONST_UINT64_T( PMC_PARAMETER_REG1_0x00062006         , ULL(0x00062006)) 
+CONST_UINT64_T( PMC_STATUS_REG_0x00062009             , ULL(0x00062009)) ;
+CONST_UINT64_T( PMC_OCC_HEARTBEAT_REG_0x00062066      , ULL(0x00062066)) ;
+CONST_UINT64_T( PMC_CORE_DECONFIG_REG_0x0006200D      , ULL(0x0006200D) );
+CONST_UINT64_T( PMC_FSMSTATE_STATUS_REG_0x00062000    , ULL(0x00062020) );
+// SPIVID Controller
 CONST_UINT64_T( PMC_SPIV_CTRL_REG0A_0x00062040        , ULL(0x00062040) );
 CONST_UINT64_T( PMC_SPIV_CTRL_REG0B_0x00062041        , ULL(0x00062041) );
 CONST_UINT64_T( PMC_SPIV_CTRL_REG1_0x00062042         , ULL(0x00062042) );
@@ -321,8 +368,7 @@ CONST_UINT64_T( PMC_SPIV_CTRL_REG3_0x00062044         , ULL(0x00062044) );
 CONST_UINT64_T( PMC_SPIV_CTRL_REG4_0x00062045         , ULL(0x00062045) );
 CONST_UINT64_T( PMC_SPIV_STATUS_REG_0x00062046        , ULL(0x00062046) );
 CONST_UINT64_T( PMC_SPIV_COMMAND_REG_0x00062047       , ULL(0x00062047) );
-
-
+// OCI to SPI (O2S)
 CONST_UINT64_T( PMC_O2S_CTRL_REG0A_0x00062050         , ULL(0x00062050) );
 CONST_UINT64_T( PMC_O2S_CTRL_REG0B_0x00062051         , ULL(0x00062051) ); 		
 CONST_UINT64_T( PMC_O2S_CTRL_REG1_0x00062052          , ULL(0x00062052) ); 		
@@ -332,13 +378,17 @@ CONST_UINT64_T( PMC_O2S_STATUS_REG_0x00062056         , ULL(0x00062056) );
 CONST_UINT64_T( PMC_O2S_COMMAND_REG_0x00062057        , ULL(0x00062057) ); 		
 CONST_UINT64_T( PMC_O2S_WDATA_REG_0x00062058          , ULL(0x00062058) ); 		
 CONST_UINT64_T( PMC_O2S_RDATA_REG_0x00062059          , ULL(0x00062059) );
-
+// PORE interface
 CONST_UINT64_T( PMC_PORE_REQ_STAT_REG_0x00062090      , ULL(0x00062090) );
-CONST_UINT64_T( PMC_MODE_REG_0x00062000               , ULL(0x00062000) );
 
+// OCI Space Addresses
 
+CONST_UINT32_T( OCI_PMC_PORE_REQ_STAT_REG_0x40010480  , ULL(0x40010480) );
 
 
+//------------------------------------------------------------------------------
+//      SPIADC
+//------------------------------------------------------------------------------
 CONST_UINT64_T( SPIPSS_ADC_CTRL_REG0_0x00070000       , ULL(0x00070000) );
 CONST_UINT64_T( SPIPSS_ADC_CTRL_REG1_0x00070001       , ULL(0x00070001) );
 CONST_UINT64_T( SPIPSS_ADC_CTRL_REG2_0x00070002       , ULL(0x00070002) );
@@ -360,21 +410,10 @@ CONST_UINT64_T( SPIPSS_P2S_RDATA_REG_0x00070060       , ULL(0x00070060) );
 CONST_UINT64_T( SPIPSS_ADC_RESET_REGISTER_0x00070005  , ULL(0x00070005) );
 CONST_UINT64_T( SPIPSS_P2S_RESET_REGISTER_0x00070045  , ULL(0x00070045) );
 
-
-// OCI Space Addresses
-CONST_UINT32_T( OCI_PMC_PORE_REQ_STAT_REG_0x40010480  , ULL(0x40010480) );
-
-
-//------------------------------------------------------------------------------
-//      SPIADC
-//------------------------------------------------------------------------------
-CONST_UINT64_T( SPIADC_0x00070000                     , ULL(0x00070000) );
-
 //------------------------------------------------------------------------------
 //      PIB-ATTACHED MEMORY
 //------------------------------------------------------------------------------
 CONST_UINT64_T( PIBMEM0_0x00080000                    , ULL(0x00080000) );
-
 CONST_UINT64_T( PIBMEM_CONTROL_0x00088000             , ULL(0x00088000) );
 CONST_UINT64_T( PIBMEM_ADDRESS_0x00088001             , ULL(0x00088001) );
 CONST_UINT64_T( PIBMEM_DATA_0x00088002                , ULL(0x00088002) );
@@ -385,6 +424,12 @@ CONST_UINT64_T( PIBMEM_RESET_0x00088006               , ULL(0x00088006) );
 CONST_UINT64_T( PIBMEM_REPAIR_LOAD_0x00088007         , ULL(0x00088007) );
 
 //------------------------------------------------------------------------------
+//      I2C MASTER (MODE)
+//------------------------------------------------------------------------------
+CONST_UINT64_T( I2CM_MODE_REGISTER_0_0x000A0006       , ULL(0x000A0006) );
+
+
+//------------------------------------------------------------------------------
 //      I2C MASTER (MEMS1)
 //------------------------------------------------------------------------------
 CONST_UINT64_T( I2CMS_MEMS1_CONTROL_0x000A0020        , ULL(0x000A0020) );
@@ -404,6 +449,29 @@ CONST_UINT64_T( I2CMS_PCI_DATA_0x000A0043             , ULL(0x000A0043) );
 CONST_UINT64_T( I2CMS_PCI_COMMAND_0x000A0045          , ULL(0x000A0045) );
 
 //------------------------------------------------------------------------------
+//      LPC
+//------------------------------------------------------------------------------
+CONST_UINT64_T( LPC_CONTROL_0x000B0000                , ULL(0x000B0000) );
+CONST_UINT64_T( LPC_RESET_0x000B0001                  , ULL(0x000B0001) );
+CONST_UINT64_T( LPC_STATUS_0x000B0002                 , ULL(0x000B0002) );
+CONST_UINT64_T( LPC_DATA_0x000B0003                   , ULL(0x000B0003) );
+CONST_UINT64_T( LPC_ECC_ADDRESS_0x000B0004            , ULL(0x000B0004) );
+CONST_UINT64_T( LPC_I2C_ADDRESS_0x000B0005            , ULL(0x000B0005) );
+CONST_UINT64_T( LPC_FW_CONTROL_0x000B0020             , ULL(0x000B0020) );
+CONST_UINT64_T( LPC_FW_RESET_0x000B0021               , ULL(0x000B0021) );
+CONST_UINT64_T( LPC_FW_STATUS_0x000B0022              , ULL(0x000B0022) );
+CONST_UINT64_T( LPC_FW_DATA_0x000B0023                , ULL(0x000B0023) );
+
+//------------------------------------------------------------------------------
+//    PORE_ECCB
+//------------------------------------------------------------------------------
+ 
+CONST_UINT64_T( PORE_ECCB_CONTROL_REGISTER_0x000C0000 , ULL(0x000C0000) );
+CONST_UINT64_T( PORE_ECCB_STATUS_REGISTER_READ_0x000C0002, ULL(0x000C0002) );
+CONST_UINT64_T( PORE_ECCB_DATA_REGISTER_0x000C0003    , ULL(0x000C0003) );
+ 
+
+//------------------------------------------------------------------------------
 //      PORE-SBE
 //------------------------------------------------------------------------------
 CONST_UINT64_T( PORE_SBE_0x000E0000                   , ULL(0x000E0000) );
@@ -559,24 +627,51 @@ CONST_UINT64_T( PBA_BARMSK3_0x02013F07                , ULL(0x02013F07) );
 CONST_UINT64_T( PBA_TRUSTMODE_0x02013F08              , ULL(0x02013F08) );
 
 //------------------------------------------------------------------------------
+//      PBAX
+//------------------------------------------------------------------------------
+CONST_UINT64_T( PBAXSNDTX_00064020    , ULL(0x00064020) );
+CONST_UINT64_T( PBAXCFG_00064021      , ULL(0x00064021) );
+CONST_UINT64_T( PBAXSHBR0_00064026    , ULL(0x00064026) );
+CONST_UINT64_T( PBAXSHBR1_0006402A    , ULL(0x0006402A) );
+
+//------------------------------------------------------------------------------
 //      PSI
 //------------------------------------------------------------------------------
+CONST_UINT64_T( PSI_TXCSR_0x02010800                  , ULL(0x02010800) );
+CONST_UINT64_T( PSI_RXCSR_0x02010808                  , ULL(0x02010808) );    
+CONST_UINT64_T( PSI_TXCIAR_0x02010810                 , ULL(0x02010810) );    
+CONST_UINT64_T( PSI_TXCMISC_0x02010813                , ULL(0x02010813) );    
+CONST_UINT64_T( PSI_RXCIAR_0x02010818                 , ULL(0x02010818) );    
+CONST_UINT64_T( PSI_RXCMISC_0x0201081B                , ULL(0x0201081B) );
 CONST_UINT64_T( PSI_BRIDGE_BAR_0x0201090A             , ULL(0x0201090A) );
 CONST_UINT64_T( PSI_FSP_BAR_0x0201090B                , ULL(0x0201090B) );
 CONST_UINT64_T( PSI_FSP_MMR_0x0201090C                , ULL(0x0201090C) );
 CONST_UINT64_T( PSI_BRIDGE_STATUS_CTL_0x0201090E      , ULL(0x0201090E) );
+CONST_UINT64_T( PSI_BRIDGE_STATUS_CTL_OR_0x02010912   , ULL(0x02010912) );
+
+CONST_UINT64_T( PSI_NOTRUST_BAR0_0x02013F40           , ULL(0x02013F40) );
+CONST_UINT64_T( PSI_NOTRUST_BAR1_0x02013F41           , ULL(0x02013F41) );
+CONST_UINT64_T( PSI_NOTRUST_BAR0_MASK_0x02013F42      , ULL(0x02013F42) );
+CONST_UINT64_T( PSI_NOTRUST_BAR1_MASK_0x02013F43      , ULL(0x02013F43) );
+
+
+//------------------------------------------------------------------------------
+//      HCA
+//------------------------------------------------------------------------------
+CONST_UINT64_T( HCA_MODE_0x0201094F                   , ULL(0x0201094F) );
 
 //------------------------------------------------------------------------------
 //     INTERRUPT CONTROL PRESENTER  (ICP)
 //------------------------------------------------------------------------------
 CONST_UINT64_T( ICP_BAR_0x020109CA                    , ULL(0x020109CA) );
+CONST_UINT64_T( ICP_SYNC_MODE_REG0_0x020109CB         , ULL(0x020109CB) );
 CONST_UINT64_T( ICP_INTR_INJECT_0x020109CC            , ULL(0x020109CC) );
 
 
 //------------------------------------------------------------------------------
 //      NEST PB EH
 //------------------------------------------------------------------------------
-// registers with multiple physical/shadow copies (all must be configured consistently)
+// registers with multiple physical/shadow copies
 // west
 CONST_UINT64_T( PB_MODE_WEST_0x02010C0A               , ULL(0x02010C0A) );
 CONST_UINT64_T( PB_HP_MODE_NEXT_WEST_0x02010C0B       , ULL(0x02010C0B) );
@@ -587,6 +682,7 @@ CONST_UINT64_T( PB_FLMCFG0_WEST_0x02010C12            , ULL(0x02010C12) );
 CONST_UINT64_T( PB_FLMCFG1_WEST_0x02010C13            , ULL(0x02010C13) );
 CONST_UINT64_T( PB_FRMCFG0_WEST_0x02010C14            , ULL(0x02010C14) );
 CONST_UINT64_T( PB_FRMCFG1_WEST_0x02010C15            , ULL(0x02010C15) );
+CONST_UINT64_T( PB_SCONFIG_LOAD_WEST_0x02010C16       , ULL(0x02010C16) );
 // center
 CONST_UINT64_T( PB_MODE_CENT_0x02010C4A               , ULL(0x02010C4A) );
 CONST_UINT64_T( PB_HP_MODE_NEXT_CENT_0x02010C4B       , ULL(0x02010C4B) );
@@ -597,6 +693,7 @@ CONST_UINT64_T( PB_FLMCFG0_CENT_0x02010C5E            , ULL(0x02010C5E) );
 CONST_UINT64_T( PB_FLMCFG1_CENT_0x02010C5F            , ULL(0x02010C5F) );
 CONST_UINT64_T( PB_FRMCFG0_CENT_0x02010C60            , ULL(0x02010C60) );
 CONST_UINT64_T( PB_FRMCFG1_CENT_0x02010C61            , ULL(0x02010C61) );
+CONST_UINT64_T( PB_SCONFIG_LOAD_CENT_0x02010C6D       , ULL(0x02010C6D) );
 // east
 CONST_UINT64_T( PB_MODE_EAST_0x02010C8A               , ULL(0x02010C8A) );
 CONST_UINT64_T( PB_HP_MODE_NEXT_EAST_0x02010C8B       , ULL(0x02010C8B) );
@@ -607,6 +704,7 @@ CONST_UINT64_T( PB_FLMCFG0_EAST_0x02010C92            , ULL(0x02010C92) );
 CONST_UINT64_T( PB_FLMCFG1_EAST_0x02010C93            , ULL(0x02010C93) );
 CONST_UINT64_T( PB_FRMCFG0_EAST_0x02010C94            , ULL(0x02010C94) );
 CONST_UINT64_T( PB_FRMCFG1_EAST_0x02010C95            , ULL(0x02010C95) );
+CONST_UINT64_T( PB_SCONFIG_LOAD_EAST_0x02010C96       , ULL(0x02010C96) );
 
 // registers without shadow copies
 // center
@@ -625,12 +723,12 @@ CONST_UINT64_T( PB_RGMCFG10_0x02010C5A                , ULL(0x02010C5A) );
 CONST_UINT64_T( PB_RGMCFGM00_0x02010C5B               , ULL(0x02010C5B) );
 CONST_UINT64_T( PB_RGMCFGM01_0x02010C5C               , ULL(0x02010C5C) );
 CONST_UINT64_T( PB_RGMCFGM10_0x02010C5D               , ULL(0x02010C5D) );
-CONST_UINT64_T( PB_GP_CMD_RATE_DP0_0x02010C62         , ULL(0x02010C62) );
-CONST_UINT64_T( PB_GP_CMD_RATE_DP1_0x02010C63         , ULL(0x02010C63) );
-CONST_UINT64_T( PB_RGP_CMD_RATE_DP0_0x02010C64        , ULL(0x02010C64) );
-CONST_UINT64_T( PB_RGP_CMD_RATE_DP1_0x02010C65        , ULL(0x02010C65) );
-CONST_UINT64_T( PB_SP_CMD_RATE_DP0_0x02010C66         , ULL(0x02010C66) );
-CONST_UINT64_T( PB_SP_CMD_RATE_DP1_0x02010C67         , ULL(0x02010C67) );
+CONST_UINT64_T( PB_GP_CMD_RATE_DP_LO_0x02010C62       , ULL(0x02010C62) );
+CONST_UINT64_T( PB_GP_CMD_RATE_DP_HI_0x02010C63       , ULL(0x02010C63) );
+CONST_UINT64_T( PB_RGP_CMD_RATE_DP_LO_0x02010C64      , ULL(0x02010C64) );
+CONST_UINT64_T( PB_RGP_CMD_RATE_DP_HI_0x02010C65      , ULL(0x02010C65) );
+CONST_UINT64_T( PB_SP_CMD_RATE_DP_LO_0x02010C66       , ULL(0x02010C66) );
+CONST_UINT64_T( PB_SP_CMD_RATE_DP_HI_0x02010C67       , ULL(0x02010C67) );
 CONST_UINT64_T( PB_EVENT_TRACE_0x02010C68             , ULL(0x02010C68) );
 CONST_UINT64_T( PB_EVENT_COMPA_0x02010C69             , ULL(0x02010C69) );
 CONST_UINT64_T( PB_EVENT_COMPB_0x02010C6A             , ULL(0x02010C6A) );
@@ -682,9 +780,20 @@ CONST_UINT64_T( PB_RAS_FIR_ACTION1_0x02010C73         , ULL(0x02010C73) );
 CONST_UINT64_T( PB_PLLLOCKREG_0x020F0019              , ULL(0x020F0019) );
 
 //------------------------------------------------------------------------------
+//      CAPP
+//------------------------------------------------------------------------------
+CONST_UINT64_T( CAPP_APC_MASTER_PB_CTL_0x02013018     , ULL(0x02013018) );
+CONST_UINT64_T( CAPP_CXA_SNOOP_CTL_0x0201301B         , ULL(0x0201301B) );
+
+//------------------------------------------------------------------------------
 //      MCS
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MCS_MCFGP_0x02011800                  , ULL(0x02011800) );
+CONST_UINT64_T( MCS_MCFGPM_0x02011801                 , ULL(0x02011801) );
+CONST_UINT64_T( MCS_MCFGPR_0x02011802                 , ULL(0x02011802) );
+CONST_UINT64_T( MCS_MCFGPA_0x02011814                 , ULL(0x02011814) );
+CONST_UINT64_T( MCS_MCFGPMA_0x02011815                , ULL(0x02011815) );
+CONST_UINT64_T( MCS_MCEPS_0x02011816                  , ULL(0x02011816) );
 
 CONST_UINT64_T( MCS_MCIFIR_0x02011840                 , ULL(0x02011840) );
 CONST_UINT64_T( MCS_MCIFIR_AND_0x02011841             , ULL(0x02011841) );
@@ -708,6 +817,7 @@ CONST_UINT64_T( ADU_FORCE_ECC_0x02020010              , ULL(0x02020010) );
 CONST_UINT64_T( ADU_PMISC_MODE_0x0202000B             , ULL(0x0202000B) );
 CONST_UINT64_T( ADU_UNTRUSTED_BAR_0x02020015          , ULL(0x02020015) );
 CONST_UINT64_T( ADU_UNTRUSTED_BAR_MASK_0x02020016     , ULL(0x02020016) );
+CONST_UINT64_T( ADU_TBROM_BAR_0x02020017              , ULL(0x02020017) );
 
 //------------------------------------------------------------------------------
 //      PCIe
@@ -777,10 +887,12 @@ CONST_UINT64_T( NX_NEAR_BAR_F0_0x02013099             , ULL(0x02013099) );
 CONST_UINT64_T( NX_FAR_BAR_F0_0x0201309A              , ULL(0x0201309A) );
 CONST_UINT64_T( NX_NEAR_BAR_F1_0x0201309B             , ULL(0x0201309B) );
 CONST_UINT64_T( NX_FAR_BAR_F1_0x0201309C              , ULL(0x0201309C) );
+CONST_UINT64_T( NX_CQ_EPS_0x0201309D                  , ULL(0x0201309D) );
 
 //------------------------------------------------------------------------------
 //      MCD
 //------------------------------------------------------------------------------
+CONST_UINT64_T( MCD_PRE_EPS_0x0201340B                , ULL(0x0201340B) );
 CONST_UINT64_T( MCD_CN00_0x0201340C                   , ULL(0x0201340C) );
 CONST_UINT64_T( MCD_CN01_0x0201340D                   , ULL(0x0201340D) );
 CONST_UINT64_T( MCD_CN10_0x0201340E                   , ULL(0x0201340E) );
@@ -820,6 +932,18 @@ CONST_UINT64_T( X_TRACE_DATA_HI_T1_0x04010800         , ULL(0x04010800) );
 CONST_UINT64_T( X_TRACE_DATA_LO_T1_0x04010801         , ULL(0x04010801) );
 
 //------------------------------------------------------------------------------
+//      X-BUS PBEN
+//------------------------------------------------------------------------------
+CONST_UINT64_T( PB_X_MODE_0x04010C0A                  , ULL(0x04010C0A) );
+
+//------------------------------------------------------------------------------
+//      X-BUS IOPSI
+//------------------------------------------------------------------------------
+CONST_UINT64_T( X_PSI_RXCNTL_0x04012420               , ULL(0x04012420) );
+CONST_UINT64_T( X_PSI_RXSTATUS_0x04012422             , ULL(0x04012422) );
+CONST_UINT64_T( X_PSI_TXCNTL_0x04012430               , ULL(0x04012430) );
+
+//------------------------------------------------------------------------------
 //      X-BUS CLOCK CONTROL
 //------------------------------------------------------------------------------
 CONST_UINT64_T( X_OPCG_CNTL0_0x04030002               , ULL(0x04030002) );
@@ -879,11 +1003,6 @@ CONST_UINT64_T( X_PLLLOCKREG_0x040F0019               , ULL(0x040F0019) );
 CONST_UINT64_T( X_HANG_P0_XBUS_0x040F0020             , ULL(0x040F0020) );   // XBUS     : setup hang pulse register0
 CONST_UINT64_T( X_HANG_PRE_XBUS_0x040F0028            , ULL(0x040F0028) );   // XBUS     : setup hang precounter (HEX:01)
 
-//------------------------------------------------------------------------------
-//      X-BUS PBEN
-//------------------------------------------------------------------------------
-CONST_UINT64_T( X_PB_MODE_0x04010C0A                  , ULL(0x04010C0A) );
-
 
 /******************************************************************************/
 /******************************  A-BUS CHIPLET  *******************************/
@@ -976,8 +1095,9 @@ CONST_UINT64_T( A_HANG_PRE_0x080F0028                 , ULL(0x080F0028) ); // AB
 //------------------------------------------------------------------------------
 //      A-BUS PBES
 //------------------------------------------------------------------------------
-CONST_UINT64_T( A_PB_MODE_0x0801080A                  , ULL(0x0801080A) );
-
+CONST_UINT64_T( PB_A_MODE_0x0801080A                  , ULL(0x0801080A) );
+CONST_UINT64_T( PB_A_TRACE_0x08010812                 , ULL(0x08010812) );
+CONST_UINT64_T( PB_A_FMR_CFG_0x08010813               , ULL(0x08010813) );
 
 /******************************************************************************/
 /*****************************  PCIE-BUS CHIPLET  *****************************/
@@ -1007,6 +1127,12 @@ CONST_UINT64_T( PCIE_GP0_OR_0x09000005                , ULL(0x09000005) );
 CONST_UINT64_T( PCIE_SCOM_0x09010000                  , ULL(0x09010000) );
 
 //------------------------------------------------------------------------------
+//      PCIE-BUS PB
+//------------------------------------------------------------------------------
+CONST_UINT64_T( PB_F_TRACE_0x09010812                 , ULL(0x09010812) );
+CONST_UINT64_T( PB_F_FMR_CFG_0x09010813               , ULL(0x09010813) );
+
+//------------------------------------------------------------------------------
 //      PCIE-BUS TRACE
 //------------------------------------------------------------------------------
 CONST_UINT64_T( PCIE_TRACE_DATA_HI_0x09010400         , ULL(0x09010400) );
@@ -1020,6 +1146,11 @@ CONST_UINT64_T( PCIE1_ASB_BAR_0x0901240B              , ULL(0x0901240B) );
 CONST_UINT64_T( PCIE2_ASB_BAR_0x0901280B              , ULL(0x0901280B) );
 
 //------------------------------------------------------------------------------
+//      PCIE-BUS PB
+//------------------------------------------------------------------------------
+CONST_UINT64_T( PB_IOF_MODE_0x09011C0A                , ULL(0x09011C0A) );
+
+//------------------------------------------------------------------------------
 //      PCIE-BUS CLOCK CONTROL
 //------------------------------------------------------------------------------
 CONST_UINT64_T( PCIE_OPCG_CNTL0_0x09030002            , ULL(0x09030002) );
@@ -1134,6 +1265,7 @@ CONST_UINT64_T( EX_GP2_0x10000002                     , ULL(0x10000002) );
 //L3
 CONST_UINT64_T( EX_L3_MODE_REG1_0x1001080A            , ULL(0x1001080A) );
 CONST_UINT64_T( EX_L3_MODE_REG0_0x1001082B            , ULL(0x1001082B) );
+CONST_UINT64_T( EX_L3_PRD_PURGE_REG_0x1001080E        , ULL(0x1001080E) );
 //L2
 CONST_UINT64_T( EX_L2_FIR_REG_0x10012800              , ULL(0x10012800) );
 CONST_UINT64_T( EX_L2_CERRS_REG0_0x10012815           , ULL(0x10012815) );
@@ -1238,6 +1370,7 @@ CONST_UINT64_T( EX_OHA_AISS_IO_REG_0x10020014                               , UL
 //------------------------------------------------------------------------------
 //      EX CLOCK CONTROL
 //------------------------------------------------------------------------------
+CONST_UINT64_T( EX_SYNC_CONFIG_0x10030000             , ULL(0x10030000) );
 CONST_UINT64_T( EX_OPCG_CNTL0_0x10030002              , ULL(0x10030002) );
 CONST_UINT64_T( EX_OPCG_CNTL1_0x10030003              , ULL(0x10030003) );
 CONST_UINT64_T( EX_OPCG_CNTL2_0x10030004              , ULL(0x10030004) );
@@ -1249,6 +1382,15 @@ CONST_UINT64_T( EX_CLK_STATUS_0x10030008              , ULL(0x10030008) );
 //------------------------------------------------------------------------------
 //      EX FIR
 //------------------------------------------------------------------------------
+CONST_UINT64_T( EX_CORE_FIR_0x10013100                , ULL(0x10013100) );
+CONST_UINT64_T( EX_CORE_FIR_AND_0x10013101            , ULL(0x10013101) );
+CONST_UINT64_T( EX_CORE_FIR_OR_0x10013102             , ULL(0x10013102) );
+CONST_UINT64_T( EX_CORE_FIR_MASK_0x10013103           , ULL(0x10013103) );
+CONST_UINT64_T( EX_CORE_FIR_MASK_AND_0x10013104       , ULL(0x10013104) );
+CONST_UINT64_T( EX_CORE_FIR_MASK_OR_0x10013105        , ULL(0x10013105) );
+CONST_UINT64_T( EX_CORE_FIR_ACTION0_0x10013106        , ULL(0x10013106) );
+CONST_UINT64_T( EX_CORE_FIR_ACTION1_0x10013107        , ULL(0x10013107) );
+CONST_UINT64_T( EX_CORE_FIR_WOF_0x10013108            , ULL(0x10013108) );
 CONST_UINT64_T( EX_XSTOP_0x10040000                   , ULL(0x10040000) );
 CONST_UINT64_T( EX_RECOV_0x10040001                   , ULL(0x10040001) );
 CONST_UINT64_T( EX_FIR_MASK_0x10040002                , ULL(0x10040002) );
@@ -1360,6 +1502,15 @@ CONST_UINT64_T( EX15_GP3_OR_0x1F0F0014                , ULL(0x1F0F0014) );
 //      EX PCB SLAVE PM
 //------------------------------------------------------------------------------
 //Generic names (need to add in (cuTarget.chipUnitNum * 0x01000000)) when being used
+//Hang counter registers
+CONST_UINT64_T( EX_HANG_P0_0x100F0020                 , ULL(0x100F0020) );
+CONST_UINT64_T( EX_HANG_P1_0x100F0021                 , ULL(0x100F0021) );
+CONST_UINT64_T( EX_HANG_P2_0x100F0022                 , ULL(0x100F0022) );
+CONST_UINT64_T( EX_HANG_P3_0x100F0023                 , ULL(0x100F0023) );
+CONST_UINT64_T( EX_HANG_P4_0x100F0024                 , ULL(0x100F0024) );
+CONST_UINT64_T( EX_HANG_P5_0x100F0025                 , ULL(0x100F0025) );
+CONST_UINT64_T( EX_HANG_P6_0x100F0026                 , ULL(0x100F0026) );
+CONST_UINT64_T( EX_HANG_PRE_0x100F0028                , ULL(0x100F0028) );
 //PMGP0 Register
 CONST_UINT64_T( EX_PMGP0_0x100F0100                   , ULL(0x100F0100) );
 CONST_UINT64_T( EX_PMGP0_AND_0x100F0101               , ULL(0x100F0101) );
@@ -1453,6 +1604,81 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: p8_scom_addresses.H,v $
+Revision 1.105  2012/09/26 17:53:25  jklazyns
+
+Added EX_L3_PRD_PURGE_REG to support L3 purge procedure
+
+Revision 1.104  2012/09/26 15:11:07  jklazyns
+
+Added addresses for Core FIR, Mask, Action, and WOF
+
+Revision 1.103  2012/09/24 03:06:59  jmcgill
+add security switch register, PSI notrust BARs
+
+Revision 1.102  2012/09/21 10:54:18  stillgs
+Clean up old PMC entries
+
+Revision 1.101  2012/09/20 10:43:03  rmaier
+Added TOD_FSM_REG_00040024
+
+Revision 1.100  2012/09/15 21:26:14  jmcgill
+add cfam addresses for mailbox scratch registers
+
+Revision 1.99  2012/09/13 20:27:35  mfred
+Added some multicast group 1 addresses to the file.
+
+Revision 1.98  2012/09/13 19:54:41  mfred
+Move group 1 (ex chiplet) multicast group definitions to this file.
+
+Revision 1.97  2012/09/12 17:19:36  jmcgill
+add LPC SCOM registers
+
+Revision 1.96  2012/09/11 14:20:23  szhong
+added: SBE VITAL REG
+       I2C MASTER (MODE)
+       PORE_ECCB CONTROL REG
+       PORE_ECCB STATUS REG
+       PORE_ECCB DATA REG
+
+Revision 1.95  2012/09/04 15:40:09  jimyac
+added OCC LFIR registers
+
+Revision 1.94  2012/08/28 07:56:27  pchatnah
+updating
+
+Revision 1.93  2012/08/26 01:54:37  jmcgill
+add EX hang pulse register definitions
+
+Revision 1.92  2012/08/21 03:30:37  jmcgill
+add A/F link framer config registers
+
+Revision 1.91  2012/08/20 19:25:19  jmcgill
+add entry from ADU TBROM BAR
+
+Revision 1.90  2012/08/15 15:03:12  jmcgill
+add PB A/F link trace register addresses
+
+Revision 1.89  2012/08/11 22:21:04  jmcgill
+add addresses for proc_build_smp procedure
+
+Revision 1.88  2012/08/08 14:25:13  kgungl
+pbax updates
+
+Revision 1.87  2012/08/08 13:18:30  stillgs
+Added PMC monitoring registers
+
+Revision 1.86  2012/08/08 11:32:16  pchatnah
+updating register address for vsafe mode
+
+Revision 1.85  2012/08/06 18:35:34  karm
+added EX_SYNC_CONFIG
+
+Revision 1.84  2012/07/30 15:34:53  bellows
+Updates for set up bars
+
+Revision 1.83  2012/07/23 14:42:39  jmcgill
+add addresses needed proc_psi_init
+
 Revision 1.82  2012/06/27 07:43:32  rkoester
 add remaining PLLLOCK register
 
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 29c4ab3b6..8e1d253d3 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -608,6 +608,7 @@
     <attribute><id>EFF_NUM_DIES_PER_PACKAGE</id></attribute>
     <attribute><id>MSS_SPARE_BYTE</id></attribute>
     <attribute><id>MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id></attribute>
+    <attribute><id>MSS_CAL_STEP_ENABLE</id></attribute>
 </targetType>
 
 <targetType>