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| author | LiuYangFan <shliuyf@cn.ibm.com> | 2016-11-14 13:35:09 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-12-05 12:14:06 -0500 |
| commit | a760376b03f184565c02e8b11b1b8e1ad4900d71 (patch) | |
| tree | ac29d654de8fdc4ddde80f28f86f8279c503fba1 /src | |
| parent | 95806adfbe2bd8a83772e22b4df3fde3fc14a0bb (diff) | |
| download | talos-hostboot-a760376b03f184565c02e8b11b1b8e1ad4900d71.tar.gz talos-hostboot-a760376b03f184565c02e8b11b1b8e1ad4900d71.zip | |
Update p9_clkoff_getreg/p9_ram_core procedures
1.update p9_clkoff_getreg FPSCR FEX/VX bit calc
2.fix p9_clkoff_getreg using ptid/vtid for getspy
3.update p9_clkoff_getreg special cases DSCR/PIR
4.fix p9_spr_name_map for some SPR share type
5.fix p9_ram_core put FPSCR issue
Change-Id: I54c13977898ac60c20fbf7a1ee3c15787466c776
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32604
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32690
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C | 9 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H | 10 |
2 files changed, 11 insertions, 8 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C index bea2cba06..75d1dae07 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C @@ -92,7 +92,7 @@ const uint32_t OPCODE_STXVD2X = 0x7C000798; const uint32_t OPCODE_MFMSR_TO_GPR0 = 0x7C0000A6; const uint32_t OPCODE_MFOCRF_TO_GPR0 = 0x7C100026; const uint32_t OPCODE_MTOCRF_FROM_GPR0 = 0x7C100120; -const uint32_t OPCODE_MTFSF_FROM_GPR0 = 0xFE00058E; +const uint32_t OPCODE_MTFSF_FROM_FPR0 = 0xFE00058E; const uint32_t OPCODE_MFVSCR_TO_VR0 = 0x10000604; const uint32_t OPCODE_MTVSCR_FROM_VR0 = 0x10000644; @@ -882,14 +882,17 @@ fapi2::ReturnCode RamCore::put_reg(const Enum_RegType i_type, const uint32_t i_r FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_fpr0)); - //2.put SPR value into GPR0 + //2.put SPR value into FPR0 FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; FAPI_TRY(ram_opcode(l_opcode, true)); + l_opcode = OPCODE_MTFPRD_FROM_GPR0_TO_FPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + //3.create mtfsf opcode, ram into thread - l_opcode = OPCODE_MTFSF_FROM_GPR0; + l_opcode = OPCODE_MTFSF_FROM_FPR0; FAPI_TRY(ram_opcode(l_opcode, true)); //4.restore FPR0 diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H index d6420147f..3d32c8796 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H @@ -99,9 +99,9 @@ typedef std::map<std::string, SPRMapEntry>::iterator SPR_MAP_IT; _op_(DSCR ,17 , ECP.LS.LSPRQX_DSCR<??T> ,FLAG_READ_WRITE ,SPR_PER_PT ,25)\ _op_(DSISR ,18 , ECP.LS.T<??T>_DSISR ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ _op_(DAR ,19 , ECP.LS.T<??T>_DAR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ - _op_(DEC ,22 , EXP.EC.CC.PCC<??C>.V<??T>_DEC ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(DEC ,22 , EXP.EC.CC.PCC<??C>.V<??T>_DEC ,FLAG_READ_WRITE ,SPR_PER_VT ,32)\ _op_(SDR1 ,25 , ECP.LS.V<??T>_SDR1_MASTER ,FLAG_READ_WRITE ,SPR_PER_VT ,64)\ - _op_(SRR0 ,26 , ECP.IFU.T<??T>_SRR0 ,FLAG_READ_WRITE ,SPR_PER_LPAR_VT ,64)\ + _op_(SRR0 ,26 , ECP.IFU.T<??T>_SRR0 ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ _op_(SRR1 ,27 , ECP.SD.T<??T>_SRR1 ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ _op_(CFAR ,28 , ECP.IFU.T<??T>_CFAR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ _op_(AMR ,29 , ECP.LS.T<??T>_AMR_MASTER ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ @@ -111,9 +111,9 @@ typedef std::map<std::string, SPRMapEntry>::iterator SPR_MAP_IT; _op_(TFIAR ,129 , ECP.IFU.T<??T>_TFIAR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ _op_(TEXASR ,130 , ECP.SD.T<??T>_TEXASR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ _op_(TEXASRU ,131 , ECP.SD.T<??T>_TEXASR ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ - _op_(CTRL_RU ,136 , EXP.EC.CC.PCC<??C>.COMMON.SPR_COMMON.CTRL ,FLAG_READ_ONLY ,SPR_PER_PT ,32)\ - _op_(TIDR ,144 , ECP.LS.T<??T>_TIDR ,FLAG_READ_WRITE ,SPR_SHARED ,64)\ - _op_(CTRL ,152 , EXP.EC.CC.PCC<??C>.COMMON.SPR_COMMON.CTRL ,FLAG_WRITE_ONLY ,SPR_PER_PT ,32)\ + _op_(CTRL_RU ,136 , EXP.EC.CC.PCC<??C>.COMMON.SPR_COMMON.CTRL ,FLAG_READ_ONLY ,SPR_SHARED ,32)\ + _op_(TIDR ,144 , ECP.LS.T<??T>_TIDR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(CTRL ,152 , EXP.EC.CC.PCC<??C>.COMMON.SPR_COMMON.CTRL ,FLAG_WRITE_ONLY ,SPR_SHARED ,32)\ _op_(FSCR ,153 , ECP.SD.T<??T>_FSCR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ _op_(UAMOR ,157 , ECP.LS.T<??T>_UAMOR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ _op_(GSR ,158 , N/A ,FLAG_READ_WRITE ,SPR_SHARE_NA ,64)\ |
