Add support for phy ac boost

Change-Id: I05b7826d8d4831d67b45a9d26302f1345797ca0f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27826
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27827
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

7 files changed, 620 insertions, 451 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index 08fb8b523..9054fe27f 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -20572,7 +20572,7 @@ fapi_try_exit:
 /// or redefined. Does not
 /// reset.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_0_version_layout(uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mr_0_version_layout(uint8_t& o_value)
 {
 
     FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_0_VERSION_LAYOUT, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
@@ -20593,7 +20593,7 @@ fapi_try_exit:
 /// layout version. Resets when layout version number
 /// increments.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_1_version_data(uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mr_1_version_data(uint8_t& o_value)
 {
 
     FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_1_VERSION_DATA, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
@@ -20613,7 +20613,7 @@ fapi_try_exit:
 /// @note  Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of
 /// data.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_2_signature_hash(uint32_t& o_value)
+inline fapi2::ReturnCode vpd_mr_2_signature_hash(uint32_t& o_value)
 {
 
     FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_2_SIGNATURE_HASH, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
@@ -20635,7 +20635,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -20661,7 +20661,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -20688,7 +20688,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -20719,7 +20719,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -20745,7 +20745,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -20772,7 +20772,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -20803,7 +20803,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -20829,7 +20829,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -20856,7 +20856,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -20887,7 +20887,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -20913,7 +20913,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -20940,7 +20940,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -20971,7 +20971,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -20997,7 +20997,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21024,7 +21024,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -21055,7 +21055,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21081,7 +21081,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21108,7 +21108,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -21139,7 +21139,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21165,7 +21165,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21192,7 +21192,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -21223,7 +21223,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21249,7 +21249,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21276,7 +21276,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -21307,7 +21307,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21333,7 +21333,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21360,7 +21360,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -21391,7 +21391,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21417,7 +21417,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21444,7 +21444,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -21475,7 +21475,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21501,7 +21501,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21528,7 +21528,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -21559,7 +21559,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21585,7 +21585,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21612,7 +21612,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -21643,7 +21643,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21669,7 +21669,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21696,7 +21696,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -21727,7 +21727,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21753,7 +21753,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21780,7 +21780,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -21811,7 +21811,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21837,7 +21837,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21864,7 +21864,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -21895,7 +21895,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21921,7 +21921,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -21948,7 +21948,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -21979,7 +21979,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22005,7 +22005,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22032,7 +22032,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -22063,7 +22063,7 @@ fapi_try_exit:
 /// cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22089,7 +22089,7 @@ fapi_try_exit:
 /// cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22116,7 +22116,7 @@ fapi_try_exit:
 /// cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -22147,7 +22147,7 @@ fapi_try_exit:
 /// cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22173,7 +22173,7 @@ fapi_try_exit:
 /// cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22200,7 +22200,7 @@ fapi_try_exit:
 /// cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -22231,7 +22231,7 @@ fapi_try_exit:
 /// Ticks are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22257,7 +22257,7 @@ fapi_try_exit:
 /// Ticks are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22284,7 +22284,7 @@ fapi_try_exit:
 /// Ticks are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -22315,7 +22315,7 @@ fapi_try_exit:
 /// Ticks are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22341,7 +22341,7 @@ fapi_try_exit:
 /// Ticks are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22368,7 +22368,7 @@ fapi_try_exit:
 /// Ticks are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -22399,7 +22399,7 @@ fapi_try_exit:
 /// Ticks are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22425,7 +22425,7 @@ fapi_try_exit:
 /// Ticks are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22452,7 +22452,7 @@ fapi_try_exit:
 /// Ticks are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -22483,7 +22483,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d0_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22509,7 +22509,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d0_clk0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22536,7 +22536,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d0_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -22567,7 +22567,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d0_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22593,7 +22593,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d0_clk1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22620,7 +22620,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d0_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -22651,7 +22651,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d1_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22677,7 +22677,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d1_clk0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22704,7 +22704,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d1_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -22735,7 +22735,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d1_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22761,7 +22761,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d1_clk1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22788,7 +22788,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d1_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -22819,7 +22819,7 @@ fapi_try_exit:
 /// cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22845,7 +22845,7 @@ fapi_try_exit:
 /// cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -22872,7 +22872,7 @@ fapi_try_exit:
 /// cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -22903,8 +22903,8 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_MCA>&
-        i_target, uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+        uint8_t& o_value)
 {
     uint8_t l_value[2];
 
@@ -22929,8 +22929,8 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&
-        i_target, uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
@@ -22956,8 +22956,8 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_MCS>&
-        i_target, uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+        uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -22987,8 +22987,8 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_MCA>&
-        i_target, uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+        uint8_t& o_value)
 {
     uint8_t l_value[2];
 
@@ -23013,8 +23013,8 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&
-        i_target, uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
@@ -23040,8 +23040,8 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_MCS>&
-        i_target, uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+        uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -23071,7 +23071,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23097,8 +23097,8 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&
-        i_target, uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
@@ -23124,7 +23124,7 @@ fapi_try_exit:
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23155,7 +23155,7 @@ fapi_try_exit:
 /// of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23181,7 +23181,7 @@ fapi_try_exit:
 /// of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23208,7 +23208,7 @@ fapi_try_exit:
 /// of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23239,7 +23239,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23265,7 +23265,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23292,7 +23292,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23323,7 +23323,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23349,7 +23349,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23376,7 +23376,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23407,7 +23407,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23433,7 +23433,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23460,7 +23460,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23491,7 +23491,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23517,7 +23517,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23544,7 +23544,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23575,7 +23575,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23601,7 +23601,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23628,7 +23628,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23659,7 +23659,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23685,7 +23685,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23712,7 +23712,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23743,7 +23743,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23769,7 +23769,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23796,7 +23796,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23827,7 +23827,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23853,7 +23853,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23880,7 +23880,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23911,7 +23911,7 @@ fapi_try_exit:
 /// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23937,7 +23937,7 @@ fapi_try_exit:
 /// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -23964,7 +23964,7 @@ fapi_try_exit:
 /// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23995,7 +23995,7 @@ fapi_try_exit:
 /// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -24021,7 +24021,7 @@ fapi_try_exit:
 /// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -24048,7 +24048,7 @@ fapi_try_exit:
 /// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24079,7 +24079,7 @@ fapi_try_exit:
 /// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -24105,7 +24105,7 @@ fapi_try_exit:
 /// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -24132,7 +24132,7 @@ fapi_try_exit:
 /// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24163,7 +24163,7 @@ fapi_try_exit:
 /// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -24189,7 +24189,7 @@ fapi_try_exit:
 /// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -24216,7 +24216,7 @@ fapi_try_exit:
 /// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24246,7 +24246,7 @@ fapi_try_exit:
 /// @note  Default value for 2N Mode from Signal
 /// Integrity.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -24271,7 +24271,7 @@ fapi_try_exit:
 /// @note  Default value for 2N Mode from Signal
 /// Integrity.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -24297,7 +24297,7 @@ fapi_try_exit:
 /// @note  Default value for 2N Mode from Signal
 /// Integrity.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24328,7 +24328,7 @@ fapi_try_exit:
 /// or redefined. Does not
 /// reset.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_0_version_layout(uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mt_0_version_layout(uint8_t& o_value)
 {
 
     FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_0_VERSION_LAYOUT, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
@@ -24349,7 +24349,7 @@ fapi_try_exit:
 /// layout version. Resets when layout version number
 /// increments.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_1_version_data(uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mt_1_version_data(uint8_t& o_value)
 {
 
     FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_1_VERSION_DATA, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
@@ -24369,7 +24369,7 @@ fapi_try_exit:
 /// @note  Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of
 /// data.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_2_signature_hash(uint32_t& o_value)
+inline fapi2::ReturnCode vpd_mt_2_signature_hash(uint32_t& o_value)
 {
 
     FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_2_SIGNATURE_HASH, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
@@ -24390,8 +24390,7 @@ fapi_try_exit:
 /// @note  Register Clock Driver, Input Bus Termination in tens of
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dimm_rcd_ibt(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
-        uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
 {
     uint8_t l_value[2][2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
@@ -24416,8 +24415,7 @@ fapi_try_exit:
 /// @note  Register Clock Driver, Input Bus Termination in tens of
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dimm_rcd_ibt(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
-        uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -24447,8 +24445,7 @@ fapi_try_exit:
 /// @note  Register Clock Driver, Input Bus Termination in tens of
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dimm_rcd_ibt(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-        uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -24477,7 +24474,7 @@ fapi_try_exit:
 /// @note  DQ and DQS Drive Impedance for
 /// [Port][DIMM][RANK].
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24509,7 +24506,7 @@ fapi_try_exit:
 /// @note  DQ and DQS Drive Impedance for
 /// [Port][DIMM][RANK].
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24540,7 +24537,7 @@ fapi_try_exit:
 /// @note  DQ and DQS Drive Impedance for
 /// [Port][DIMM][RANK].
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24570,8 +24567,7 @@ fapi_try_exit:
 /// @note  DRAM side Nominal Termination Resistance in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
-        uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -24602,8 +24598,7 @@ fapi_try_exit:
 /// @note  DRAM side Nominal Termination Resistance in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
-        uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -24633,8 +24628,7 @@ fapi_try_exit:
 /// @note  DRAM side Nominal Termination Resistance in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-        uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -24663,8 +24657,7 @@ fapi_try_exit:
 /// @note  DRAM side Park Termination Resistance in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_rtt_park(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
-        uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -24695,8 +24688,7 @@ fapi_try_exit:
 /// @note  DRAM side Park Termination Resistance in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_rtt_park(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
-        uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -24726,8 +24718,7 @@ fapi_try_exit:
 /// @note  DRAM side Park Termination Resistance in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_rtt_park(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-        uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -24756,8 +24747,7 @@ fapi_try_exit:
 /// @note  DRAM side Write Termination Resistance in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
-        uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -24788,7 +24778,7 @@ fapi_try_exit:
 /// @note  DRAM side Write Termination Resistance in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -24818,7 +24808,7 @@ fapi_try_exit:
 /// @note  DRAM side Write Termination Resistance in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -24853,7 +24843,7 @@ fapi_try_exit:
 /// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits
 /// 8-15)
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint32_t& o_value)
 {
     uint32_t l_value[2];
@@ -24884,7 +24874,7 @@ fapi_try_exit:
 /// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits
 /// 8-15)
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint32_t& o_value)
 {
     uint32_t l_value[2];
@@ -24916,7 +24906,7 @@ fapi_try_exit:
 /// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits
 /// 8-15)
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint32_t* o_array)
 {
     if (o_array == nullptr)
@@ -24952,7 +24942,7 @@ fapi_try_exit:
 /// 8-15) Bit 24-26 = DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits
 /// 8-15)
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint32_t& o_value)
 {
     uint32_t l_value[2];
@@ -24983,7 +24973,7 @@ fapi_try_exit:
 /// 8-15) Bit 24-26 = DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits
 /// 8-15)
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint32_t& o_value)
 {
     uint32_t l_value[2];
@@ -25015,7 +25005,7 @@ fapi_try_exit:
 /// 8-15) Bit 24-26 = DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits
 /// 8-15)
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint32_t* o_array)
 {
     if (o_array == nullptr)
@@ -25051,7 +25041,7 @@ fapi_try_exit:
 /// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits
 /// 8-15)
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint32_t& o_value)
 {
     uint32_t l_value[2];
@@ -25082,7 +25072,7 @@ fapi_try_exit:
 /// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits
 /// 8-15)
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint32_t& o_value)
 {
     uint32_t l_value[2];
@@ -25114,7 +25104,7 @@ fapi_try_exit:
 /// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits
 /// 8-15)
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint32_t* o_array)
 {
     if (o_array == nullptr)
@@ -25154,8 +25144,7 @@ fapi_try_exit:
 /// 3 Nibble 2 Bit 14-15 = DP16 Block 1 Nibble 3 Bit 30-31 = DP16 Block 3 Nibble
 /// 3
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_ctle_cap(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
-        uint64_t& o_value)
+inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_cap(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint64_t& o_value)
 {
     uint64_t l_value[2];
 
@@ -25188,7 +25177,7 @@ fapi_try_exit:
 /// 3 Nibble 2 Bit 14-15 = DP16 Block 1 Nibble 3 Bit 30-31 = DP16 Block 3 Nibble
 /// 3
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_ctle_cap(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_cap(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint64_t& o_value)
 {
     uint64_t l_value[2];
@@ -25223,8 +25212,7 @@ fapi_try_exit:
 /// 3 Nibble 2 Bit 14-15 = DP16 Block 1 Nibble 3 Bit 30-31 = DP16 Block 3 Nibble
 /// 3
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_ctle_cap(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-        uint64_t* o_array)
+inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_cap(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint64_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -25263,8 +25251,7 @@ fapi_try_exit:
 /// Nibble 2 Bit 21-23 = DP16 Block 1 Nibble 3 Bit 45-47 = DP16 Block 3 Nibble
 /// 3
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_ctle_res(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
-        uint64_t& o_value)
+inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_res(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint64_t& o_value)
 {
     uint64_t l_value[2];
 
@@ -25297,7 +25284,7 @@ fapi_try_exit:
 /// Nibble 2 Bit 21-23 = DP16 Block 1 Nibble 3 Bit 45-47 = DP16 Block 3 Nibble
 /// 3
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_ctle_res(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_res(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint64_t& o_value)
 {
     uint64_t l_value[2];
@@ -25332,8 +25319,7 @@ fapi_try_exit:
 /// Nibble 2 Bit 21-23 = DP16 Block 1 Nibble 3 Bit 45-47 = DP16 Block 3 Nibble
 /// 3
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_ctle_res(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-        uint64_t* o_array)
+inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_res(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint64_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -25362,8 +25348,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Drive Impedance for Address Lines in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_addr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
-        uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_addr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
 {
     uint8_t l_value[2];
 
@@ -25387,7 +25372,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Drive Impedance for Address Lines in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_addr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_addr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -25412,8 +25397,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Drive Impedance for Address Lines in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_addr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-        uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_addr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -25442,8 +25426,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Drive Impedance for Clock in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
-        uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
 {
     uint8_t l_value[2];
 
@@ -25466,8 +25449,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Drive Impedance for Clock in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
-        uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
@@ -25491,8 +25473,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Drive Impedance for Clock in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-        uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -25521,8 +25502,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Drive Impedance for Control Lines in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
-        uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
 {
     uint8_t l_value[2];
 
@@ -25546,7 +25526,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Drive Impedance for Control Lines in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -25571,8 +25551,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Drive Impedance for Control Lines in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-        uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -25601,7 +25580,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Drive Impedance for Data and Data Strobe Lines in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -25626,7 +25605,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Drive Impedance for Data and Data Strobe Lines in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -25651,7 +25630,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Drive Impedance for Data and Data Strobe Lines in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -25681,7 +25660,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Drive Impedance for Clock Enable Spare Line in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_spcke(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_spcke(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -25706,7 +25685,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Drive Impedance for Clock Enable Spare Line in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_spcke(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_spcke(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -25731,7 +25710,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Drive Impedance for Clock Enable Spare Line in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_spcke(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_spcke(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -25761,7 +25740,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Receiver Impedance for Data and Data Strobe Lines in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -25786,7 +25765,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Receiver Impedance for Data and Data Strobe Lines in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
@@ -25811,7 +25790,7 @@ fapi_try_exit:
 /// @note  Memory Controller side Receiver Impedance for Data and Data Strobe Lines in
 /// Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -25841,7 +25820,7 @@ fapi_try_exit:
 /// @note  READ, On Die Termination triggering
 /// bitmap.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -25872,7 +25851,7 @@ fapi_try_exit:
 /// @note  READ, On Die Termination triggering
 /// bitmap.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -25902,7 +25881,7 @@ fapi_try_exit:
 /// @note  READ, On Die Termination triggering
 /// bitmap.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -25931,7 +25910,7 @@ fapi_try_exit:
 /// @note  WRITE, On Die Termination triggering
 /// bitmap.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -25962,7 +25941,7 @@ fapi_try_exit:
 /// @note  WRITE, On Die Termination triggering
 /// bitmap.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -25992,7 +25971,7 @@ fapi_try_exit:
 /// @note  WRITE, On Die Termination triggering
 /// bitmap.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -26022,8 +26001,7 @@ fapi_try_exit:
 /// Bit 1 is the Range. Bits 2-7 is the Value. Refer to the VrefDQ Training Table in
 /// JEDEC.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_vref_dram_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
-        uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mt_vref_dram_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
 {
     uint8_t l_value[2];
 
@@ -26047,8 +26025,7 @@ fapi_try_exit:
 /// Bit 1 is the Range. Bits 2-7 is the Value. Refer to the VrefDQ Training Table in
 /// JEDEC.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_vref_dram_wr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
-        uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mt_vref_dram_wr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
@@ -26073,8 +26050,7 @@ fapi_try_exit:
 /// Bit 1 is the Range. Bits 2-7 is the Value. Refer to the VrefDQ Training Table in
 /// JEDEC.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_vref_dram_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-        uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mt_vref_dram_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -26104,7 +26080,7 @@ fapi_try_exit:
 /// of
 /// Vdd
 ///
-inline fapi2::ReturnCode mss_vpd_mt_vref_mc_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint32_t& o_value)
+inline fapi2::ReturnCode vpd_mt_vref_mc_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint32_t& o_value)
 {
     uint32_t l_value[2];
 
@@ -26128,8 +26104,7 @@ fapi_try_exit:
 /// of
 /// Vdd
 ///
-inline fapi2::ReturnCode mss_vpd_mt_vref_mc_rd(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
-        uint32_t& o_value)
+inline fapi2::ReturnCode vpd_mt_vref_mc_rd(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint32_t& o_value)
 {
     uint32_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
@@ -26154,7 +26129,7 @@ fapi_try_exit:
 /// of
 /// Vdd
 ///
-inline fapi2::ReturnCode mss_vpd_mt_vref_mc_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint32_t* o_array)
+inline fapi2::ReturnCode vpd_mt_vref_mc_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint32_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -26186,8 +26161,7 @@ fapi_try_exit:
 /// enabled, disable periodic rd_ctr in draminit_mc.
 /// Default
 ///
-inline fapi2::ReturnCode mss_vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
-        uint16_t& o_value)
+inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint16_t& o_value)
 {
     uint16_t l_value[2];
 
@@ -26213,7 +26187,7 @@ fapi_try_exit:
 /// enabled, disable periodic rd_ctr in draminit_mc.
 /// Default
 ///
-inline fapi2::ReturnCode mss_vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint16_t& o_value)
 {
     uint16_t l_value[2];
@@ -26241,8 +26215,7 @@ fapi_try_exit:
 /// enabled, disable periodic rd_ctr in draminit_mc.
 /// Default
 ///
-inline fapi2::ReturnCode mss_vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-        uint16_t* o_array)
+inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint16_t* o_array)
 {
     if (o_array == nullptr)
     {
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H
index ddee22377..db3f2a30a 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H
@@ -44,7 +44,7 @@ namespace decoder
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  MR Keyword Layout Version Number.  Increases when attributes are added, removed, or redefined.  Does not reset.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_0_version_layout(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
+inline fapi2::ReturnCode vpd_mr_0_version_layout(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value;
@@ -64,7 +64,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  MR Keyword Data Version Number.  Increases when data changes with the above layout version.  Resets when layout version number increments.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_1_version_data(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
+inline fapi2::ReturnCode vpd_mr_1_version_data(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value;
@@ -84,7 +84,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of data.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_2_signature_hash(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
+inline fapi2::ReturnCode vpd_mr_2_signature_hash(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
         const uint8_t* i_blob)
 {
     uint32_t l_value;
@@ -105,7 +105,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -125,7 +125,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -145,7 +145,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -165,7 +165,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -185,7 +185,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -205,7 +205,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -225,7 +225,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -245,7 +245,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -265,7 +265,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -285,7 +285,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -305,7 +305,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -325,7 +325,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -345,7 +345,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -365,7 +365,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -385,7 +385,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -405,7 +405,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Bank Address of BA# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -425,7 +425,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Bank Address of BA# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -445,7 +445,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Bank Group of BG# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -465,7 +465,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Bank Group of BA# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -485,7 +485,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -505,7 +505,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -525,7 +525,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -545,7 +545,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d0_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -565,7 +565,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d0_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -585,7 +585,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d1_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -605,7 +605,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_d1_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -625,7 +625,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -645,8 +645,8 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_MCS>&
-        i_target, const uint8_t* i_blob)
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+        const uint8_t* i_blob)
 {
     uint8_t l_value[2];
 
@@ -665,8 +665,8 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_MCS>&
-        i_target, const uint8_t* i_blob)
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+        const uint8_t* i_blob)
 {
     uint8_t l_value[2];
 
@@ -685,7 +685,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -705,7 +705,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -725,7 +725,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -745,7 +745,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -765,7 +765,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -785,7 +785,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -805,7 +805,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -825,7 +825,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -845,7 +845,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -865,7 +865,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -885,7 +885,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -905,7 +905,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -925,7 +925,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -945,7 +945,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -965,7 +965,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Default value for 2N Mode from Signal Integrity.
 ///
-inline fapi2::ReturnCode mss_vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -987,7 +987,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  MT Keyword Layout Version Number.  Increases when attributes are added, removed, or redefined.  Does not reset.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_0_version_layout(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
+inline fapi2::ReturnCode vpd_mt_0_version_layout(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value;
@@ -1007,7 +1007,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  MT Keyword Data Version Number.  Increases when data changes with the above layout version.  Resets when layout version number increments.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_1_version_data(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
+inline fapi2::ReturnCode vpd_mt_1_version_data(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value;
@@ -1027,7 +1027,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of data.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_2_signature_hash(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
+inline fapi2::ReturnCode vpd_mt_2_signature_hash(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
         const uint8_t* i_blob)
 {
     uint32_t l_value;
@@ -1048,7 +1048,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Register Clock Driver, Input Bus Termination in tens of Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dimm_rcd_ibt(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2][2];
@@ -1068,7 +1068,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  DQ and DQS Drive Impedance for [Port][DIMM][RANK].
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2][2][2];
@@ -1088,7 +1088,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  DRAM side Nominal Termination Resistance in Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2][2][2];
@@ -1108,7 +1108,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  DRAM side Park Termination Resistance in Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_rtt_park(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2][2][2];
@@ -1128,7 +1128,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  DRAM side Write Termination Resistance in Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2][2][2];
@@ -1158,7 +1158,7 @@ fapi_try_exit:
 /// Bit 24-26 = DP16 Block 4 (DQ Bits 0-7)
 /// Bit 27-29 = DP16 Block 4 (DQ Bits 8-15)
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint32_t l_value[2];
@@ -1194,7 +1194,7 @@ fapi_try_exit:
 /// Bit 24-26 = DP16 Block 4 (DQ Bits 0-7)
 /// Bit 27-29 = DP16 Block 4 (DQ Bits 8-15)
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint32_t l_value[2];
@@ -1230,7 +1230,7 @@ fapi_try_exit:
 /// Bit 24-26 = DP16 Block 4 (DQ Bits 0-7)
 /// Bit 27-29 = DP16 Block 4 (DQ Bits 8-15)
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint32_t l_value[2];
@@ -1264,7 +1264,7 @@ fapi_try_exit:
 /// Bit 12-13 = DP16 Block 1 Nibble 2     Bit 28-29 = DP16 Block 3 Nibble 2
 /// Bit 14-15 = DP16 Block 1 Nibble 3     Bit 30-31 = DP16 Block 3 Nibble 3
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_ctle_cap(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_cap(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint64_t l_value[2];
@@ -1298,7 +1298,7 @@ fapi_try_exit:
 /// Bit 18-20 = DP16 Block 1 Nibble 2     Bit 42-44 = DP16 Block 3 Nibble 2
 /// Bit 21-23 = DP16 Block 1 Nibble 3     Bit 45-47 = DP16 Block 3 Nibble 3
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_dq_ctle_res(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_res(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint64_t l_value[2];
@@ -1324,7 +1324,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Memory Controller side Drive Impedance for Address Lines in Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_addr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_addr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -1344,7 +1344,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Memory Controller side Drive Impedance for Clock in Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -1364,7 +1364,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Memory Controller side Drive Impedance for Control Lines in Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -1384,7 +1384,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Memory Controller side Drive Impedance for Data and Data Strobe Lines in Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -1404,7 +1404,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Memory Controller side Drive Impedance for Clock Enable Spare Line in Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_drv_imp_spcke(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_drv_imp_spcke(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -1424,7 +1424,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Memory Controller side Receiver Impedance for Data and Data Strobe Lines in Ohms.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -1444,7 +1444,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  READ, On Die Termination triggering bitmap.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
+inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
 {
     uint8_t l_value[2][2][2];
 
@@ -1463,7 +1463,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  WRITE, On Die Termination triggering bitmap.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
+inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
 {
     uint8_t l_value[2][2][2];
 
@@ -1482,7 +1482,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  DRAM side Write Vref setting for DDR4. Bit encode is 01234567. Bit 0 is unused. Bit 1 is the Range. Bits 2-7 is the Value. Refer to the VrefDQ Training Table in JEDEC.
 ///
-inline fapi2::ReturnCode mss_vpd_mt_vref_dram_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_vref_dram_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value[2];
@@ -1502,8 +1502,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Memory Controller side Read Vref setting. Dividing by 1000 gives you percentage of Vdd
 ///
-inline fapi2::ReturnCode mss_vpd_mt_vref_mc_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-        const uint8_t* i_blob)
+inline fapi2::ReturnCode vpd_mt_vref_mc_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
 {
     uint32_t l_value[2];
 
@@ -1528,7 +1527,7 @@ fapi_try_exit:
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Derived from calibration/characterization of read centering. Number of windage offset in units of pico-seconds[ps] with sign bit0 (0b0=positive, 0b1=negative) and value in bits1..31, so 0x8023 for example would mean "-35ps". If this is enabled, disable periodic rd_ctr in draminit_mc. Default
 ///
-inline fapi2::ReturnCode mss_vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint16_t l_value[2];
@@ -1560,77 +1559,77 @@ fapi_try_exit:
 inline fapi2::ReturnCode eff_decode(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_mt_blob,
                                     const uint8_t* i_mr_blob)
 {
-    FAPI_TRY (decoder::mss_vpd_mr_0_version_layout(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_1_version_data(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_2_signature_hash(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_a00(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_a01(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_a02(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_a03(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_a04(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_a05(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_a06(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_a07(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_a08(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_a09(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_a10(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_a11(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_a12(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_a13(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_a17(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_ba0(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_ba1(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_bg0(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_bg1(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_c0(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_c1(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_addr_c2(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_d0_clk0(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_d0_clk1(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_d1_clk0(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_d1_clk1(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cmd_actn(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cmd_addr_casn_a15(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cmd_addr_wen_a14(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cmd_par(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cntl_d0_cke0(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cntl_d0_cke1(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cntl_d1_cke0(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cntl_d1_cke1(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cntl_d0_csn0(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cntl_d0_csn1(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cntl_d1_csn0(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cntl_d1_csn1(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cntl_d0_odt0(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cntl_d0_odt1(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cntl_d1_odt0(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_phase_rot_cntl_d1_odt1(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mr_mc_2n_mode_autoset(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_0_version_layout(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_1_version_data(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_2_signature_hash(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_dimm_rcd_ibt(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_dram_drv_imp_dq_dqs(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_dram_rtt_nom(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_dram_rtt_park(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_dram_rtt_wr(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_mc_dq_acboost_rd_up(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_mc_dq_acboost_wr_down(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_mc_dq_acboost_wr_up(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_mc_dq_ctle_cap(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_mc_dq_ctle_res(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_mc_drv_imp_addr(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_mc_drv_imp_clk(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_mc_drv_imp_cntl(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_mc_drv_imp_dq_dqs(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_mc_drv_imp_spcke(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_mc_rcv_imp_dq_dqs(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_odt_rd(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_odt_wr(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_vref_dram_wr(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_vref_mc_rd(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::mss_vpd_mt_windage_rd_ctr(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mr_0_version_layout(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_1_version_data(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_2_signature_hash(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a00(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a01(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a02(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a03(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a04(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a05(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a06(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a07(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a08(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a09(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a10(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a11(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a12(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a13(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a17(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_ba0(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_ba1(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_bg0(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_bg1(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_c0(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_c1(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_c2(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d0_clk0(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d0_clk1(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d1_clk0(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d1_clk1(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cmd_actn(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cmd_addr_casn_a15(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cmd_addr_wen_a14(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cmd_par(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d0_cke0(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d0_cke1(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_cke0(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_cke1(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d0_csn0(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d0_csn1(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_csn0(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_csn1(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d0_odt0(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d0_odt1(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_odt0(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_odt1(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_2n_mode_autoset(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mt_0_version_layout(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_1_version_data(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_2_signature_hash(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_dimm_rcd_ibt(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_dram_drv_imp_dq_dqs(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_dram_rtt_nom(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_dram_rtt_park(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_dram_rtt_wr(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_mc_dq_acboost_rd_up(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_mc_dq_acboost_wr_down(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_mc_dq_acboost_wr_up(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_mc_dq_ctle_cap(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_mc_dq_ctle_res(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_mc_drv_imp_addr(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_mc_drv_imp_clk(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_mc_drv_imp_cntl(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_mc_drv_imp_dq_dqs(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_mc_drv_imp_spcke(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_mc_rcv_imp_dq_dqs(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_odt_rd(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_odt_wr(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_vref_dram_wr(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_vref_mc_rd(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_windage_rd_ctr(i_target, i_mt_blob) );
 
 fapi_try_exit:
     return fapi2::current_err;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
index 601e5e53b..19c3f2f1a 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
@@ -668,6 +668,9 @@ fapi2::ReturnCode phy_scominit(const fapi2::Target<TARGET_TYPE_MCBIST>& i_target
 
         // Read Control reset
         FAPI_TRY( mss::rc::reset(p) );
+
+        // Reset the AC Boost controls from the values in VPD
+        FAPI_TRY( mss::dp16::reset_ac_boost_cntl(p) );
     }
 
 fapi_try_exit:
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
index 3fd70a47f..fdd62a324 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
@@ -79,6 +79,19 @@ const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DATA_BIT_DIR1 =
     MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4,
 };
 
+// Definition of the DP16 AC Boost Control registers
+// DP16 AC Boost registers all come in pairs - one per 8 bits
+// 5 DP16 per MCA gives us 10  Registers.
+// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
+const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::AC_BOOST_CNTRL_REG =
+{
+    { MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0, MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0 },
+    { MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1, MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1 },
+    { MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2, MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2 },
+    { MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3, MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3 },
+    { MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4, MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4 },
+};
+
 namespace dp16
 {
 
@@ -423,5 +436,117 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
+///
+/// @brief Reset AC_BOOST_CNTL MCA specialization - for all DP16 in the target
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template<>
+fapi2::ReturnCode reset_ac_boost_cntl( const fapi2::Target<TARGET_TYPE_MCA>& i_target )
+{
+    typedef dp16Traits<TARGET_TYPE_MCA> TT;
+
+    // Get the attributes which contain the information from the VPD
+    fapi2::buffer<uint32_t> l_rd_up;
+    fapi2::buffer<uint32_t> l_wr_down;
+    fapi2::buffer<uint32_t> l_wr_up;
+
+    // Keep track of the bit postion we start at, so we can slide thru the attributes
+    // as we iterate over the registers
+    uint64_t l_start_bit = 0;
+    constexpr uint64_t BIT_FIELD_LEN = 3;
+    constexpr uint64_t BIT_POSITION_DELTA = BIT_FIELD_LEN * 2;
+
+    // A little DP block indicator useful for tracing
+    uint64_t l_which_dp16 = 0;
+
+    FAPI_TRY( mss::vpd_mt_mc_dq_acboost_rd_up(i_target, l_rd_up) );
+    FAPI_TRY( mss::vpd_mt_mc_dq_acboost_wr_down(i_target, l_wr_down) );
+    FAPI_TRY( mss::vpd_mt_mc_dq_acboost_wr_up(i_target, l_wr_up) );
+
+    FAPI_INF("seeing acboost attributes wr_down: 0x%08lx wr_up: 0x%08lx, rd_up: 0x%08lx",
+             l_wr_down, l_wr_up, l_rd_up);
+
+    // For all of the AC Boost attributes, they're laid out in the uint32_t as such:
+    // (dear OpenPOWER: remember in IBM-speak, bit 0 is the left-most bit because no
+    // good reason)
+    // Bit 0-2   = DP16 Block 0 (DQ Bits 0-7)
+    // Bit 3-5   = DP16 Block 0 (DQ Bits 8-15)
+    // Bit 6-8   = DP16 Block 1 (DQ Bits 0-7)
+    // Bit 9-11  = DP16 Block 1 (DQ Bits 8-15)
+    // Bit 12-14 = DP16 Block 2 (DQ Bits 0-7)
+    // Bit 15-17 = DP16 Block 2 (DQ Bits 8-15)
+    // Bit 18-20 = DP16 Block 3 (DQ Bits 0-7)
+    // Bit 21-23 = DP16 Block 3 (DQ Bits 8-15)
+    // Bit 24-26 = DP16 Block 4 (DQ Bits 0-7)
+    // Bit 27-29 = DP16 Block 4 (DQ Bits 8-15)
+
+    // For all the AC_BOOST registers on this MCA, shuffle in the bits and write
+    // the registers.
+
+    for (const auto& r : TT::AC_BOOST_CNTRL_REG)
+    {
+        fapi2::buffer<uint64_t> l_boost_0;
+        fapi2::buffer<uint64_t> l_boost_1;
+
+        // Read
+        FAPI_TRY( mss::getScom(i_target, r.first, l_boost_0) );
+        FAPI_TRY( mss::getScom(i_target, r.second, l_boost_1) );
+
+        // Modify
+        {
+            // Yeah, we could do this once, however we need to flush them to 0 every time so this is the same
+            fapi2::buffer<uint64_t> l_scratch_0;
+            fapi2::buffer<uint64_t> l_scratch_1;
+
+            l_wr_down.extractToRight(l_scratch_0, l_start_bit, BIT_FIELD_LEN);
+            l_boost_0.insertFromRight(l_scratch_0, TT::AC_BOOST_WR_DOWN, TT::AC_BOOST_WR_DOWN_LEN);
+
+            l_wr_down.extractToRight(l_scratch_1, l_start_bit + BIT_FIELD_LEN, BIT_FIELD_LEN);
+            l_boost_1.insertFromRight(l_scratch_1, TT::AC_BOOST_WR_DOWN, TT::AC_BOOST_WR_DOWN_LEN);
+
+            FAPI_INF("ac boost wr down for %s dp16 %d: 0x%08lx, 0x%08lx (0x%016lx, 0x%016lx)",
+                     mss::c_str(i_target), l_which_dp16, l_scratch_0, l_scratch_1, l_boost_0, l_boost_1);
+        }
+        {
+            fapi2::buffer<uint64_t> l_scratch_0;
+            fapi2::buffer<uint64_t> l_scratch_1;
+
+            l_wr_up.extractToRight(l_scratch_0, l_start_bit, BIT_FIELD_LEN);
+            l_boost_0.insertFromRight(l_scratch_0, TT::AC_BOOST_WR_UP, TT::AC_BOOST_WR_UP_LEN);
+
+            l_wr_up.extractToRight(l_scratch_1, l_start_bit + BIT_FIELD_LEN, BIT_FIELD_LEN);
+            l_boost_1.insertFromRight(l_scratch_1, TT::AC_BOOST_WR_UP, TT::AC_BOOST_WR_UP_LEN);
+
+            FAPI_INF("ac boost wr up for %s dp16 %d: 0x%08lx, 0x%08lx (0x%016lx, 0x%016lx)",
+                     mss::c_str(i_target), l_which_dp16, l_scratch_0, l_scratch_1, l_boost_0, l_boost_1);
+        }
+        {
+            fapi2::buffer<uint64_t> l_scratch_0;
+            fapi2::buffer<uint64_t> l_scratch_1;
+
+            l_rd_up.extractToRight(l_scratch_0, l_start_bit, BIT_FIELD_LEN);
+            l_boost_0.insertFromRight(l_scratch_0, TT::AC_BOOST_RD_UP, TT::AC_BOOST_RD_UP_LEN);
+
+            l_rd_up.extractToRight(l_scratch_1, l_start_bit + BIT_FIELD_LEN, BIT_FIELD_LEN);
+            l_boost_1.insertFromRight(l_scratch_1, TT::AC_BOOST_RD_UP, TT::AC_BOOST_RD_UP_LEN);
+
+            FAPI_INF("ac boost rd down for %s dp16 %d: 0x%08lx, 0x%08lx (0x%016lx, 0x%016lx)",
+                     mss::c_str(i_target), l_which_dp16, l_scratch_0, l_scratch_1, l_boost_0, l_boost_1);
+        }
+
+        // Write
+        FAPI_TRY( mss::putScom(i_target, r.first, l_boost_0) );
+        FAPI_TRY( mss::putScom(i_target, r.second, l_boost_1) );
+
+        // Slide over in the attributes, bump the dp16 trace counter, and do it again
+        l_start_bit += BIT_POSITION_DELTA;
+        ++l_which_dp16;
+    }
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
 } // close namespace dp16
 } // close namespace mss
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
index 025855639..b8e8067d7 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
@@ -125,6 +125,7 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA>
 
         // Vectors of DP16 registers. The pair represents the two DLL in per DP16
         static const std::vector< std::pair<uint64_t, uint64_t> > DLL_CNFG_REG;
+        static const std::vector< std::pair<uint64_t, uint64_t> > AC_BOOST_CNTRL_REG;
         static const std::vector< uint64_t > DATA_BIT_DIR1;
 
         enum
@@ -132,6 +133,14 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA>
             DLL_CNTL_INIT_RXDLL_CAL_RESET = MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_RESET,
             FLUSH = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_FLUSH,
             INIT_IO = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_INIT_IO,
+
+            // Seriously PHY guys?
+            AC_BOOST_WR_DOWN = MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC,
+            AC_BOOST_WR_DOWN_LEN = MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC_LEN,
+            AC_BOOST_WR_UP = MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC,
+            AC_BOOST_WR_UP_LEN = MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC_LEN,
+            AC_BOOST_RD_UP = MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC,
+            AC_BOOST_RD_UP_LEN = MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC_LEN,
         };
 };
 
@@ -197,6 +206,66 @@ fapi_try_exit:
 //
 
 ///
+/// @brief Read AC_BOOST_CNTL
+/// @tparam I DP16 instance
+/// @tparam T fapi2 Target Type - derived
+/// @tparam P the type of the std::pair elements
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of both of the the registers (upper and lower bytes)
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< uint64_t I, fapi2::TargetType T, typename P, typename TT = dp16Traits<T> >
+inline fapi2::ReturnCode read_ac_boost_cntl( const fapi2::Target<T>& i_target,
+        std::pair<P, P>& o_data )
+{
+    static_assert( I < TT::DP_COUNT, "dp16 instance out of range");
+
+    // The pair represents the upper and lower bytes of the DP16 - each has its own boost regiters
+    FAPI_TRY( mss::getScom(i_target, TT::AC_BOOST_CNTRL_REG[I].first, o_data.first) );
+    FAPI_TRY( mss::getScom(i_target, TT::AC_BOOST_CNTRL_REG[I].second, o_data.second) );
+    FAPI_INF("ac_boost_cntl dp16<%d>: 0x%016lx, 0x%016lx", I, o_data.first, o_data.second);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Write AC_BOOST_CNTL
+/// @tparam I DP16 instance
+/// @tparam T fapi2 Target Type - derived
+/// @tparam P the type of the std::pair elements
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of both of the the registers (upper and lower bytes)
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< uint64_t I, fapi2::TargetType T, typename P, typename TT = dp16Traits<T> >
+inline fapi2::ReturnCode write_ac_boost_cntl( const fapi2::Target<T>& i_target,
+        const std::pair<P, P>& i_data )
+{
+    static_assert( I < TT::DP_COUNT, "dp16 instance out of range");
+
+    // The pair represents the upper and lower bytes of the DP16 - each has its own boost regiters
+    FAPI_INF("ac_boost_cntl dp16<%d>: 0x%016lx, 0x%016lx", I, i_data.first, i_data.second);
+    FAPI_TRY( mss::putScom(i_target, TT::AC_BOOST_CNTRL_REG[I].first, i_data.first) );
+    FAPI_TRY( mss::putScom(i_target, TT::AC_BOOST_CNTRL_REG[I].second, i_data.second) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Reset AC_BOOST_CNTL - for all DP16 in the target
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = dp16Traits<T> >
+fapi2::ReturnCode reset_ac_boost_cntl( const fapi2::Target<T>& i_target );
+
+///
 /// @brief Set the DLL cal reset (begins DLL cal operations)
 /// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
 /// @tparam TT traits type defaults to dp16Traits<T>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml
index 93234ea92..db6be426b 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml
@@ -35,7 +35,7 @@
         <mssUnits>num</mssUnits>
         <mssBlobStart>0</mssBlobStart>
         <mssBlobLength>1</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_0_version_layout</mssAccessorName>
+        <mssAccessorName>vpd_mr_0_version_layout</mssAccessorName>
     </attribute>
 
     <attribute>
@@ -50,7 +50,7 @@
         <mssUnits>num</mssUnits>
         <mssBlobStart>1</mssBlobStart>
         <mssBlobLength>1</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_1_version_data</mssAccessorName>
+        <mssAccessorName>vpd_mr_1_version_data</mssAccessorName>
     </attribute>
 
     <attribute>
@@ -65,7 +65,7 @@
         <mssUnits>hash</mssUnits>
         <mssBlobStart>2</mssBlobStart>
         <mssBlobLength>4</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_2_signature_hash</mssAccessorName>
+        <mssAccessorName>vpd_mr_2_signature_hash</mssAccessorName>
     </attribute>
 
     <attribute>
@@ -80,7 +80,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>6</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_a00</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_a00</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -96,7 +96,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>8</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_a01</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_a01</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -112,7 +112,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>10</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_a02</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_a02</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -128,7 +128,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>12</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_a03</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_a03</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -144,7 +144,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>14</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_a04</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_a04</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -160,7 +160,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>16</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_a05</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_a05</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -176,7 +176,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>18</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_a06</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_a06</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -192,7 +192,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>20</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_a07</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_a07</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -208,7 +208,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>22</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_a08</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_a08</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -224,7 +224,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>24</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_a09</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_a09</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -240,7 +240,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>26</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_a10</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_a10</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -256,7 +256,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>28</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_a11</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_a11</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -272,7 +272,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>30</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_a12</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_a12</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -288,7 +288,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>32</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_a13</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_a13</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -304,7 +304,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>34</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_a17</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_a17</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -320,7 +320,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>36</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_ba0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_ba0</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -336,7 +336,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>38</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_ba1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_ba1</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -352,7 +352,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>40</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_bg0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_bg0</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -368,7 +368,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>42</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_bg1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_bg1</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -384,7 +384,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>44</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_c0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_c0</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -400,7 +400,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>46</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_c1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_c1</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -416,7 +416,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>48</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_addr_c2</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_addr_c2</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -432,7 +432,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>50</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_d0_clk0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_d0_clk0</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -448,7 +448,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>52</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_d0_clk1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_d0_clk1</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -464,7 +464,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>54</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_d1_clk0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_d1_clk0</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -480,7 +480,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>56</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_d1_clk1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_d1_clk1</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -496,7 +496,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>58</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cmd_actn</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cmd_actn</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -512,7 +512,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>60</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cmd_addr_casn_a15</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_casn_a15</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -528,7 +528,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>62</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cmd_addr_rasn_a16</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_rasn_a16</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -544,7 +544,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>64</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cmd_addr_wen_a14</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_wen_a14</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -560,7 +560,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>66</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cmd_par</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cmd_par</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -576,7 +576,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>68</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cntl_d0_cke0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_cke0</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -592,7 +592,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>70</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cntl_d0_cke1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_cke1</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -608,7 +608,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>72</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cntl_d1_cke0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_cke0</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -624,7 +624,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>74</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cntl_d1_cke1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_cke1</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -640,7 +640,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>76</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cntl_d0_csn0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_csn0</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -656,7 +656,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>78</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cntl_d0_csn1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_csn1</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -672,7 +672,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>80</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cntl_d1_csn0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_csn0</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -688,7 +688,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>82</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cntl_d1_csn1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_csn1</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -704,7 +704,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>84</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cntl_d0_odt0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_odt0</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -720,7 +720,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>86</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cntl_d0_odt1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_odt1</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -736,7 +736,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>88</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cntl_d1_odt0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_odt0</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -752,7 +752,7 @@
         <mssUnits>tick</mssUnits>
         <mssBlobStart>90</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_phase_rot_cntl_d1_odt1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_odt1</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -768,7 +768,7 @@
         <mssUnits>num</mssUnits>
         <mssBlobStart>92</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mr_mc_2n_mode_autoset</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_2n_mode_autoset</mssAccessorName>
         <array>2</array>
     </attribute>
 
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml
index 18adcab59..01a1e791c 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml
@@ -35,7 +35,7 @@
         <mssUnits>num</mssUnits>
         <mssBlobStart>0</mssBlobStart>
         <mssBlobLength>1</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_0_version_layout</mssAccessorName>
+        <mssAccessorName>vpd_mt_0_version_layout</mssAccessorName>
     </attribute>
 
     <attribute>
@@ -50,7 +50,7 @@
         <mssUnits>num</mssUnits>
         <mssBlobStart>1</mssBlobStart>
         <mssBlobLength>1</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_1_version_data</mssAccessorName>
+        <mssAccessorName>vpd_mt_1_version_data</mssAccessorName>
     </attribute>
 
     <attribute>
@@ -65,7 +65,7 @@
         <mssUnits></mssUnits>
         <mssBlobStart>2</mssBlobStart>
         <mssBlobLength>4</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_2_signature_hash</mssAccessorName>
+        <mssAccessorName>vpd_mt_2_signature_hash</mssAccessorName>
     </attribute>
 
     <attribute>
@@ -81,7 +81,7 @@
         <mssUnits>ohm</mssUnits>
         <mssBlobStart>6</mssBlobStart>
         <mssBlobLength>4</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_dimm_rcd_ibt</mssAccessorName>
+        <mssAccessorName>vpd_mt_dimm_rcd_ibt</mssAccessorName>
         <array>2 2</array>
     </attribute>
 
@@ -98,7 +98,7 @@
         <mssUnits>ohm</mssUnits>
         <mssBlobStart>10</mssBlobStart>
         <mssBlobLength>8</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_dram_drv_imp_dq_dqs</mssAccessorName>
+        <mssAccessorName>vpd_mt_dram_drv_imp_dq_dqs</mssAccessorName>
         <array>2 2 2</array>
     </attribute>
 
@@ -115,7 +115,7 @@
         <mssUnits>ohm</mssUnits>
         <mssBlobStart>18</mssBlobStart>
         <mssBlobLength>8</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_dram_rtt_nom</mssAccessorName>
+        <mssAccessorName>vpd_mt_dram_rtt_nom</mssAccessorName>
         <array>2 2 2</array>
     </attribute>
 
@@ -132,7 +132,7 @@
         <mssUnits>ohm</mssUnits>
         <mssBlobStart>26</mssBlobStart>
         <mssBlobLength>8</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_dram_rtt_park</mssAccessorName>
+        <mssAccessorName>vpd_mt_dram_rtt_park</mssAccessorName>
         <array>2 2 2</array>
     </attribute>
 
@@ -149,7 +149,7 @@
         <mssUnits>ohm</mssUnits>
         <mssBlobStart>34</mssBlobStart>
         <mssBlobLength>8</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_dram_rtt_wr</mssAccessorName>
+        <mssAccessorName>vpd_mt_dram_rtt_wr</mssAccessorName>
         <array>2 2 2</array>
     </attribute>
 
@@ -175,7 +175,7 @@
         <mssUnits></mssUnits>
         <mssBlobStart>42</mssBlobStart>
         <mssBlobLength>8</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_mc_dq_acboost_rd_up</mssAccessorName>
+        <mssAccessorName>vpd_mt_mc_dq_acboost_rd_up</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -201,7 +201,7 @@
         <mssUnits></mssUnits>
         <mssBlobStart>50</mssBlobStart>
         <mssBlobLength>8</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_mc_dq_acboost_wr_down</mssAccessorName>
+        <mssAccessorName>vpd_mt_mc_dq_acboost_wr_down</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -227,7 +227,7 @@
         <mssUnits></mssUnits>
         <mssBlobStart>58</mssBlobStart>
         <mssBlobLength>8</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_mc_dq_acboost_wr_up</mssAccessorName>
+        <mssAccessorName>vpd_mt_mc_dq_acboost_wr_up</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -251,7 +251,7 @@
         <mssUnits></mssUnits>
         <mssBlobStart>66</mssBlobStart>
         <mssBlobLength>16</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_mc_dq_ctle_cap</mssAccessorName>
+        <mssAccessorName>vpd_mt_mc_dq_ctle_cap</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -275,7 +275,7 @@
         <mssUnits></mssUnits>
         <mssBlobStart>82</mssBlobStart>
         <mssBlobLength>16</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_mc_dq_ctle_res</mssAccessorName>
+        <mssAccessorName>vpd_mt_mc_dq_ctle_res</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -292,7 +292,7 @@
         <mssUnits>ohm</mssUnits>
         <mssBlobStart>98</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_mc_drv_imp_addr</mssAccessorName>
+        <mssAccessorName>vpd_mt_mc_drv_imp_addr</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -309,7 +309,7 @@
         <mssUnits>ohm</mssUnits>
         <mssBlobStart>100</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_mc_drv_imp_clk</mssAccessorName>
+        <mssAccessorName>vpd_mt_mc_drv_imp_clk</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -326,7 +326,7 @@
         <mssUnits>ohm</mssUnits>
         <mssBlobStart>102</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_mc_drv_imp_cntl</mssAccessorName>
+        <mssAccessorName>vpd_mt_mc_drv_imp_cntl</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -343,7 +343,7 @@
         <mssUnits>ohm</mssUnits>
         <mssBlobStart>104</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_mc_drv_imp_dq_dqs</mssAccessorName>
+        <mssAccessorName>vpd_mt_mc_drv_imp_dq_dqs</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -360,7 +360,7 @@
         <mssUnits>ohm</mssUnits>
         <mssBlobStart>106</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_mc_drv_imp_spcke</mssAccessorName>
+        <mssAccessorName>vpd_mt_mc_drv_imp_spcke</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -377,7 +377,7 @@
         <mssUnits>ohm</mssUnits>
         <mssBlobStart>108</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_mc_rcv_imp_dq_dqs</mssAccessorName>
+        <mssAccessorName>vpd_mt_mc_rcv_imp_dq_dqs</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -393,7 +393,7 @@
         <mssUnits></mssUnits>
         <mssBlobStart>110</mssBlobStart>
         <mssBlobLength>8</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_odt_rd</mssAccessorName>
+        <mssAccessorName>vpd_mt_odt_rd</mssAccessorName>
         <array>2 2 2</array>
     </attribute>
 
@@ -409,7 +409,7 @@
         <mssUnits></mssUnits>
         <mssBlobStart>118</mssBlobStart>
         <mssBlobLength>8</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_odt_wr</mssAccessorName>
+        <mssAccessorName>vpd_mt_odt_wr</mssAccessorName>
         <array>2 2 2</array>
     </attribute>
 
@@ -425,7 +425,7 @@
         <mssUnits></mssUnits>
         <mssBlobStart>126</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_vref_dram_wr</mssAccessorName>
+        <mssAccessorName>vpd_mt_vref_dram_wr</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -442,7 +442,7 @@
         <mssUnits>percent of Vdd</mssUnits>
         <mssBlobStart>128</mssBlobStart>
         <mssBlobLength>8</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_vref_mc_rd</mssAccessorName>
+        <mssAccessorName>vpd_mt_vref_mc_rd</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -458,7 +458,7 @@
         <mssUnits>num</mssUnits>
         <mssBlobStart>136</mssBlobStart>
         <mssBlobLength>4</mssBlobLength>
-        <mssAccessorName>mss_vpd_mt_windage_rd_ctr</mssAccessorName>
+        <mssAccessorName>vpd_mt_windage_rd_ctr</mssAccessorName>
         <array>2</array>
     </attribute>