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| author | Dan Crowell <dcrowell@us.ibm.com> | 2017-04-14 13:01:32 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-04-17 14:35:02 -0400 |
| commit | fc384889b3e18d51f56ca43976f0d455271b7280 (patch) | |
| tree | 338e9d32c06914576d0a6ce4aa0f08918e9eda7c /src | |
| parent | 05f0ee2abdaf68858e506ce800ea98084f9c80d9 (diff) | |
| download | talos-hostboot-fc384889b3e18d51f56ca43976f0d455271b7280.tar.gz talos-hostboot-fc384889b3e18d51f56ca43976f0d455271b7280.zip | |
Remove PIB reset recovery for everything except Centaur
A PIB reset is a catastrophic event in P9, causing issues to
other logic (e.g. power management engines).
Change-Id: I65cca3bf5574f56e8851bf535037be38bcbb4910
RTC: 167651
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39279
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/usr/fsi/fsidd.C | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/src/usr/fsi/fsidd.C b/src/usr/fsi/fsidd.C index 9f651f173..bbbdce165 100644 --- a/src/usr/fsi/fsidd.C +++ b/src/usr/fsi/fsidd.C @@ -2670,13 +2670,21 @@ errlHndl_t FsiDD::errorCleanup( FSI::FsiAddrInfo_t& i_addrInfo, l_err = write( i_addrInfo.fsiTarg, FSI::SLRES_34, &data ); if(l_err) break; - //further step is to issue a PIB reset to the FSI2PIB engine - //in busy state, i.e. write arbitrary data to 101c - //(putcfam 1007) register of the previously failed FSI2PIB - //engine on Centaur. - data = 0xFFFFFFFF; - l_err = write( i_addrInfo.fsiTarg, FSI::FSI2PIB_STATUS, &data ); - if(l_err) break; + //Note: Not issuing PIB reset here to recent chips as it + // causes bad things to the rest of the logic + if( i_addrInfo.fsiTarg->getAttr<TARGETING::ATTR_MODEL>() + == TARGETING::MODEL_CENTAUR ) + { + //further step is to issue a PIB reset to the FSI2PIB engine + //in busy state, i.e. write arbitrary data to 101c + //(putcfam 1007) register of the previously failed FSI2PIB + //engine on Centaur. + data = 0xFFFFFFFF; + l_err = write( i_addrInfo.fsiTarg, + FSI::FSI2PIB_STATUS, + &data ); + if(l_err) break; + } //Need to save/restore the true/comp masks or the FSP will // get annoyed |
