diff options
| author | Stephen Glancy <sglancy@us.ibm.com> | 2017-06-15 13:04:02 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-06-19 13:50:25 -0400 |
| commit | f3fba8c656ba6c3983d3b6761327480c3d1cbcea (patch) | |
| tree | dbadfe4c27ba47c209e2ddade14b5e35aaa8cf32 /src | |
| parent | 4c3aaea4c22328b2fcf114e282e1f02d34a3898b (diff) | |
| download | talos-hostboot-f3fba8c656ba6c3983d3b6761327480c3d1cbcea.tar.gz talos-hostboot-f3fba8c656ba6c3983d3b6761327480c3d1cbcea.zip | |
Fixes bug where WR VREF would never be run
Change-Id: Ifc880e4ad711a6c447d31b47258e28745d53dea4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41909
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41912
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C | 5 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H | 4 |
2 files changed, 5 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index 81cbe8297..60feb017d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -1125,7 +1125,8 @@ fapi2::ReturnCode setup_and_execute_cal( const fapi2::Target<fapi2::TARGET_TYPE_ // Sets up the cal steps in the buffer fapi2::buffer<uint32_t> l_steps_to_execute; l_steps_to_execute.setBit<mss::cal_steps::DQS_ALIGN>(); - l_steps_to_execute.writeBit<mss::cal_steps::INITIAL_PAT_WR>(i_cal_steps_enabled.getBit<mss::cal_steps::WR_LEVEL>()); + l_steps_to_execute.writeBit<mss::cal_steps::INITIAL_PAT_WR> + (i_cal_steps_enabled.getBit<mss::cal_steps::INITIAL_PAT_WR>()); FAPI_INF("%s Running DQS align on RP%d 0x%08lx", mss::c_str(i_target), i_rp, l_steps_to_execute); @@ -1174,7 +1175,7 @@ fapi2::ReturnCode setup_and_execute_cal( const fapi2::Target<fapi2::TARGET_TYPE_ if (i_cal_steps_enabled.getBit<mss::cal_steps::WRITE_CTR, mss::cal_steps::WR_VREF_TO_COARSE_RD_LEN>()) { fapi2::buffer<uint32_t> l_steps_to_execute( i_cal_steps_enabled ); - l_steps_to_execute.clearBit<mss::cal_steps::DRAM_ZQCAL, mss::cal_steps::DRAM_ZQCAL_TO_WRITE_CTR_2D_VREF>(); + l_steps_to_execute.clearBit<mss::cal_steps::DRAM_ZQCAL, mss::cal_steps::DRAM_ZQCAL_UP_TO_WRITE_CTR_2D_VREF>(); // Setting the WR_VREF_LATCH bit to run the WR_VREF workaround after wr_vref runs // Gets set iff the bit is set in i_steps_to_execute diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index e54a9c6b2..a225fb1ec 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -177,11 +177,11 @@ enum cal_steps : uint64_t RUN_ALL_CAL_STEPS = 0xFFFFF000, RUN_CAL_SKIP_WR_RD_2D_VREF = 0xFFFD7000, - DRAM_ZQCAL_TO_WR_LEVEL_LEN = inclusive_range(DRAM_ZQCAL, WR_LEVEL), INITIAL_PAT_WR_TO_RD_CTR_LEN = inclusive_range(INITIAL_PAT_WR, READ_CTR), WR_VREF_TO_COARSE_RD_LEN = inclusive_range(WRITE_CTR_2D_VREF, COARSE_RD), RDCLK_ALIGN_TO_RD_CTR_LEN = inclusive_range(RDCLK_ALIGN, READ_CTR), - DRAM_ZQCAL_TO_WRITE_CTR_2D_VREF = inclusive_range(DRAM_ZQCAL, WRITE_CTR_2D_VREF), + // In this case, we just want to clear everything prior to WR 2D VREF, inclusive range also kills the WR VREF bit + DRAM_ZQCAL_UP_TO_WRITE_CTR_2D_VREF = WRITE_CTR_2D_VREF, }; // Static consts for DDR4 voltages used in p9_mss_volt |
