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| author | Jacob Harvey <jlharvey@us.ibm.com> | 2017-04-25 09:47:34 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-05-03 13:13:16 -0400 |
| commit | f08f9a6bd3e26e212f3df35e6205d216d234c288 (patch) | |
| tree | b520e737bb4e48624af0ea266deef6b4bc60f710 /src | |
| parent | 0454abc3ae5785821f1806496eafbce2807ab7c0 (diff) | |
| download | talos-hostboot-f08f9a6bd3e26e212f3df35e6205d216d234c288.tar.gz talos-hostboot-f08f9a6bd3e26e212f3df35e6205d216d234c288.zip | |
Change RD_CTR workaround val and update attr name
Change-Id: I00b2cf9cb54fdc4ec54b8f75ae1b9e687d2d4549
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39649
Reviewed-by: ANUWAT SAETOW <asaetow@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Dev-Ready: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39657
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
3 files changed, 13 insertions, 13 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H index 069b24625..faafed6ae 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H @@ -337,7 +337,7 @@ fapi_try_exit: } /// -/// @brief ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WOKRAROUND getter +/// @brief ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WORKAROUND getter /// @tparam T the fapi2 target type of the target /// @param[in] const ref to the target /// @return bool true iff feature is enabled @@ -348,12 +348,12 @@ inline bool chip_ec_feature_mss_run_rd_ctr_workaround(const fapi2::Target<T>& i_ const auto l_chip = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(i_target); uint8_t l_value = 0; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WOKRAROUND, l_chip, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WORKAROUND, l_chip, l_value) ); return l_value != 0; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WOKRAROUND: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WORKAROUND: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); fapi2::Assert(false); return false; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H index 2db02bf34..1c670c9ca 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H @@ -346,12 +346,12 @@ fapi2::ReturnCode find_median_and_sort(std::vector<delay_data>& io_reg_data, uin /// @brief Overrides any bad (out of range) read delay values with the median value /// @param[in] i_target the fapi2 target of the port /// @param[in] i_rank_pair the rank pair to operate on -/// @param[in] i_percent the percentage below the median outside of which to override values to be the median - OPTIONAL - defaults to 66 +/// @param[in] i_percent the percentage below the median outside of which to override values to be the median - OPTIONAL - defaults to 75 /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok /// fapi2::ReturnCode fix_delay_values(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const uint64_t i_rank_pair, - const uint64_t i_percent = 66); + const uint64_t i_percent = 75); } // close namespace rd_dq diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 85e8495f2..304adeefd 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -71,7 +71,7 @@ <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> Returns true if the chip has NDL IOValid bits - P9N dd2 + P9N dd2 </description> <chipEcFeature> <chip> @@ -162,7 +162,7 @@ </chip> </chipEcFeature> </attribute> - <!-- ********************************************************************* --> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_FSI_GP_SHADOWS_OVERWRITE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -257,7 +257,7 @@ <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> Filter pll setting differences. - Cumulus matches nimbus dd2. + Cumulus matches nimbus dd2. </description> <chipEcFeature> <chip> @@ -345,7 +345,7 @@ <id>ATTR_CHIP_EC_FEATURE_HW405413</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - HW405413 : NCU sends data out of order + HW405413 : NCU sends data out of order </description> <chipEcFeature> <chip> @@ -1363,7 +1363,7 @@ <id>ATTR_CHIP_EC_FEATURE_HW377094</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - DD1 only: HW377094 L2 stq and ncu stq deadlock. g/ord_g causes artificial dependency between barrier and snptlbcmp in NCU + DD1 only: HW377094 L2 stq and ncu stq deadlock. g/ord_g causes artificial dependency between barrier and snptlbcmp in NCU while lfsr bits being reused in L2 stq causes entry to never be selected due to high priority ld-hit-st override. </description> <chipEcFeature> @@ -2459,7 +2459,7 @@ <id>ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - DD1 only: Use the DD1 register addresses for the PHY0 BAR registers, PHY1 BAR registers, and MMIO BAR registers + DD1 only: Use the DD1 register addresses for the PHY0 BAR registers, PHY1 BAR registers, and MMIO BAR registers </description> <chipEcFeature> <chip> @@ -2737,7 +2737,7 @@ </attribute> <attribute> - <id>ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WOKRAROUND</id> + <id>ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WORKAROUND</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> In below DD2 Nimbus, a workaround after read centering might need to be run. @@ -2897,7 +2897,7 @@ <id>ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - For Nimbus DD2 we no longer need a workaround for Ring Save in MPIPL + For Nimbus DD2 we no longer need a workaround for Ring Save in MPIPL </description> <chipEcFeature> <chip> |
