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| author | Matt Ploetz <maploetz@us.ibm.com> | 2017-04-10 15:59:43 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-04-14 14:35:02 -0400 |
| commit | e1f7f248bb421cf31a5872a0d5ff5726032a4404 (patch) | |
| tree | 9b73427501c13a8c0244c75a0a047dede4d8a6c7 /src | |
| parent | 6e5f3ee7ecb21964d8cfa239e2620c498912ad1d (diff) | |
| download | talos-hostboot-e1f7f248bb421cf31a5872a0d5ff5726032a4404.tar.gz talos-hostboot-e1f7f248bb421cf31a5872a0d5ff5726032a4404.zip | |
Add no connected PHB config to all PECs
Change-Id: I3aee218a8c482877b3595ced9721919da28d711f
CQ:SW384841
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39067
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/usr/isteps/istep08/host_proc_pcie_scominit.C | 39 |
1 files changed, 36 insertions, 3 deletions
diff --git a/src/usr/isteps/istep08/host_proc_pcie_scominit.C b/src/usr/isteps/istep08/host_proc_pcie_scominit.C index e807a1b7e..00d733489 100644 --- a/src/usr/isteps/istep08/host_proc_pcie_scominit.C +++ b/src/usr/isteps/istep08/host_proc_pcie_scominit.C @@ -341,7 +341,14 @@ errlHndl_t computeProcPcieConfigAttrs(TARGETING::Target * i_pProcChipTarget) // is discovered, the PEC config value is pulled from the matching row and // set in the attributes. const laneConfigRow pec0_laneConfigTable[] = - {{{LANE_WIDTH_16X, + {{{LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC}, + 0x00,PHB_MASK_NA, + PHB_X16_MAC_MAP}, + + {{LANE_WIDTH_16X, LANE_WIDTH_NC, LANE_WIDTH_NC, LANE_WIDTH_NC}, @@ -350,7 +357,14 @@ errlHndl_t computeProcPcieConfigAttrs(TARGETING::Target * i_pProcChipTarget) }; const laneConfigRow pec1_laneConfigTable[] = - {{{LANE_WIDTH_8X, + {{{LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC}, + 0x00,PHB_MASK_NA, + PHB_X8_X8_MAC_MAP}, + + {{LANE_WIDTH_8X, LANE_WIDTH_NC, LANE_WIDTH_8X, LANE_WIDTH_NC}, @@ -373,7 +387,14 @@ errlHndl_t computeProcPcieConfigAttrs(TARGETING::Target * i_pProcChipTarget) }; const laneConfigRow pec2_laneConfigTable[] = - {{{LANE_WIDTH_16X, + {{{LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC}, + 0x00,PHB_MASK_NA, + PHB_X16_MAC_MAP}, + + {{LANE_WIDTH_16X, LANE_WIDTH_NC, LANE_WIDTH_NC, LANE_WIDTH_NC}, @@ -682,10 +703,22 @@ errlHndl_t computeProcPcieConfigAttrs(TARGETING::Target * i_pProcChipTarget) refEnable = 0x1; macCntl = laneConfigItr->phb_to_pcieMAC; pecPhbActiveMask = laneConfigItr->phbActive; + + // If we find a valid config, and the PHB_MASK is still NA + // that means all PHB's on this PEC will be disabled. Lets + // trace something out just so someone knows. + if(pecPhbActiveMask == PHB_MASK_NA) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,"Valid " + "configuration found for PEC 0x%08X, but no PHBs behind " + "it wil be functional", l_pecID); + } + // Disable applicable PHBs pecPhbActiveMask &= (~disabledPhbs); // Add the PEC phb mask to the overall Proc PHB mask procPhbActiveMask |= pecPhbActiveMask; + } else { |
