diff options
author | Thi Tran <thi@us.ibm.com> | 2013-09-19 12:30:02 -0500 |
---|---|---|
committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-09-19 16:14:58 -0500 |
commit | d7fe818bc556e2ce826ba70247f8cd832af581c3 (patch) | |
tree | db2b9374c98b2ea9ab24fdf7f165bafebebc8fd8 /src | |
parent | aff8b3f7925b5c1d440260035e7db7b3eae0ac99 (diff) | |
download | talos-hostboot-d7fe818bc556e2ce826ba70247f8cd832af581c3.tar.gz talos-hostboot-d7fe818bc556e2ce826ba70247f8cd832af581c3.zip |
INITPROC: Hostboot - from defect SW223818 - High Priority week 9/10
Change-Id: Ia25ff3f1a518fb9b4333c4cec1dd6a6ef0797e2d
CQ:SW223818
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6260
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src')
4 files changed, 228 insertions, 29 deletions
diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C index 7416c9170..d761e5424 100644 --- a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C +++ b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_thermal_init.C,v 1.6 2012/11/28 15:22:20 joabhend Exp $ +// $Id: mss_thermal_init.C,v 1.7 2013/09/12 15:23:21 joabhend Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_thermal_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -45,6 +45,10 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.7 | pardeik |01-AUG-13| Functional corrections to procedure +// | Updates for defect HW257484 +// | Use custom DIMM instead of dimm type attribute +// | Added commented out throttle section at end to enable later // 1.6 | joabhend |28-NOV-12| Corrected procedure_name from char* to const char* // 1.5 | joabhend |16-NOV-12| Updated code to reflect review output // 1.4 | joabhend |02-NOV-12| Corrected scom call from SCAC_FIRMASK to SCAC_ADDRMAP @@ -60,6 +64,7 @@ #include <mss_thermal_init.H> #include <fapi.H> #include <mss_unmask_errors.H> +#include <cen_scom_addresses.H> extern "C" { @@ -111,30 +116,93 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target) const uint8_t l_NUM_PORTS = 2; // Number of ports per MBA const uint8_t l_NUM_DIMMS = 2; // Number of dimms per MBA port + const uint64_t HANG_PULSE_0_REG = 0x020f0020; + const uint64_t THERM_MODE_REG = 0x0205000f; + const uint64_t CONTROL_REG = 0x02050012; + const uint64_t SCAC_FIRMASK = 0x020115c3; + const uint64_t SCAC_ACTMASK = 0x020115d3; const uint64_t SCAC_ADDRMAP = 0x020115cd; const uint64_t SCAC_CONFIG = 0x020115ce; const uint64_t SCAC_ENABLE = 0x020115cc; const uint64_t SCAC_I2CMCTRL = 0x020115d1; //const uint64_t SCAC_LFIR = 0x020115c0; const uint64_t SCAC_PIBTARGET = 0x020115d2; + const uint64_t I2CM_RESET = 0x000A0001; const uint64_t MBS_EMER_THROT = 0x0201142d; const uint64_t MBS_FIR_REG = 0x02011400; const uint32_t PRIMARY_I2C_BASE_ADDR = 0x000A0000; - const uint32_t SPARE_I2C_BASE_ADDR = 0x000A0020; - const uint32_t I2C_SETUP_UPPER_HALF = 0x92314009; - const uint32_t I2C_SETUP_LOWER_HALF = 0x00000000; - const uint32_t CONFIG_INTERVAL_TIMER = 0; - const uint32_t CONFIG_STALE_TIMER = 0; + const uint32_t SPARE_I2C_BASE_ADDR = 0x000A0000; + const uint32_t I2C_SETUP_UPPER_HALF = 0xD2314049; + const uint32_t I2C_SETUP_LOWER_HALF = 0x05000000; + const uint32_t ACT_MASK_UPPER_HALF = 0x00018000; + const uint32_t ACT_MASK_LOWER_HALF = 0x00000000; +// OCC polls cacheline every 2 ms. +// For I2C bus at 50kHz (9.6 ms max to read 8 sensors), use interval of 5 to prevent stall error + const uint32_t CONFIG_INTERVAL_TIMER = 5; + const uint32_t CONFIG_STALL_TIMER = 128; // Variable declaration uint8_t l_dimm_ranks_array[l_NUM_MBAS][l_NUM_PORTS][l_NUM_DIMMS]; // Number of ranks for each configured DIMM in each MBA - uint8_t l_dimm_type_array[l_NUM_MBAS]; // Type of DIMMs in each MBA + uint8_t l_custom_dimm[l_NUM_MBAS]; // Custom DIMM uint8_t l_mba_pos = 0; // Current MBA for populating rank array ecmdDataBufferBase l_data(64); +//******************************************** +// Centaur internal temperature polling setup +//******************************************** +// setup hang pulse + l_rc = fapiGetScom(i_target, HANG_PULSE_0_REG, l_data); + if (l_rc) return l_rc; + l_ecmd_rc |= l_data.setBit(1); + l_ecmd_rc |= l_data.setBit(2); + if(l_ecmd_rc) { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } + l_rc = fapiPutScom(i_target, HANG_PULSE_0_REG, l_data); + if (l_rc) return l_rc; +// setup DTS enables + l_rc = fapiGetScom(i_target, THERM_MODE_REG, l_data); + l_ecmd_rc |= l_data.setBit(20); + l_ecmd_rc |= l_data.setBit(21); + if(l_ecmd_rc) { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } + l_rc = fapiPutScom(i_target, THERM_MODE_REG, l_data); + if (l_rc) return l_rc; +// setup pulse count and enable DTS sampling + l_rc = fapiGetScom(i_target, THERM_MODE_REG, l_data); + l_ecmd_rc |= l_data.setBit(5); + l_ecmd_rc |= l_data.setBit(6); + l_ecmd_rc |= l_data.setBit(7); + l_ecmd_rc |= l_data.setBit(8); + l_ecmd_rc |= l_data.setBit(9); + if(l_ecmd_rc) { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } + l_rc = fapiPutScom(i_target, THERM_MODE_REG, l_data); + if (l_rc) return l_rc; +// issue a reset + l_ecmd_rc |= l_data.flushTo0(); + l_ecmd_rc |= l_data.setBit(0); + l_ecmd_rc |= l_data.setBit(1); + l_ecmd_rc |= l_data.setBit(2); + l_ecmd_rc |= l_data.setBit(3); + l_ecmd_rc |= l_data.setBit(4); + if(l_ecmd_rc) { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } + l_rc = fapiPutScom(i_target, CONTROL_REG, l_data); + if (l_rc) return l_rc; +// Centaur internal temperature polling setup complete + + // Get input attributes from MBAs std::vector<fapi::Target> l_target_mba_array; l_rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MBA_CHIPLET, l_target_mba_array); @@ -149,9 +217,9 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target) if (l_rc) return l_rc; FAPI_INF("EFF_NUM_RANKS: %d:%d:%d:%d", l_dimm_ranks_array[l_mba_pos][0][0], l_dimm_ranks_array[l_mba_pos][0][1], l_dimm_ranks_array[l_mba_pos][1][0], l_dimm_ranks_array[l_mba_pos][1][1]); - l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &l_target_mba_array[mba_index], l_dimm_type_array[l_mba_pos]); + l_rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &l_target_mba_array[mba_index], l_custom_dimm[l_mba_pos]); if (l_rc) return l_rc; - FAPI_INF("ATTR_EFF_DIMM_TYPE: %d", l_dimm_type_array[l_mba_pos]); + FAPI_INF("ATTR_EFF_DIMM_TYPE: %d", l_custom_dimm[l_mba_pos]); } // Configure Centaur Thermal Cache @@ -198,7 +266,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target) l_rc = fapiGetScom(i_target, SCAC_ADDRMAP, l_data); if (l_rc) return l_rc; - if (l_dimm_type_array[0] == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM && l_dimm_type_array[1] == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM){ + if (l_custom_dimm[0] == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES && l_custom_dimm[1] == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES){ l_addr_map_data_int = 0x012389ab; } else{ @@ -259,7 +327,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target) l_ecmd_rc |= l_i2c_ctrl_lower_half.insert(I2C_SETUP_LOWER_HALF, 0, 32, 0); l_ecmd_rc |= l_data.insert(l_i2c_ctrl_upper_half, 0, 32, 0); - l_ecmd_rc |= l_data.insert(l_i2c_ctrl_lower_half, 32, 0, 0); + l_ecmd_rc |= l_data.insert(l_i2c_ctrl_lower_half, 32, 32, 0); if(l_ecmd_rc) { l_rc.setEcmdError(l_ecmd_rc); return l_rc; @@ -267,6 +335,33 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target) l_rc = fapiPutScom(i_target, SCAC_I2CMCTRL, l_data); if (l_rc) return l_rc; + + // --------------------------------- + // Program Action Mask Register + // --------------------------------- + + l_rc = fapiGetScom(i_target, SCAC_ACTMASK, l_data); + if (l_rc) return l_rc; + + ecmdDataBufferBase l_act_mask_upper_half(32); + ecmdDataBufferBase l_act_mask_lower_half(32); + + l_ecmd_rc |= l_act_mask_upper_half.flushTo0(); + l_ecmd_rc |= l_act_mask_upper_half.insert(ACT_MASK_UPPER_HALF, 0, 32, 0); + + l_ecmd_rc |= l_act_mask_lower_half.flushTo0(); + l_ecmd_rc |= l_act_mask_lower_half.insert(ACT_MASK_LOWER_HALF, 0, 32, 0); + + l_ecmd_rc |= l_data.insert(l_act_mask_upper_half, 0, 32, 0); + l_ecmd_rc |= l_data.insert(l_act_mask_lower_half, 32, 32, 0); + if(l_ecmd_rc) { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } + l_rc = fapiPutScom(i_target, SCAC_ACTMASK, l_data); + if (l_rc) return l_rc; + + // --------------------------------- // Program SensorCacheConfiguration Register // --------------------------------- @@ -275,17 +370,17 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target) if (l_rc) return l_rc; ecmdDataBufferBase l_interval_timer(32); - ecmdDataBufferBase l_stale_timer(32); + ecmdDataBufferBase l_stall_timer(32); l_ecmd_rc |= l_interval_timer.flushTo0(); l_ecmd_rc |= l_interval_timer.insert(CONFIG_INTERVAL_TIMER, 0, 32, 0); - l_ecmd_rc |= l_stale_timer.flushTo0(); - l_ecmd_rc |= l_stale_timer.insert(CONFIG_STALE_TIMER, 0, 32, 0); + l_ecmd_rc |= l_stall_timer.flushTo0(); + l_ecmd_rc |= l_stall_timer.insert(CONFIG_STALL_TIMER, 0, 32, 0); l_ecmd_rc |= l_data.setBit(1); //Sync to OCC_Read signal l_ecmd_rc |= l_data.insert(l_interval_timer, 11, 5, 32-5); - l_ecmd_rc |= l_data.insert(l_stale_timer, 16, 8, 32-8); + l_ecmd_rc |= l_data.insert(l_stall_timer, 16, 8, 32-8); if(l_ecmd_rc) { l_rc.setEcmdError(l_ecmd_rc); return l_rc; @@ -300,7 +395,9 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target) l_rc = fapiGetScom(i_target, SCAC_ENABLE, l_data); if (l_rc) return l_rc; - if (l_dimm_type_array[0] == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM && l_dimm_type_array[1] == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM){ + if (l_custom_dimm[0] == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES && l_custom_dimm[1] == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES){ + + l_ecmd_rc |= l_data.setBit(0); l_ecmd_rc |= l_data.setBit(4); } @@ -336,6 +433,20 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target) l_rc = fapiPutScom(i_target, SCAC_ENABLE, l_data); if (l_rc) return l_rc; + //--------------------------------- + // Reset the I2CM + //--------------------------------- + + ecmdDataBufferBase l_reset(64); + l_ecmd_rc |= l_reset.flushTo0(); + l_ecmd_rc |= l_reset.setBit(0); + if(l_ecmd_rc) { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } + + l_rc = fapiPutScom(i_target, I2CM_RESET, l_reset); + if (l_rc) return l_rc; // --------------------------------- // Set the master enable bit @@ -394,6 +505,85 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target) // Disable Emergency Throttles COMPLETED + +// Write the IPL Safe Mode Throttles +// TODO: Enable once OCC writes the runtime memory throttles +/* + uint32_t l_safemode_throttle_n_per_mba; + uint32_t l_safemode_throttle_n_per_chip; + uint32_t l_safemode_throttle_d; + + l_rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA, NULL, l_safemode_throttle_n_per_mba); + if (l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP, NULL, l_safemode_throttle_n_per_chip); + if (l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR, NULL, l_safemode_throttle_d); + if (l_rc) return l_rc; +// write the N/M throttle control register + for (uint8_t mba_index = 0; mba_index < l_target_mba_array.size(); mba_index++){ + l_rc = fapiGetScom(l_target_mba_array[mba_index], MBA01_MBA_FARB3Q_0x03010416, l_data); + if (l_rc) return l_rc; + l_ecmd_rc |= l_data.insertFromRight(l_safemode_throttle_n_per_mba, 0, 15); + l_ecmd_rc |= l_data.insertFromRight(l_safemode_throttle_n_per_chip, 15, 16); + l_ecmd_rc |= l_data.insertFromRight(l_safemode_throttle_d, 31, 14); + if(l_ecmd_rc) { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } + l_rc = fapiPutScom(l_target_mba_array[mba_index], MBA01_MBA_FARB3Q_0x03010416, l_data); + if (l_rc) return l_rc; + } +*/ + +// Update the runtime throttle attributes if needed for non custom DIMMs since those run power tests +// TODO: Enable once dimm_power_test is running and updating attributes +/* + uint32_t l_runtime_throttle_n_per_mba; + uint32_t l_runtime_throttle_n_per_chip; + uint32_t l_runtime_throttle_d; + uint32_t l_dimm_power_test_throttle_n_per_mba; + uint32_t l_dimm_power_test_throttle_n_per_chip; + uint32_t l_dimm_power_test_throttle_d; + + for (uint8_t mba_index = 0; mba_index < l_target_mba_array.size(); mba_index++){ + if (l_custom_dimm[mba_index] == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO){ + + l_rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA, &l_target_mba_array[mba_index], l_runtime_throttle_n_per_mba); + if (l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP, &l_target_mba_array[mba_index], l_runtime_throttle_n_per_chip); + if (l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR, &l_target_mba_array[mba_index], l_runtime_throttle_d); + if (l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_MBA, &l_target_mba_array[mba_index], l_dimm_power_test_throttle_n_per_mba); + if (l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_CHIP, &l_target_mba_array[mba_index], l_dimm_power_test_throttle_n_per_chip); + if (l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_DENOMINATOR, &l_target_mba_array[mba_index], l_dimm_power_test_throttle_d); + if (l_rc) return l_rc; +// update the runtime throttle attributes with the dimm power test attributes if they are different + if ( + (l_runtime_throttle_n_per_mba != l_dimm_power_test_throttle_n_per_mba) + || + (l_runtime_throttle_n_per_chip != l_dimm_power_test_throttle_n_per_chip) + || + (l_runtime_throttle_d != l_dimm_power_test_throttle_d) + ) + { + l_rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA, + &l_target_mba_array[mba_index], l_dimm_power_test_throttle_n_per_mba); + if (l_rc) return l_rc; + l_rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP, + &l_target_mba_array[mba_index], l_dimm_power_test_throttle_n_per_chip); + if (l_rc) return l_rc; + l_rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR, + &l_target_mba_array[mba_index], l_dimm_power_test_throttle_d); + if (l_rc) return l_rc; + + } + } + } +*/ + FAPI_INF("*** %s COMPLETE ***", procedure_name); return l_rc; diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C index fdd424e2a..c6372259a 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training_advanced.C,v 1.36 2013/08/23 13:09:34 sasethur Exp $ +// $Id: mss_draminit_training_advanced.C,v 1.37 2013/09/04 08:50:49 lapietra Exp $ /* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */ //------------------------------------------------------------------------------ @@ -31,7 +31,7 @@ // *! TITLE :mss_draminit_training_advanced.C // *! DESCRIPTION : Tools for centaur procedures // *! OWNER NAME : Saravanan Sethuraman email ID:saravanans@in.ibm.com -// *! BACKUP NAME: Mark D Bellows email ID:bellows@us.ibm.com +// *! BACKUP NAME: Mark D Bellows email ID:bellows@us.ibm.com // #! ADDITIONAL COMMENTS : // // General purpose funcs @@ -74,8 +74,9 @@ // 1.32 | sasethur |04-Jun-13| Fixed for PortD cnfg, vref print for min setup, hold, fixed rdvref print, added set/reset mcbist attr // 1.33 | sasethur |12-Jun-13| Updated mcbist setup attribute // 1.34 | sasethur |20-Jun-13| Fixed read_vref print, setup attribute -// 1.35 | sasethur |08-Aug-13| Fixed fw comment. +// 1.35 | sasethur |08-Aug-13| Fixed fw comment // 1.36 | sasethur |23-Aug-13| Ability to run MCBIST is enabled. +// 1.37 | sasethur |04-Sep-13| Fixed fw review comment // This procedure Schmoo's DRV_IMP, SLEW, VREF (DDR, CEN), RCV_IMP based on attribute from effective config procedure @@ -84,7 +85,7 @@ // Internal Vref controlled by this function & external vref platform to provide function we return value // Not supported -// DDR4, DIMM Types +// DDR4, DIMM Types //---------------------------------------------------------------------- // Includes - FAPI //---------------------------------------------------------------------- @@ -1053,8 +1054,7 @@ fapi::ReturnCode set_attribute(const fapi::Target & i_target_mba) { fapi::ReturnCode rc; uint8_t l_mcbist_setup_multiple_set = 1; //Hard coded it wont change - FAPI_ATTR_SET(ATTR_SCHMOO_MULTIPLE_SETUP_CALL, &i_target_mba, l_mcbist_setup_multiple_set); - if (rc) return rc; + rc = FAPI_ATTR_SET(ATTR_SCHMOO_MULTIPLE_SETUP_CALL, &i_target_mba, l_mcbist_setup_multiple_set); return rc; } @@ -1067,8 +1067,7 @@ fapi::ReturnCode reset_attribute(const fapi::Target & i_target_mba) { fapi::ReturnCode rc; uint8_t l_mcbist_setup_multiple_reset = 0; //Hard coded it wont change - FAPI_ATTR_SET(ATTR_SCHMOO_MULTIPLE_SETUP_CALL, &i_target_mba, l_mcbist_setup_multiple_reset); - if (rc) return rc; + rc = FAPI_ATTR_SET(ATTR_SCHMOO_MULTIPLE_SETUP_CALL, &i_target_mba, l_mcbist_setup_multiple_reset); return rc; } diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C index 028486e1c..182452a34 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C @@ -21,7 +21,7 @@ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_generic_shmoo.C,v 1.66 2013/08/12 10:07:23 sasethur Exp $ +// $Id: mss_generic_shmoo.C,v 1.67 2013/09/04 09:21:33 sasethur Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -40,6 +40,7 @@ //------------------------------------------------------------------------------ // Version:|Author: | Date: | Comment: // --------|--------|---------|-------------------------------------------------- +// 1.67 |abhijit |4-sep-13 | fixed fw comments for the host boot // 1.65 |abhijit |8-aug-13 | added binary schmoo first phase and modified training call // 1.64 |abhijit |17-jul-13| added rd dqs phase 2 // 1.63 |abhijit |19-jun-13| fixed warnings in schmoo @@ -237,7 +238,7 @@ fapi::ReturnCode generic_shmoo::shmoo_save_rest(const fapi::Target & i_target,ui if(i_mode == 0) { FAPI_INF(" Saving DP18 data bit direction register contents"); - for(l_index = 0;l_index<9;l_index++) + for(l_index = 0;l_index<10;l_index++) { l_value = l_Databitdir[l_index]; rc = fapiGetScom(i_target,l_value,l_shmoo1ab); if(rc) return rc; @@ -252,7 +253,7 @@ fapi::ReturnCode generic_shmoo::shmoo_save_rest(const fapi::Target & i_target,ui else if(i_mode == 1) { FAPI_INF(" Restoring DP18 data bit direction register contents"); - for(l_index = 0;l_index<9;l_index++) + for(l_index = 0;l_index<10;l_index++) { l_val_u64 = i_content_array[l_index]; l_value = l_Databitdir[l_index]; diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C index 9584518d2..91e7ac74e 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_shmoo.C,v 1.7 2013/08/09 17:54:08 bellows Exp $ +// $Id: mss_eff_config_shmoo.C,v 1.8 2013/09/02 08:33:13 sasethur Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_shmoo.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -47,11 +47,14 @@ // 1.5 | sauchadh |15-May-13| Fixed FW comments // 1.6 | sauchadh |6-Jun-13 | Added some more attributes // 1.7 | bellows |09-Aug-13| Set default pattern to 0, per Sarvanan Req +// 1.8 | sauchadh |2- Sep-13| Added random seed attribute //---------------------------------------------------------------------- // My Includes //---------------------------------------------------------------------- + + //---------------------------------------------------------------------- // Includes //---------------------------------------------------------------------- @@ -115,6 +118,10 @@ fapi::ReturnCode mss_eff_config_shmoo(const fapi::Target & i_target_mba) { uint8_t mcb_user_rank=0; uint8_t mcb_user_bank=0; uint8_t shmoo_mul_setup_call=0; + uint32_t rand_seed_val=0; + uint8_t rand_seed_type=0x01; + + rc = FAPI_ATTR_SET(ATTR_MCBIST_PRINTING_DISABLE, &i_target_mba, mcb_print_disable); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_MCBIST_DATA_ENABLE, &i_target_mba, mcb_data_en); if(rc) return rc; @@ -161,6 +168,8 @@ fapi::ReturnCode mss_eff_config_shmoo(const fapi::Target & i_target_mba) { rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_ADDR_SCHMOO, &i_target_mba, cen_slew_rate_addr_schmoo); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CLK_SCHMOO, &i_target_mba, cen_slew_rate_clk_schmoo); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_SPCKE_SCHMOO, &i_target_mba, cen_slew_rate_spcke_schmoo); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_RANDOM_SEED_VALUE, &i_target_mba, rand_seed_val); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_RANDOM_SEED_TYPE, &i_target_mba, rand_seed_type); if(rc) return rc; |