diff options
| author | Yue Du <daviddu@us.ibm.com> | 2017-02-09 17:07:44 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-03-06 16:30:56 -0500 |
| commit | 9630c0f54dbac14cd848b3673f2556e72d273059 (patch) | |
| tree | 826761f9f76fee4fa2928089884bc662ee4ea954 /src | |
| parent | d0bc5a168223ce85d1f3810edc0a93608a18b4b6 (diff) | |
| download | talos-hostboot-9630c0f54dbac14cd848b3673f2556e72d273059.tar.gz talos-hostboot-9630c0f54dbac14cd848b3673f2556e72d273059.zip | |
Hcode: Create centralized memory map headers
findings and todos:
zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
redundant cpmr linker
not sure which one is in use
cme/link.cmd
cme/linkcpmr.cmd
cme/stop_cme/link_cpmr.cmd
sgpe/stop_gpe/link.cmd
sgpe/stop_gpe/linkqpmr.cmd
zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
redundant asm of cpmr and qpmr headers:
not sure which one is in use
file names are inconsistant and confusing
cme/p9_cpmr_header.S
cme/stop_cme/p9_cme_cpmr.S
cme/stop_cme/p9_cme_header.S
sgpe/p9_sgpe_qpmr.S
sgpe/stop_gpe/p9_sgpe_qpmr.S
sgpe/stop_gpe/p9_sgpe_image_header.S
zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
redundant edit programs
not sure which ones are still useful
contents are overlapping and out updated
(i.e. cme one still try to edit build date/ver)
cme/p9_cpmr_img_edit.C
cme/stop_cme/p9_cme_img_edit.c
cme/stop_cme/p9_cme_edit.mk
sgpe/p9_sgpe_img_edit.c
sgpe/stop_gpe/p9_sgpe_img_edit.c
sgpe/stop_gpe/p9_sgpe_edit.mk
zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
previous local makefiles
not sure if still useful
optional to keep or delete
cme/Makefile
cme/img_defs.mk
sgpe/Makefile
sgpe/img_defs.mk
sgpe/stop_gpe/Makefile
sgpe/stop_gpe/img_defs.mk
sgpe/boot/Makefile
sgpe/boot/img_defs.mk
zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
Change-Id: I94fbd28fc3e3c125e43232ea556a4e70b293db6d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36253
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36321
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
13 files changed, 3567 insertions, 3086 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_header_defs.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_header_defs.H index 0f02d3eee..49c814a46 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_header_defs.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_header_defs.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -23,8 +23,8 @@ /* */ /* IBM_PROLOG_END_TAG */ /// -/// @file p9_occ_sram_defs.H -/// @brief Constants defining the layout of the OCC SRAM +/// @file p9_hcd_header_defs.H +/// @brief defines header constants based on file types /// /// This header contains those cpp manifest constants required for processing /// the linker scripts used to generate OCC code images. As these are used @@ -32,11 +32,12 @@ /// into a namespace. Prefixing these with the region name is the attempt /// to make these globally unique when this header is included in C++ code. /// -// *HWP HWP Owner: Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner: Prem Jha <premjha2@in.ibm.com> -// *HWP Team: PM -// *HWP Level: 2 -// *HWP Consumed by: PM +// *HWP HWP Owner: David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner: Prem Jha <premjha2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: PM // #ifndef __HCD_HEADER_DEFS_H__ @@ -103,54 +104,49 @@ .endm // *INDENT-ON* -#undef CONST_UINT8_T -#undef CONST_UINT32_T -#undef CONST_UINT64_T - -#define CONST_UINT8_T(name, expr) .set name, expr -#define CONST_UINT16_T(name, expr) .set name, expr -#define CONST_UINT32_T(name, expr) .set name, expr -#define CONST_UINT64_T(name, expr) .set name, expr - #define ULL(x) x +#define HCD_CONST(name, expr) .set name, expr; +#define HCD_CONST64(name, expr) .set name, expr; #define HCD_HDR_UINT64(symbol, value) hcd_header_uint64 symbol value #define HCD_HDR_UINT32(symbol, value) hcd_header_uint32 symbol value #define HCD_HDR_UINT16(symbol, value) hcd_header_uint16 symbol value #define HCD_HDR_UINT8(symbol, value) hcd_header_uint8 symbol value #define HCD_HDR_UINT8_VEC(symbol, number, value) hcd_header_uint8_vec symbol number value - -#define HCD_HDR_ATTN(symbol, number) hcd_header_attn symbol number +#define HCD_HDR_ATTN(symbol, number) hcd_header_attn symbol number #define HCD_HDR_ATTN_PAD(align) hcd_header_attn_pad align #define HCD_HDR_PAD(align) hcd_header_pad align -#define HCD_MAGIC_NUMBER(symbol, value) .set symbol, value -#else // __ASSEMBLER__ +#else // NOT __ASSEMBLER__ -#undef CONST_UINT8_T -#undef CONST_UINT32_T -#undef CONST_UINT64_T +#ifdef __LINKERSCRIPT__ -#define CONST_UINT8_T(name, expr) static const uint8_t name = expr; -#define CONST_UINT16_T(name, expr) static const uint16_t name = expr; -#define CONST_UINT32_T(name, expr) static const uint32_t name = expr; -#define CONST_UINT64_T(name, expr) static const uint64_t name = expr; + #define ULL(x) x + #define POUND_DEFINE #define + #define HCD_CONST(name, expr) POUND_DEFINE name expr + #define HCD_CONST64(name, expr) POUND_DEFINE name expr -#define ULL(x) x##ull +#else -#define HCD_HDR_UINT64(symbol, value) uint64_t symbol -#define HCD_HDR_UINT32(symbol, value) uint32_t symbol -#define HCD_HDR_UINT16(symbol, value) uint16_t symbol -#define HCD_HDR_UINT8(symbol, value) uint8_t symbol -#define HCD_HDR_UINT8_VEC(symbol, number, value) uint8_t symbol[number] -#define HCD_HDR_ATTN(symbol, number) uint32_t symbol[number] -#define HCD_HDR_ATTN_PAD(align) -#define HCD_HDR_PAD(align) -#define HCD_MAGIC_NUMBER(symbol, value) static const uint64_t symbol = value + #define ULL(x) x##ull + #define HCD_CONST(name, expr) enum { name = expr }; + #define HCD_CONST64(name, expr) enum { name = expr }; + #define HCD_HDR_UINT64(symbol, value) uint64_t symbol + #define HCD_HDR_UINT32(symbol, value) uint32_t symbol + #define HCD_HDR_UINT16(symbol, value) uint16_t symbol + #define HCD_HDR_UINT8(symbol, value) uint8_t symbol + #define HCD_HDR_UINT8_VEC(symbol, number, value) uint8_t symbol[number] + #define HCD_HDR_ATTN(symbol, number) uint32_t symbol[number] + #define HCD_HDR_ATTN_PAD(align) + #define HCD_HDR_PAD(align) + +#endif // __LINKERSCRIPT__ #endif // __ASSEMBLER__ +// Stringification + #define STR_HELPER(x) #x #define STR(x) STR_HELPER(x) -#endif // __HCD_HEADER_DEFS_H__ +#endif // __HCD_HEADER_DEFS_H__ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H new file mode 100644 index 000000000..be75c06a0 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -0,0 +1,480 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_memmap_base.H +/// @brief defines region constants shared by different memory components. +/// + +// *HWP HWP Owner: David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner: Prem S Jha <premjha2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: PM:Hostboot:Phyp + +#ifndef __HCD_MEMMAP_BASE_H__ +#define __HCD_MEMMAP_BASE_H__ + +#include <p9_hcd_header_defs.H> + +// ------------------------------------------------------------------- +// Note: There can be NO semicolons(";") at end of macros in this file +// There can ONLY have HCD_CONST/HCD_CONST64 macros in this file +// ------------------------------------------------------------------- + +/// Image Magic Numbers + +HCD_CONST64(CPMR_MAGIC_NUMBER, ULL(0x43504d525f312e30)) // CPMR_1.0 +HCD_CONST64(CME_MAGIC_NUMBER , ULL(0x434d455f5f312e30)) // CME__1.0 + +HCD_CONST64(QPMR_MAGIC_NUMBER, ULL(0x51504d525f312e30)) // QPMR_1.0 +HCD_CONST64(SGPE_MAGIC_NUMBER, ULL(0x534750455f312e30)) // SGPE_1.0 + +HCD_CONST64(PPMR_MAGIC_NUMBER, ULL(0x50504d525f312e30)) // PPMR_1.0 +HCD_CONST64(PGPE_MAGIC_NUMBER, ULL(0x504750455F312E30)) // PGPE_1.0 + +HCD_CONST(CME_BUILD_VERSION, 0x001) // CME__1.0 +HCD_CONST(SGPE_BUILD_VERSION, 0x001) // SGPE_1.0 +HCD_CONST(PGPE_BUILD_VERSION, 0x001) // PGPE_1.0 + +/// Size constants + +HCD_CONST(HALF_KB, 512) +HCD_CONST(ONE_KB, 1024) +HCD_CONST(HALF_MB, (1024 * 512)) +HCD_CONST(ONE_MB, (1024 * 1024)) +HCD_CONST(TWO_MB, (2 * 1024 * 1024)) + +/// Memory constants + +HCD_CONST(CME_SRAM_SIZE, (32 * ONE_KB)) +HCD_CONST(OCC_SRAM_SIZE, (768 * ONE_KB)) + +HCD_CONST(HOMER_MEMORY_SIZE, (4 * ONE_MB)) +HCD_CONST(HOMER_OPMR_REGION_NUM, 0) +HCD_CONST(HOMER_QPMR_REGION_NUM, 1) +HCD_CONST(HOMER_CPMR_REGION_NUM, 2) +HCD_CONST(HOMER_PPMR_REGION_NUM, 3) + +/// Chip constants + +HCD_CONST(MAX_THREADS_PER_CORE, 4) +HCD_CONST(MAX_CORES_PER_CHIP, 24) + +HCD_CONST(MAX_CMES_PER_CHIP, 12) +HCD_CONST(MAX_EXES_PER_CHIP, 12) + +HCD_CONST(MAX_QUADS_PER_CHIP, 6) +HCD_CONST(MAX_CACHES_PER_CHIP, 6) + +HCD_CONST(MAX_CORES_PER_CME, 2) +HCD_CONST(MAX_CORES_PER_EX, 2) + +HCD_CONST(MAX_CMES_PER_QUAD, 2) +HCD_CONST(MAX_EXES_PER_QUAD, 2) + +HCD_CONST(CACHE0_CHIPLET_ID, 0x10) +HCD_CONST(CACHE_CHIPLET_ID_MIN, 0x10) +HCD_CONST(CACHE_CHIPLET_ID_MAX, 0x15) + +HCD_CONST(CORE0_CHIPLET_ID, 0x20) +HCD_CONST(CORE_CHIPLET_ID_MIN, 0x20) +HCD_CONST(CORE_CHIPLET_ID_MAX, 0x37) + +HCD_CONST(MAX_QUAD_ID_SUPPORTED, 5) +HCD_CONST(MAX_CORE_ID_SUPPORTED, 23) +HCD_CONST(MAX_THREAD_ID_SUPPORTED, 3) + +/// Image build constants + +HCD_CONST(HARDWARE_IMG_SIZE, ONE_MB) + +HCD_CONST(FUSED_CORE_MODE, 0xBB) +HCD_CONST(NONFUSED_CORE_MODE, 0xAA) + +HCD_CONST(SELF_RESTORE_BLR_INST, 0x4e800020) +HCD_CONST(CORE_RESTORE_PAD_OPCODE, 0x00000200) //ATTN Opcode + +HCD_CONST(SCOM_RESTORE_PAD_OPCODE, 0x00000000) //zero pads +HCD_CONST(SCOM_RESTORE_ENTRY_SIZE, 16) //4B pad,4B address,8B data + +HCD_CONST(CME_BLOCK_READ_LEN, 32) +HCD_CONST(CME_BLK_SIZE_SHIFT, 0x05) + +HCD_CONST(RING_ALIGN_BOUNDARY, 0x08) +HCD_CONST64(DARN_BAR_EN_POS, ULL(0x8000000000000000)) + +//--------------------------------------------------------------------------------------- + +/// OPMR + +HCD_CONST(OCC_HOST_AREA_SIZE, ONE_MB) +HCD_CONST(OPMR_OCC_IMAGE_SIZE, HALF_MB) +HCD_CONST(OPMR_HOST_AREA_SIZE, HALF_MB) + +//--------------------------------------------------------------------------------------- + +/// QPMR Header + +HCD_CONST(QPMR_HOMER_OFFSET, (HOMER_QPMR_REGION_NUM* ONE_MB)) +HCD_CONST(QPMR_HEADER_SIZE, 512) + +HCD_CONST(QPMR_MAGIC_NUMBER_BYTE, 0x00) +HCD_CONST(QPMR_BOOT_COPIER_OFFSET_BYTE, 0x08) +HCD_CONST(QPMR_BOOT_LOADER_OFFSET_BYTE, 0x10) +HCD_CONST(QPMR_BOOT_LOADER_LENGTH_BYTE, 0x14) +HCD_CONST(QPMR_BUILD_DATE_BYTE, 0x18) +HCD_CONST(QPMR_BUILD_VER_BYTE, 0x1C) +HCD_CONST(QPMR_SGPE_HCODE_OFFSET_BYTE, 0x28) +HCD_CONST(QPMR_SGPE_HCODE_LENGTH_BYTE, 0x2C) +HCD_CONST(QPMR_QUAD_COMMON_RINGS_OFFSET_BYTE, 0x30) +HCD_CONST(QPMR_QUAD_COMMON_RINGS_LENGTH_BYTE, 0x34) +HCD_CONST(QPMR_QUAD_OVERRIDE_RINGS_OFFSET_BYTE, 0x38) +HCD_CONST(QPMR_QUAD_OVERRIDE_RINGS_LENGTH_BYTE, 0x3C) +HCD_CONST(QPMR_QUAD_SPECIFIC_RINGS_OFFSET_BYTE, 0x40) +HCD_CONST(QPMR_QUAD_SPECIFIC_RINGS_LENGTH_BYTE, 0x44) +HCD_CONST(QPMR_QUAD_SCOM_RESTORE_OFFSET_BYTE, 0x48) +HCD_CONST(QPMR_QUAD_SCOM_RESTORE_LENGTH_BYTE, 0x4C) +HCD_CONST(QPMR_24x7_DATA_OFFSET_BYTE, 0x50) +HCD_CONST(QPMR_24x7_DATA_LENGTH_BYTE, 0x54) +HCD_CONST(QPMR_STOP_FFDC_OFFSET_BYTE, 0x58) +HCD_CONST(QPMR_STOP_FFDC_LENGTH_BYTE, 0x5C) + +/// SGPE Boot + +HCD_CONST(SGPE_BOOT_COPIER_QPMR_OFFSET, QPMR_HEADER_SIZE) +HCD_CONST(SGPE_BOOT_COPIER_SIZE, ONE_KB) + +HCD_CONST(SGPE_BOOT_LOADER_QPMR_OFFSET, + (SGPE_BOOT_COPIER_QPMR_OFFSET + SGPE_BOOT_COPIER_SIZE)) +HCD_CONST(SGPE_BOOT_LOADER_SIZE, ONE_KB) +HCD_CONST(SGPE_BOOT_LOADER_RESET_ADDR_VAL, 0x40) + +HCD_CONST(SGPE_INSTRUMENTATION_SIZE, (2 * ONE_KB)) + +/// SGPE Image + +HCD_CONST(SGPE_IMAGE_QPMR_OFFSET, + (SGPE_BOOT_LOADER_QPMR_OFFSET + SGPE_BOOT_LOADER_SIZE)) +HCD_CONST(SGPE_IMAGE_SIZE, (80 * ONE_KB)) +HCD_CONST(SGPE_INT_VECTOR_SIZE, 384) +HCD_CONST(SGPE_HCODE_RESET_ADDR_VAL, 0x40) + +/// SGPE Header + +HCD_CONST(SGPE_HEADER_QPMR_OFFSET, + (SGPE_IMAGE_QPMR_OFFSET + SGPE_INT_VECTOR_SIZE)) +HCD_CONST(SGPE_HEADER_IMAGE_OFFSET, SGPE_INT_VECTOR_SIZE) +HCD_CONST(SGPE_HEADER_SIZE, 128) + +HCD_CONST(SGPE_MAGIC_NUMBER_BYTE, 0x00) +HCD_CONST(SGPE_SYSTEM_RESET_ADDR_BYTE, 0x08) +HCD_CONST(SGPE_IVPR_ADDR_BYTE, 0x10) +HCD_CONST(SGPE_BUILD_DATE_BYTE, 0x18) +HCD_CONST(SGPE_BUILD_VER_BYTE, 0x1C) +HCD_CONST(SGPE_STOP_FLAGS_BYTE, 0x20) +HCD_CONST(SGPE_LOCATION_ID_BYTE, 0x24) +HCD_CONST(SGPE_QUAD_COMMON_RING_SRAM_OFF_BYTE, 0x28) +HCD_CONST(SGPE_QUAD_OVERRIDE_RING_SRAM_OFF_BYTE, 0x2C) +HCD_CONST(SGPE_QUAD_SPECIFIC_RING_SRAM_OFF_BYTE, 0x30) +HCD_CONST(SGPE_QUAD_SCOM_RESTORE_SRAM_OFF_BYTE, 0x34) +HCD_CONST(SGPE_QUAD_SCOM_RESTORE_MEM_OFF_BYTE, 0x38) +HCD_CONST(SGPE_QUAD_SCOM_RESTORE_LENGTH_BYTE, 0x3C) +HCD_CONST(SGPE_24x7_DATA_OFFSET_BYTE, 0x40) +HCD_CONST(SGPE_24x7_DATA_LENGTH_BYTE, 0x44) +HCD_CONST(PGPE_24x7_CTRL_BYTE, 0x48) + +HCD_CONST(SGPE_RESET_ADDR_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_SYSTEM_RESET_ADDR_BYTE)) +HCD_CONST(SGPE_BUILD_DATE_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_BUILD_DATE_BYTE)) +HCD_CONST(SGPE_BUILD_VER_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_BUILD_VER_BYTE)) + +HCD_CONST(SGPE_STOP_4_TO_2_BIT_POS, 0x80000000) +HCD_CONST(SGPE_STOP_5_TO_4_BIT_POS, 0x40000000) +HCD_CONST(SGPE_STOP_8_TO_5_BIT_POS, 0x20000000) +HCD_CONST(SGPE_STOP_11_TO_8_BIT_POS, 0x10000000) +HCD_CONST(SGPE_PROC_FAB_ADDR_BAR_MODE_POS, 0x00008000) + +/// SGPE Hcode + +HCD_CONST(SGPE_HCODE_IMAGE_OFFSET, (SGPE_INT_VECTOR_SIZE + SGPE_HEADER_SIZE)) +HCD_CONST(SGPE_HCODE_SIZE, ((45 * ONE_KB) + HALF_KB)) //RTC158543 +HCD_CONST(SGPE_DEBUG_PTRS_OFFSET, 0x200) +HCD_CONST(SGPE_DEBUG_PTRS_SIZE, 0x24) +HCD_CONST(SGPE_DBG_PTR_AREA_SIZE, 64) + +/// Quad Scan + +// 400B * 9 rings * 3 types (base, RL, CC) +HCD_CONST(QUAD_COMMON_RING_SIZE, (13 * ONE_KB)) +// 300B * 9 rings +HCD_CONST(QUAD_OVERRIDE_RING_SIZE, (3 * ONE_KB)) +// 1KB/ring * 5 rings/cache +HCD_CONST(QUAD_SPECIFIC_RING_SIZE_PER_QUAD, ((3 * ONE_KB) + HALF_KB)) +HCD_CONST(QUAD_SPECIFIC_RING_SIZE_TOTAL, (19 * ONE_KB)) //checkme? + +/// Quad Scom + +HCD_CONST(QUAD_SCOM_RESTORE_QPMR_OFFSET, (128 * ONE_KB)) +HCD_CONST(QUAD_SCOM_RESTORE_HOMER_OFFSET, + (QUAD_SCOM_RESTORE_QPMR_OFFSET + QPMR_HOMER_OFFSET)) + +HCD_CONST(MAX_L2_SCOM_ENTRIES, 16) +HCD_CONST(MAX_L3_SCOM_ENTRIES, 16) +HCD_CONST(MAX_EQ_SCOM_ENTRIES, 15) +HCD_CONST(QUAD_SCOM_RESTORE_REGS_PER_QUAD, + (MAX_EQ_SCOM_ENTRIES + MAX_L2_SCOM_ENTRIES + MAX_L3_SCOM_ENTRIES + 1)) + +HCD_CONST(QUAD_SCOM_RESTORE_SIZE_PER_QUAD, + (SCOM_RESTORE_ENTRY_SIZE* QUAD_SCOM_RESTORE_REGS_PER_QUAD)) + +HCD_CONST(QUAD_SCOM_RESTORE_SIZE_TOTAL, (6 * ONE_KB)) //rounded to 6KB + +//--------------------------------------------------------------------------------------- + +/// CPMR Header + +HCD_CONST(CPMR_HOMER_OFFSET, (HOMER_CPMR_REGION_NUM* ONE_MB)) +HCD_CONST(CPMR_HEADER_SIZE, 256) + +HCD_CONST(CPMR_ATTN_WORD0_BYTE, 0x00) +HCD_CONST(CPMR_ATTN_WORD1_BYTE, 0x04) +HCD_CONST(CPMR_MAGIC_NUMBER_BYTE, 0x08) +HCD_CONST(CPMR_BUILD_DATE_BYTE, 0x10) +HCD_CONST(CPMR_BUILD_VER_BYTE, 0x14) +HCD_CONST(CPMR_CME_HCODE_OFFSET_BYTE, 0x20) +HCD_CONST(CPMR_CME_HCODE_LENGTH_BYTE, 0x24) +HCD_CONST(CPMR_CORE_COMMON_RING_OFFSET_BYTE, 0x28) +HCD_CONST(CPMR_CORE_COMMON_RING_LENGTH_BYTE, 0x2C) +HCD_CONST(CPMR_CME_LOCAL_PSTATE_OFFSET_BYTE, 0x30) +HCD_CONST(CPMR_CME_LOCAL_PSTATE_LENGTH_BYTE, 0x34) +HCD_CONST(CPMR_CORE_SPECIFIC_RING_OFFSET_BYTE, 0x38) +HCD_CONST(CPMR_CORE_SPECIFIC_RING_LENGTH_BYTE, 0x3C) +HCD_CONST(CPMR_CORE_SCOM_RESTORE_OFFSET_BYTE, 0x40) +HCD_CONST(CPMR_CORE_SCOM_RESTORE_LENGTH_BYTE, 0x44) +HCD_CONST(CPMR_SELF_RESTORE_OFFSET_BYTE, 0x48) +HCD_CONST(CPMR_SELF_RESTORE_LENGTH_BYTE, 0x4C) + +/// Self Restore + +HCD_CONST(SELF_RESTORE_CPMR_OFFSET, CPMR_HEADER_SIZE) +HCD_CONST(SELF_RESTORE_INT_SIZE, (8 * ONE_KB)) +HCD_CONST(THREAD_LAUNCHER_SIZE, 256) +HCD_CONST(SELF_RESTORE_CODE_SIZE, + (SELF_RESTORE_INT_SIZE + THREAD_LAUNCHER_SIZE)) + +HCD_CONST(CORE_RESTORE_THREAD_AREA_SIZE, (ONE_KB)) +HCD_CONST(CORE_RESTORE_CORE_AREA_SIZE, (ONE_KB)) +HCD_CONST(CORE_RESTORE_SIZE_PER_THREAD, + (CORE_RESTORE_THREAD_AREA_SIZE + CORE_RESTORE_CORE_AREA_SIZE)) +HCD_CONST(SELF_RESTORE_CORE_REGS_SIZE, + (CORE_RESTORE_SIZE_PER_THREAD* + MAX_THREADS_PER_CORE* MAX_CORES_PER_CHIP)) + +HCD_CONST(SELF_RESTORE_SIZE_TOTAL, + (SELF_RESTORE_CODE_SIZE + SELF_RESTORE_CORE_REGS_SIZE)) + + +/// Core Scom + +HCD_CONST(CORE_SCOM_RESTORE_CPMR_OFFSET, (256 * ONE_KB)) +HCD_CONST(CORE_SCOM_RESTORE_HOMER_OFFSET, + (CORE_SCOM_RESTORE_CPMR_OFFSET + CPMR_HOMER_OFFSET)) + +HCD_CONST(MAX_CORE_SCOM_ENTRIES, 15) +HCD_CONST(CORE_SCOM_RESTORE_REGS_PER_CORE, (MAX_CORE_SCOM_ENTRIES + 1)) + +HCD_CONST(CORE_SCOM_RESTORE_SIZE_PER_CORE, + (SCOM_RESTORE_ENTRY_SIZE* CORE_SCOM_RESTORE_REGS_PER_CORE)) // 16*16=256 +HCD_CONST(CORE_SCOM_RESTORE_SIZE_PER_CME, + (CORE_SCOM_RESTORE_SIZE_PER_CORE* MAX_CORES_PER_CME)) // 256*2=512 + +HCD_CONST(CORE_SCOM_RESTORE_SIZE_TOTAL, + (CORE_SCOM_RESTORE_SIZE_PER_CME* MAX_CMES_PER_CHIP)) // 512*12=6K + +/// CME Image + +HCD_CONST(CME_IMAGE_CPMR_OFFSET, + (CORE_SCOM_RESTORE_CPMR_OFFSET + CORE_SCOM_RESTORE_SIZE_TOTAL)) +//HCD_CONST(CME_IMAGE_SIZE, 0) +HCD_CONST(CME_INT_VECTOR_SIZE, 384) + +/// CME Header + +HCD_CONST(CME_HEADER_CPMR_OFFSET, + (CME_IMAGE_CPMR_OFFSET + CME_INT_VECTOR_SIZE)) +HCD_CONST(CME_HEADER_IMAGE_OFFSET, CME_INT_VECTOR_SIZE) +HCD_CONST(CME_HEADER_SIZE, 128) + +HCD_CONST(CME_MAGIC_NUMBER_BYTE, 0x00) +HCD_CONST(CME_HCODE_OFFSET_BYTE, 0x08) +HCD_CONST(CME_HCODE_LENGTH_BYTE, 0x0C) +HCD_CONST(CME_CORE_COMMON_RING_OFFSET_BYTE, 0x10) +HCD_CONST(CME_CORE_OVERRIDE_RING_OFFSET_BYTE, 0x14) +HCD_CONST(CME_CORE_COMMON_RING_LENGTH_BYTE, 0x18) +HCD_CONST(CME_LOCAL_PSTATE_OFFSET_BYTE, 0x1C) +HCD_CONST(CME_LOCAL_PSTATE_LENGTH_BYTE, 0x20) +HCD_CONST(CME_CORE_SPECIFIC_RING_OFFSET_BYTE, 0x24) +HCD_CONST(CME_CORE_SPECIFIC_RING_LENGTH_BYTE, 0x28) +HCD_CONST(CME_CORE_SCOM_RESTORE_OFFSET_BYTE, 0x2C) +HCD_CONST(CME_CORE_SCOM_RESTORE_LENGTH_BYTE, 0x30) +HCD_CONST(CME_STOP_FLAGS_BYTE, 0x34) +HCD_CONST(CME_LOCATION_ID_BYTE, 0x38) +HCD_CONST(CME_QM_FLAGS_BYTE, 0x3A) +HCD_CONST(CME_HOMER_ADDRESS_BYTE, 0x40) + +HCD_CONST(CME_HCODE_OFF_IMAGE_OFFSET, (CME_HEADER_IMAGE_OFFSET + CME_HCODE_OFFSET_BYTE)) +HCD_CONST(CME_HCODE_LEN_IMAGE_OFFSET, (CME_HEADER_IMAGE_OFFSET + CME_HCODE_LENGTH_BYTE)) + +HCD_CONST(CME_STOP_3_TO_2_BIT_POS, 0x80000000) +HCD_CONST(CME_STOP_4_TO_2_BIT_POS, 0x40000000) +HCD_CONST(CME_STOP_5_TO_4_BIT_POS, 0x20000000) +HCD_CONST(CME_STOP_8_TO_5_BIT_POS, 0x10000000) +HCD_CONST(CME_STOP_11_TO_8_BIT_POS, 0x08000000) +HCD_CONST(CME_SKIP_CORE_POWEROFF_BIT_POS, 0x00000001) + +/// CME Hcode + +HCD_CONST(CME_HCODE_IMAGE_OFFSET, (CME_INT_VECTOR_SIZE + CME_HEADER_SIZE)) +//HCD_CONST(CME_HCODE_SIZE, 0) +HCD_CONST(CME_DEBUG_PTRS_OFFSET, 0x200) +HCD_CONST(CME_DEBUG_PTRS_SIZE, 0x24) +HCD_CONST(CME_INSTRUMENTATION_SIZE, HALF_KB) +HCD_CONST(CME_SRAM_HCODE_OFFSET, 0) + +/// Core Scan + +HCD_CONST(CORE_COMMON_RING_SIZE, (2 * ONE_KB)) +HCD_CONST(CORE_OVERRIDE_RING_SIZE, (1 * ONE_KB)) +HCD_CONST(CORE_SPECIFIC_RING_SIZE_PER_CORE, (1 * ONE_KB)) +HCD_CONST(CORE_SPECIFIC_RING_SIZE_TOTAL, (32 * ONE_KB)) // rounded to 32K + +/// Quad P-State + +HCD_CONST(CME_QUAD_PSTATE_SIZE, HALF_KB) + +// CME Hcode + Core Scan + Pstate + +HCD_CONST(CME_REGION_SIZE, (64 * ONE_KB)) + +//--------------------------------------------------------------------------------------- + +/// PPMR Header + +HCD_CONST(PPMR_HOMER_OFFSET, (HOMER_PPMR_REGION_NUM* ONE_MB)) +HCD_CONST(PPMR_HEADER_SIZE, 512) + +HCD_CONST(PPMR_MAGIC_NUMBER_BYTE, 0x00) +HCD_CONST(PPMR_BOOT_COPIER_OFFSET_BYTE, 0x08) +HCD_CONST(PPMR_BOOT_LOADER_OFFSET_BYTE, 0x10) +HCD_CONST(PPMR_BOOT_LOADER_LENGTH_BYTE, 0x14) +HCD_CONST(PPMR_BUILD_DATE_BYTE, 0x18) +HCD_CONST(PPMR_BUILD_VER_BYTE, 0x1C) +HCD_CONST(PPMR_PGPE_HCODE_OFFSET_BYTE, 0x28) +HCD_CONST(PPMR_PGPE_HCODE_LENGTH_BYTE, 0x2C) +HCD_CONST(PPMR_GLOBAL_PSTATE_OFFSET_BYTE, 0x30) +HCD_CONST(PPMR_GLOBAL_PSTATE_LENGTH_BYTE, 0x34) +HCD_CONST(PPMR_LOCAL_PSTATE_OFFSET_BYTE, 0x38) +HCD_CONST(PPMR_LOCAL_PSTATE_LENGTH_BYTE, 0x3C) +HCD_CONST(PPMR_OCC_PSTATE_OFFSET_BYTE, 0x40) +HCD_CONST(PPMR_OCC_PSTATE_LENGTH_BYTE, 0x44) +HCD_CONST(PPMR_PSTATE_TABLE_OFFSET_BYTE, 0x48) +HCD_CONST(PPMR_PSTATE_TABLE_LENGTH_BYTE, 0x4C) +HCD_CONST(PPMR_PGPE_SRAM_IMAGE_SIZE_BYTE, 0x50) +HCD_CONST(PPMR_PGPE_BOOT_PROG_CODE_BYTE, 0x54) + +/// PGPE Boot + +HCD_CONST(PGPE_BOOT_COPIER_PPMR_OFFSET, PPMR_HEADER_SIZE) +HCD_CONST(PGPE_BOOT_COPIER_SIZE, ONE_KB) + +HCD_CONST(PGPE_BOOT_LOADER_PPMR_OFFSET, + (PGPE_BOOT_COPIER_PPMR_OFFSET + PGPE_BOOT_COPIER_SIZE)) +HCD_CONST(PGPE_BOOT_LOADER_SIZE, ONE_KB) +HCD_CONST(PGPE_BOOT_LOADER_RESET_ADDR_VAL, 0x40) + +HCD_CONST(PGPE_INSTRUMENTATION_SIZE, (2 * ONE_KB)) + +/// PGPE Image + +HCD_CONST(PGPE_IMAGE_PPMR_OFFSET, + (PGPE_BOOT_LOADER_PPMR_OFFSET + PGPE_BOOT_LOADER_SIZE)) +HCD_CONST(PGPE_IMAGE_SIZE, (48 * ONE_KB)) //RTC 158543 +HCD_CONST(PGPE_INT_VECTOR_SIZE, 384) +HCD_CONST(PGPE_HCODE_RESET_ADDR_VAL, 0x40) + +/// PGPE Header + +HCD_CONST(PGPE_HEADER_IMAGE_OFFSET, PGPE_INT_VECTOR_SIZE) +HCD_CONST(PGPE_HEADER_PPMR_OFFSET, + (PGPE_IMAGE_PPMR_OFFSET + PGPE_INT_VECTOR_SIZE)) +HCD_CONST(PGPE_HEADER_SIZE, 128) + +HCD_CONST(PGPE_MAGIC_NUMBER_BYTE, 0x00) +HCD_CONST(PGPE_SYSTEM_RESET_ADDR_BYTE, 0x08) +HCD_CONST(PGPE_SHARED_SRAM_ADDR_BYTE, 0x0C) +HCD_CONST(PGPE_IVPR_ADDR_BYTE, 0x10) +HCD_CONST(PGPE_SHARED_SRAM_LENGTH_BYTE, 0x14) +HCD_CONST(PGPE_BUILD_DATE_BYTE, 0x18) +HCD_CONST(PGPE_BUILD_VER_BYTE, 0x1C) +HCD_CONST(PGPE_PGPE_FLAGS_BYTE, 0x20) +HCD_CONST(PGPE_GLOBAL_PSTATE_SRAM_ADDR_BYTE, 0x28) +HCD_CONST(PGPE_GLOBAL_PSTATE_MEM_OFFSET_BYTE, 0x30) +HCD_CONST(PGPE_GLOBAL_PSTATE_PPB_SIZE_BYTE, 0x34) +HCD_CONST(PGPE_GEN_PSTATE_TABLE_MEM_OFFSET_BYTE, 0x38) +HCD_CONST(PGPE_GEN_PSTATE_TABLE_SIZE_BYTE, 0x3C) +HCD_CONST(PGPE_OCC_PSTATE_TABLE_MEM_OFFSET_BYTE, 0x40) +HCD_CONST(PGPE_OCC_PSTATE_TABLE_SIZE_BYTE, 0x44) +HCD_CONST(PGPE_BEACON_ADDR_BYTE, 0x48) +HCD_CONST(PGPE_ACTUAL_QUAD_STATUS_ADDR_BYTE, 0x4C) +HCD_CONST(PGPE_WOF_TABLE_ADDR_BYTE, 0x50) +HCD_CONST(PGPE_WOF_TABLE_LENGTH_BYTE, 0x54) + +HCD_CONST(PGPE_RESET_ADDR_IMAGE_OFFSET, (PGPE_HEADER_IMAGE_OFFSET + PGPE_SYSTEM_RESET_ADDR_BYTE)) +HCD_CONST(PGPE_BUILD_DATE_IMAGE_OFFSET, (PGPE_HEADER_IMAGE_OFFSET + PGPE_BUILD_DATE_BYTE)) +HCD_CONST(PGPE_BUILD_VER_IMAGE_OFFSET, (PGPE_HEADER_IMAGE_OFFSET + PGPE_BUILD_VER_BYTE)) + +/// PGPE Hcode + +//HCD_CONST(PGPE_HCODE_SIZE, (32 * ONE_KB)) //RTC 158543 +HCD_CONST(PGPE_DBG_PTR_AREA_SIZE, 64) +HCD_CONST(PGPE_GLOBAL_PSTATE_PARAM_BLOCK_SIZE, (4 * ONE_KB)) + +/// Pstate Parameter Block + Pstate Table + +HCD_CONST(OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET, (128 * ONE_KB)) +HCD_CONST(OCC_PSTATE_PARAM_BLOCK_SIZE, (8 * ONE_KB)) +HCD_CONST(OCC_PSTATE_PARAM_BLOCK_REGION_SIZE, (16 * ONE_KB)) + +HCD_CONST(PGPE_PSTATE_OUTPUT_TABLES_PPMR_OFFSET, (144 * ONE_KB)) +HCD_CONST(PGPE_PSTATE_OUTPUT_TABLES_SIZE, (8 * ONE_KB)) +HCD_CONST(PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE, (16 * ONE_KB)) + +HCD_CONST(OCC_WOF_TABLES_PPMR_OFFSET, (768 * ONE_KB)) +HCD_CONST(OCC_WOF_TABLES_SIZE, (256 * ONE_KB)) + +HCD_CONST(PGPE_IMAGE_RESERVE_SIZE, + (OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET - PGPE_IMAGE_PPMR_OFFSET - PGPE_IMAGE_SIZE)) + +#endif /* __HCD_MEMMAP_BASE_H__ */ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_cme_sram.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_cme_sram.H new file mode 100644 index 000000000..6bf3e9764 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_cme_sram.H @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_cme_sram.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_memmap_cme_sram.H +/// @brief defines region constants of cme sram. +/// + +// *HWP HWP Owner: David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner: Prem S Jha <premjha2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: PM:Hostboot: Phyp + +#ifndef __P9_HCD_MEMMAP_CME_SRAM_H__ +#define __P9_HCD_MEMMAP_CME_SRAM_H__ + +#include <p9_hcd_header_defs.H> +#include <p9_hcd_memmap_base.H> + +// ------------------------------------------------------------------- +// Note: There can be NO semicolons(";") at end of macros in this file +// There can ONLY have HCD_CONST/HCD_CONST64 macros in this file +// ------------------------------------------------------------------- + +HCD_CONST(CME_SRAM_BASE_ADDR, 0xFFFF8000) +HCD_CONST(CME_SRAM_HEADER_ADDR, + (CME_SRAM_BASE_ADDR + CME_INT_VECTOR_SIZE)) + +#endif /* __P9_HCD_MEMMAP_CME_SRAM_H__ */ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H new file mode 100644 index 000000000..2e59b3620 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H @@ -0,0 +1,88 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_memmap_homer.H +/// @brief defines region constants of homer. +/// + +// *HWP HWP Owner: David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner: Prem S Jha <premjha2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: PM:Hostboot:Phyp + +#ifndef __P9_HCD_MEMMAP_HOMER_H__ +#define __P9_HCD_MEMMAP_HOMER_H__ + +#include <p9_hcd_header_defs.H> +#include <p9_hcd_memmap_base.H> + +// ------------------------------------------------------------------- +// Note: There can be NO semicolons(";") at end of macros in this file +// There can ONLY have HCD_CONST/HCD_CONST64 macros in this file +//-------------------------------------------------------------------- + +/// HOMER + +HCD_CONST(HOMER_BASE_ADDR, 0x80000000) + +/// QPMR + +HCD_CONST(HOMER_QPMR_BASE_ADDR, (HOMER_BASE_ADDR + (QPMR_HOMER_OFFSET))) +HCD_CONST(HOMER_QPMR_HEADER_ADDR, HOMER_QPMR_BASE_ADDR) +HCD_CONST(HOMER_SGPE_BOOT_LOADER_OFFSET_ADDR, + (HOMER_QPMR_HEADER_ADDR + QPMR_BOOT_LOADER_OFFSET_BYTE)) +HCD_CONST(HOMER_SGPE_BOOT_LOADER_LENGTH_ADDR, + (HOMER_QPMR_HEADER_ADDR + QPMR_BOOT_LOADER_LENGTH_BYTE)) +HCD_CONST(HOMER_SGPE_BOOT_COPIER_ADDR, + (HOMER_QPMR_HEADER_ADDR + QPMR_HEADER_SIZE)) + + +/// CPMR + +HCD_CONST(HOMER_CPMR_BASE_ADDR, (HOMER_BASE_ADDR + (CPMR_HOMER_OFFSET))) +HCD_CONST(HOMER_CPMR_HEADER_ADDR, HOMER_CPMR_BASE_ADDR) + + +/// PPMR + +HCD_CONST(HOMER_PPMR_BASE_ADDR, (HOMER_BASE_ADDR + (PPMR_HOMER_OFFSET))) +HCD_CONST(HOMER_PPMR_HEADER_ADDR, HOMER_PPMR_BASE_ADDR) +HCD_CONST(HOMER_PGPE_BOOT_LOADER_OFFSET_ADDR, + (HOMER_PPMR_HEADER_ADDR + PPMR_BOOT_LOADER_OFFSET_BYTE)) +HCD_CONST(HOMER_PGPE_BOOT_LOADER_LENGTH_ADDR, + (HOMER_PPMR_HEADER_ADDR + PPMR_BOOT_LOADER_LENGTH_BYTE)) +HCD_CONST(HOMER_PGPE_BOOT_COPIER_ADDR, + (HOMER_PPMR_HEADER_ADDR + PPMR_HEADER_SIZE)) + +HCD_CONST(HOMER_OCC_PSTATE_PARAM_BLOCK_ADDR, + (HOMER_PPMR_BASE_ADDR + OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET)); +HCD_CONST(HOMER_PGPE_PSTATE_OUTPUT_TABLES_ADDR, + (HOMER_PPMR_BASE_ADDR + PGPE_PSTATE_OUTPUT_TABLES_PPMR_OFFSET)); +HCD_CONST(HOMER_OCC_WOF_TABLES_ADDR, + (HOMER_PPMR_BASE_ADDR + OCC_WOF_TABLES_PPMR_OFFSET)); + +#endif /* __P9_HCD_MEMMAP_HOMER_H__ */ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H new file mode 100644 index 000000000..bc0591bec --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H @@ -0,0 +1,133 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_memmap_occ_sram.H +/// @brief defines region constants of occ sram. +/// + +// *HWP HWP Owner: David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner: Prem S Jha <premjha2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: PM:Hostboot: Phyp + +#ifndef __P9_HCD_MEMMAP_OCC_SRAM_H__ +#define __P9_HCD_MEMMAP_OCC_SRAM_H__ + +#include <p9_hcd_header_defs.H> +#include <p9_hcd_memmap_base.H> + +// ------------------------------------------------------------------- +// Note: There can be NO semicolons(";") at end of macros in this file +// There can ONLY have HCD_CONST/HCD_CONST64 macros in this file +// ------------------------------------------------------------------- + +/// OCC SRAM + +HCD_CONST(OCC_SRAM_BASE_ADDR, 0xFFF00000) +HCD_CONST(OCC_SRAM_IPC_REGION_SIZE, (4 * ONE_KB)) +HCD_CONST(OCC_SRAM_GPE0_REGION_SIZE, (60 * ONE_KB)) +HCD_CONST(OCC_SRAM_GPE1_REGION_SIZE, (64 * ONE_KB)) +HCD_CONST(OCC_SRAM_PGPE_REGION_SIZE, (64 * ONE_KB)) +HCD_CONST(OCC_SRAM_SGPE_REGION_SIZE, (64 * ONE_KB)) +HCD_CONST(OCC_SRAM_OCC_REGION_SIZE, (512 * ONE_KB)) + +HCD_CONST(OCC_SRAM_BEFORE_PGPE_REGION_SIZE_TOTAL, + (OCC_SRAM_IPC_REGION_SIZE + OCC_SRAM_GPE0_REGION_SIZE + OCC_SRAM_GPE1_REGION_SIZE)) + +//-------------------------------------------------------------------------------------- + +/// PGPE Base + +HCD_CONST(OCC_SRAM_PGPE_BASE_ADDR, + (OCC_SRAM_BASE_ADDR + OCC_SRAM_BEFORE_PGPE_REGION_SIZE_TOTAL)) +HCD_CONST(OCC_SRAM_PGPE_END_ADDR, + (OCC_SRAM_PGPE_BASE_ADDR + OCC_SRAM_PGPE_REGION_SIZE)) +HCD_CONST(OCC_SRAM_PGPE_HCODE_RESET_ADDR, + (OCC_SRAM_PGPE_BASE_ADDR + PGPE_HCODE_RESET_ADDR_VAL)) +HCD_CONST(OCC_SRAM_PGPE_HEADER_ADDR, + (OCC_SRAM_PGPE_BASE_ADDR + PGPE_INT_VECTOR_SIZE)) + + +/// PGPE Boot + +HCD_CONST(OCC_SRAM_PGPE_COPY_BOOT_LOADER_SIZE, ONE_KB) +HCD_CONST(OCC_SRAM_PGPE_COPY_PPMR_HEADER_SIZE, ONE_KB) +HCD_CONST(OCC_SRAM_PGPE_BOOT_LOADER_ADDR, + (OCC_SRAM_PGPE_END_ADDR - OCC_SRAM_PGPE_COPY_BOOT_LOADER_SIZE)) +HCD_CONST(OCC_SRAM_PGPE_BOOT_LOADER_RESET_ADDR, + (OCC_SRAM_PGPE_BOOT_LOADER_ADDR + PGPE_BOOT_LOADER_RESET_ADDR_VAL)) +HCD_CONST(OCC_SRAM_PGPE_PPMR_HEADER_ADDR, + (OCC_SRAM_PGPE_BOOT_LOADER_ADDR - OCC_SRAM_PGPE_COPY_PPMR_HEADER_SIZE)) + +/// PGPE Copy + +HCD_CONST(OCC_SRAM_PGPE_HCODE_OFFSET_ADDR, + (OCC_SRAM_PGPE_PPMR_HEADER_ADDR + PPMR_PGPE_HCODE_OFFSET_BYTE)) +HCD_CONST(OCC_SRAM_PGPE_HCODE_LENGTH_ADDR, + (OCC_SRAM_PGPE_PPMR_HEADER_ADDR + PPMR_PGPE_HCODE_LENGTH_BYTE)) + +//-------------------------------------------------------------------------------------- + +/// SGPE Base + +HCD_CONST(OCC_SRAM_SGPE_BASE_ADDR, + (OCC_SRAM_BASE_ADDR + OCC_SRAM_BEFORE_PGPE_REGION_SIZE_TOTAL + OCC_SRAM_PGPE_REGION_SIZE)) +HCD_CONST(OCC_SRAM_SGPE_END_ADDR, + (OCC_SRAM_SGPE_BASE_ADDR + OCC_SRAM_SGPE_REGION_SIZE)) +HCD_CONST(OCC_SRAM_SGPE_HCODE_RESET_ADDR, + (OCC_SRAM_SGPE_BASE_ADDR + SGPE_HCODE_RESET_ADDR_VAL)) +HCD_CONST(OCC_SRAM_SGPE_HEADER_ADDR, + (OCC_SRAM_SGPE_BASE_ADDR + SGPE_INT_VECTOR_SIZE)) + +/// SGPE Boot + +HCD_CONST(OCC_SRAM_SGPE_COPY_BOOT_LOADER_SIZE, ONE_KB) +HCD_CONST(OCC_SRAM_SGPE_COPY_QPMR_HEADER_SIZE, ONE_KB) +HCD_CONST(OCC_SRAM_SGPE_BOOT_LOADER_ADDR, + (OCC_SRAM_SGPE_END_ADDR - OCC_SRAM_SGPE_COPY_BOOT_LOADER_SIZE)) +HCD_CONST(OCC_SRAM_SGPE_BOOT_LOADER_RESET_ADDR, + (OCC_SRAM_SGPE_BOOT_LOADER_ADDR + SGPE_BOOT_LOADER_RESET_ADDR_VAL)) +HCD_CONST(OCC_SRAM_SGPE_QPMR_HEADER_ADDR, + (OCC_SRAM_SGPE_BOOT_LOADER_ADDR - OCC_SRAM_SGPE_COPY_QPMR_HEADER_SIZE)) + +/// SGPE Copy + +HCD_CONST(OCC_SRAM_SGPE_HCODE_OFFSET_ADDR, + (OCC_SRAM_SGPE_QPMR_HEADER_ADDR + QPMR_SGPE_HCODE_OFFSET_BYTE)) +HCD_CONST(OCC_SRAM_SGPE_HCODE_LENGTH_ADDR, + (OCC_SRAM_SGPE_QPMR_HEADER_ADDR + QPMR_SGPE_HCODE_LENGTH_BYTE)) +HCD_CONST(OCC_SRAM_QUAD_COMMON_RINGS_OFFSET_ADDR, + (OCC_SRAM_SGPE_QPMR_HEADER_ADDR + QPMR_QUAD_COMMON_RINGS_OFFSET_BYTE)) +HCD_CONST(OCC_SRAM_QUAD_COMMON_RINGS_LENGTH_ADDR, + (OCC_SRAM_SGPE_QPMR_HEADER_ADDR + QPMR_QUAD_COMMON_RINGS_LENGTH_BYTE)) +HCD_CONST(OCC_SRAM_QUAD_SPECIFIC_RINGS_OFFSET_ADDR, + (OCC_SRAM_SGPE_QPMR_HEADER_ADDR + QPMR_QUAD_SPECIFIC_RINGS_OFFSET_BYTE)) +HCD_CONST(OCC_SRAM_QUAD_SPECIFIC_RINGS_LENGTH_ADDR, + (OCC_SRAM_SGPE_QPMR_HEADER_ADDR + QPMR_QUAD_SPECIFIC_RINGS_LENGTH_BYTE)) + + +#endif /* __P9_HCD_MEMMAP_OCC_SRAM_H__ */ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index a438b6250..3e2c4f1fd 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -36,6 +36,11 @@ #define __HW_IMG_DEFINE #include <p9_hcd_header_defs.H> +#include <p9_hcd_memmap_base.H> +#include <p9_hcd_memmap_homer.H> +#include <p9_hcd_memmap_occ_sram.H> +#include <p9_hcd_memmap_cme_sram.H> + #include <p9_pstates_cmeqm.h> #include <p9_pstates_common.h> #include <p9_pstates_occ.h> @@ -53,21 +58,6 @@ namespace p9_hcodeImageBuild #endif //__PPE_PLAT #endif //__cplusplus #endif //__ASSEMBLER__ -// Constants used in both C++ and Assembler/Linker code -CONST_UINT32_T(CPMR_HEADER_SIZE, 256); -CONST_UINT32_T(QPMR_HEADER_SIZE, 512); -CONST_UINT32_T(PPMR_HEADER_SIZE, 512); -CONST_UINT32_T(PGPE_IVPR_ADDR, 0xfff20000); - -//#pragma message (STR(CPMR_HEADER_SIZE)) - -// Define the Magic Numbers for the various images -HCD_MAGIC_NUMBER(CPMR_MAGIC_NUMBER, ULL(0x43504d525f312e30)); // CPMR_1.0 -HCD_MAGIC_NUMBER(CME_MAGIC_NUMBER , ULL(0x434d455f5f312e30)); // CME__1.0 -HCD_MAGIC_NUMBER(QPMR_MAGIC_NUMBER, ULL(0x51504d525f312e30)); // QPMR_1.0 -HCD_MAGIC_NUMBER(SGPE_MAGIC_NUMBER, ULL(0x534750455f312e30 )); // SGPE_1.0 -HCD_MAGIC_NUMBER(PPMR_MAGIC_NUMBER, ULL(0x50504d525f312e30)); // PPMR_1.0 -HCD_MAGIC_NUMBER(PGPE_MAGIC_NUMBER , ULL(0x504750455F312E30)); // PGPE_1.0 /** * @brief models QPMR header in HOMER @@ -323,7 +313,7 @@ typedef struct HCD_HDR_UINT64(g_pgpe_magic_number, PGPE_MAGIC_NUMBER); // PGPE_1.0 HCD_HDR_UINT32(g_pgpe_sys_reset_addr, 0 ); // Fully qualified OCC address where pk_init resides HCD_HDR_UINT32(g_pgpe_shared_sram_addr, 0 ); // SRAM address where shared SRAM begins -HCD_HDR_UINT32(g_pgpe_ivpr_addr, PGPE_IVPR_ADDR ); // Beginning of PGPE region in OCC SRAM +HCD_HDR_UINT32(g_pgpe_ivpr_addr, 0 ); // Beginning of PGPE region in OCC SRAM HCD_HDR_UINT32(g_pgpe_shared_sram_len, 0 ); // Length of shared SRAM area HCD_HDR_UINT32(g_pgpe_build_date, 0 ); // Build date for PGPE Image HCD_HDR_UINT32(g_pgpe_build_ver, 0 ); // Build Version @@ -355,172 +345,6 @@ HCD_HDR_UINT32(g_wof_table_length, 0 ); #ifndef __ASSEMBLER__ /** - * @brief summarizes constants associated with hcode image build. - */ -enum -{ - HALF_KB = 512, - ONE_KB = 1024, - ONE_MB = 1024 * 1024, - HARDWARE_IMG_SIZE = ONE_MB, - OCC_HOST_AREA_SIZE = ONE_MB, - HOMER_OCC_REGION_NUM = 0, - HOMER_QPMR_REGION_NUM = 1, - HOMER_CMPR_REGION_NUM = 2, - HOMER_PPMR_REGION_NUM = 3, - MAX_CORES_PER_CHIP = 24, - THREADS_PER_CORE = 4, - MAX_CME_PER_CHIP = 12, - MAX_CACHE_CHIPLETS = 6, - CACH0_CHIPLET_ID = 0x10, - MAX_CORES_PER_EX = 2, - CORE0_CHIPLET_ID = 0x20, - PAD_OPCODE = 0x00000200, //ATTN Opcode - BLR_INST = 0x4e800020, //blr instruction - THREAD_RESTORE_AREA_SIZE = 2048, - PPE_RESERVE_AREA = 0x200, - FUSED_MODE = 0xBB, - NONFUSED_MODE = 0xAA, - PK_DBG_PTR_AREA_SIZE = 64, - SCOM_ENTRY_SIZE = 16, // 4B pad, 4B address, 8B data - SCOM_RESTORE_PER_CHIPLET = 64, // size in words (16B * 16)/4 - - //---- QPMR ---- - QPMR_OFFSET = HOMER_QPMR_REGION_NUM * ONE_MB, - - //** Boot Loaders - SGPE_LVL_1_BOOT_LOAD_SIZE = ONE_KB, - SGPE_LVL_2_BOOT_LOAD_SIZE = ONE_KB, - - //** Hcode - SGPE_INT_VECT = 384, - SGPE_IMG_HEADER = sizeof(sgpeHeader_t), - SGPE_DBG_PTR_AREA_SIZE = 64, - SGPE_HCODE_SIZE = (45 * ONE_KB) + HALF_KB, // @todo RTC 158543 Reallocate space - - SGPE_IMAGE_SIZE = 80 * ONE_KB, - - SGPE_ALLOCATED_SIZE = SGPE_HCODE_SIZE, // @todo RTC 158543 Reallocate space (collapse??) - - //** Scan - SGPE_COMMON_RING_SIZE = 13 * ONE_KB, // 400B * 9 rings * 3 types (base, RL, CC) - SGPE_OVERRIDE_RING_SIZE = 3 * ONE_KB, // 300B * 9 rings - - CACHE_INST_SPECIFIC_SIZE = (3 * ONE_KB) + HALF_KB, // per cache, 1KB/ring x 5 rings/cache - SGPE_INSTRUMENTATION_SIZE = 2 * ONE_KB, - MAX_CACHE_CHIPLET = 6, - MAX_QUAD_SPEC_RING_SIZE = 19 * ONE_KB, - - //** SCOM - NUM_CACHE_SCOM_REGS = 47 + 1, // 16 L2 repr, 16 L3 repr, 15 non-repr, 1 NULL - CACHE_SCOM_RESTORE_SIZE = 6 * ONE_KB, //4488B rounded to 6KB - - CACHE_SCOM_START = 128 * ONE_KB, // HOMER offset from QPMR - - //** OCC SRAM Allocation - SGPE_MAX_AREA_SIZE = 80 * ONE_KB, // Allocation within the OCC SRAM - SGPE_RESERVE_SIZE = SGPE_MAX_AREA_SIZE - - ( SGPE_HCODE_SIZE + - SGPE_COMMON_RING_SIZE + - CACHE_SCOM_RESTORE_SIZE + - SGPE_OVERRIDE_RING_SIZE + - CACHE_SCOM_RESTORE_SIZE), - - //---- CPMR ---- - CPMR_OFFSET = HOMER_CMPR_REGION_NUM * ONE_MB, - - //** Self Restore - THREAD_LAUNCHER_SIZE = 256, - CORE_INT_AREA = 8 * ONE_KB, - SELF_REST_SIZE = CORE_INT_AREA + THREAD_LAUNCHER_SIZE, - CORE_RESTORE_SIZE = ((2 * ONE_KB) * THREADS_PER_CORE) * MAX_CORES_PER_CHIP, - - //** SCOM - CORE_SCOM_START = (256 * ONE_KB), - CORE_SCOM_RESTORE_SIZE = SCOM_ENTRY_SIZE * 16, // (15 registers + 1 NULL) per core - CME_SCOM_AREA = CORE_SCOM_RESTORE_SIZE * 2, // 2 cores - SCOM_AREA_PER_CME = HALF_KB, // 256(ea ) * 2( CORES PER CME) (???) - - //** Hcode - CORE_SCOM_PER_CME = 512, - CORE_SCOM_RES_SIZE = MAX_CME_PER_CHIP * SCOM_AREA_PER_CME, - CME_INT_VECTOR_SIZE = 384, - CME_IMG_HEADER_SIZE = 64, - CPMR_CME_HCODE_OFFSET = (CORE_SCOM_START + CORE_SCOM_RES_SIZE), - CME_REGION_SIZE = (64 * ONE_KB), // CME hcode and data's footprint in HOMER - CME_SRAM_SIZE = (32 * ONE_KB ), - - //** Scan - CORE_COMMON_RING_SIZE = 2 * ONE_KB, // common ring( 2KB) + common overrides (1KB) - MAX_SIZE_CME_INST_RING = 1 * ONE_KB, - CORE_OVERRIDE_RING = 1 * ONE_KB, // common for all cores - QUAD_PSTATE_SIZE = HALF_KB, // common for all cores - CME_INSTRUMENTATION_SIZE = HALF_KB, // per CME - INSTRUMENTATION_COUNTERS = HALF_KB, // (???) - CME_SRAM_HCODE_OFFSET = 0x00, //(???) - CME_REGION_START = (CORE_SCOM_START + CORE_SCOM_RES_SIZE), - CME_BLOCK_READ_LEN = 32, - CME_BLK_SIZE_SHIFT = 0x05, - - //CME Image Flags - CME_STOP_3_TO_2_BIT_POS = 0x80000000, - CME_STOP_4_TO_2_BIT_POS = 0x40000000, - CME_STOP_5_TO_4_BIT_POS = 0x20000000, - CME_STOP_8_TO_5_BIT_POS = 0x10000000, - CME_STOP_11_TO_8_BIT_POS = 0x08000000, - CME_SKIP_CORE_POWEROFF_BIT_POS = 0x00000001, - - //SGPE Image Flags - SGPE_STOP_4_TO_2_BIT_POS = 0x80000000, - SGPE_STOP_5_TO_4_BIT_POS = 0x40000000, - SGPE_STOP_8_TO_5_BIT_POS = 0x20000000, - SGPE_STOP_11_TO_8_BIT_POS = 0x10000000, - SGPE_PROC_FAB_ADDR_BAR_MODE_POS = 0x00008000, - - // PPMR - //** Boot Loaders - PPMR_OFFSET = HOMER_PPMR_REGION_NUM * ONE_MB, - PPMR_HEADER_LEN = 512, - PGPE_LVL_1_BOOT_LOAD_SIZE = ONE_KB, - PGPE_LVL_2_BOOT_LOAD_SIZE = ONE_KB, - PGPE_MAX_AREA_SIZE = 48 * ONE_KB, // @todo RTC 158543 Reallocate space - - PGPE_HOMER_SRAM_ALLOC = 128 * ONE_KB, - PGPE_HOMER_SRAM_RESERVE = PGPE_HOMER_SRAM_ALLOC - - (PPMR_HEADER_LEN + - PGPE_LVL_1_BOOT_LOAD_SIZE + - PGPE_LVL_2_BOOT_LOAD_SIZE + - PGPE_MAX_AREA_SIZE), - - PGPE_INT_VECTOR = 384, - PGPE_HCODE_SIZE = 32 * ONE_KB, - PGPE_PARAM_BLOCK_SIZE = 8 * ONE_KB, - - // @todo: get these from the p9_homer_map.h file - HOMER_OOC_PARAM_BLOCK_ADDR = 0x00320000, // PPMR + 128KB - HOMER_PSTATE_OUTPUT_TABLE_ADDR = 0x00324000, // PPMR + 144KB - HOMER_WOF_TABLE_ADDR = 0x003C0000, // PPMR + 768KB (the last 256KB) - - OCC_PARAM_BLOCK_ALLOC = 16 * ONE_KB, - OCC_PARAM_BLOCK_SIZE = 8 * ONE_KB, - - PSTATE_OUTPUT_TABLE_ALLOC = 16 * ONE_KB, - PSTATE_OUTPUT_TABLE_SIZE = 8 * ONE_KB, - - WOF_TABLES_BLOCK_ALLOC = 256 * ONE_KB, - - OCI_SRAM_ADDR_BASE = 0xFFF20000, // @todo: what is this for? - OCI_PBA_ADDR_BASE = 0x80300000, - IGNORE_CHIPLET_INSTANCE = 0xFF, - - //RING LAYOUT - RING_ALIGN_BOUNDARY = 0x08, - - //MISC - DARN_BAR_EN_POS = 0x8000000000000000ll, -}; - -/** * @brief enumerates all return codes associated with hcode image build. */ enum ImgBldRetCode_t @@ -599,13 +423,13 @@ typedef struct typedef struct { CoreSpecRingList_t coreSpecRings; - uint8_t instanceRingPayLoad[ MAX_SIZE_CME_INST_RING - sizeof(CoreSpecRingList_t)]; + uint8_t instanceRingPayLoad[ CORE_SPECIFIC_RING_SIZE_PER_CORE - sizeof(CoreSpecRingList_t)]; } CoreSpecRingCme_t; typedef union { CoreSpecRingCme_t instRingIndex; - uint8_t instScanRings[ MAX_SIZE_CME_INST_RING ]; + uint8_t instScanRings[ CORE_SPECIFIC_RING_SIZE_PER_CORE ]; } CoreSpecRingLayout_t; /** @@ -669,13 +493,13 @@ typedef struct typedef struct { QuadCmnRingsList_t quadCmnRingList; - uint8_t cmnRingPayLoad[SGPE_COMMON_RING_SIZE - sizeof(QuadCmnRingsList_t)]; + uint8_t cmnRingPayLoad[QUAD_COMMON_RING_SIZE - sizeof(QuadCmnRingsList_t)]; } QuadCmnRingsSgpe_t; typedef union { QuadCmnRingsSgpe_t cmnRingIndex; - uint8_t cmnScanRings[SGPE_COMMON_RING_SIZE]; + uint8_t cmnScanRings[QUAD_COMMON_RING_SIZE]; } CmnRingLayoutSgpe_t; /** @@ -699,14 +523,14 @@ typedef struct typedef struct { - QuadSpecRingsList_t quadSpecRings[MAX_CACHE_CHIPLET]; - uint8_t quadSpecRingPayLoad[ MAX_QUAD_SPEC_RING_SIZE - (MAX_CACHE_CHIPLET * sizeof(QuadSpecRingsList_t))]; + QuadSpecRingsList_t quadSpecRings[MAX_QUADS_PER_CHIP]; + uint8_t quadSpecRingPayLoad[ QUAD_SPECIFIC_RING_SIZE_TOTAL - (MAX_QUADS_PER_CHIP * sizeof(QuadSpecRingsList_t))]; } QuadSpecRing_t; typedef union { QuadSpecRing_t instRingIndex; - uint8_t instScanRings[ MAX_QUAD_SPEC_RING_SIZE ]; + uint8_t instScanRings[ QUAD_SPECIFIC_RING_SIZE_TOTAL ]; } InstRingLayoutSgpe_t; /** @@ -715,18 +539,18 @@ typedef union typedef struct { uint8_t qpmrHeader[sizeof(QpmrHeaderLayout_t)]; - uint8_t l1BootLoader[SGPE_LVL_1_BOOT_LOAD_SIZE]; - uint8_t l2BootLoader[SGPE_LVL_2_BOOT_LOAD_SIZE]; + uint8_t l1BootLoader[SGPE_BOOT_COPIER_SIZE]; + uint8_t l2BootLoader[SGPE_BOOT_LOADER_SIZE]; uint8_t sgpeSramImage[SGPE_IMAGE_SIZE]; } SgpeLayout_t; typedef union CPMRSelfRestoreLayout { - uint8_t region[SELF_REST_SIZE]; + uint8_t region[SELF_RESTORE_CODE_SIZE]; struct { cpmrHeader_t CPMRHeader; - uint8_t exe[SELF_REST_SIZE - sizeof(cpmrHeader_t)]; + uint8_t exe[SELF_RESTORE_CODE_SIZE - sizeof(cpmrHeader_t)]; } elements; } CPMRSelfRestoreLayout_t; @@ -736,9 +560,9 @@ typedef union CPMRSelfRestoreLayout typedef struct { CPMRSelfRestoreLayout_t CPMR_SR; - uint8_t coreSelfRestore[CORE_RESTORE_SIZE]; - uint8_t reserve[CORE_SCOM_START - (SELF_REST_SIZE + CORE_RESTORE_SIZE)]; - uint8_t coreScom[CORE_SCOM_RES_SIZE]; + uint8_t coreSelfRestore[SELF_RESTORE_CORE_REGS_SIZE]; + uint8_t reserve[CORE_SCOM_RESTORE_CPMR_OFFSET - SELF_RESTORE_SIZE_TOTAL]; + uint8_t coreScom[CORE_SCOM_RESTORE_SIZE_TOTAL]; } SelfRestoreLayout_t; typedef struct @@ -752,15 +576,15 @@ typedef struct */ typedef struct { - uint8_t ppmrHeader[PPMR_HEADER_LEN]; - uint8_t l1BootLoader[PGPE_LVL_1_BOOT_LOAD_SIZE]; - uint8_t l2BootLoader[PGPE_LVL_2_BOOT_LOAD_SIZE]; - uint8_t pgpeSramImage[PGPE_MAX_AREA_SIZE]; // Includes the Global Pstate Parameter Block - uint8_t ppmr_reserved0[PGPE_HOMER_SRAM_RESERVE]; + uint8_t ppmrHeader[PPMR_HEADER_SIZE]; + uint8_t l1BootLoader[PGPE_BOOT_COPIER_SIZE]; + uint8_t l2BootLoader[PGPE_BOOT_LOADER_SIZE]; + uint8_t pgpeSramImage[PGPE_IMAGE_SIZE]; // Includes the Global Pstate Parameter Block + uint8_t ppmr_reserved0[PGPE_IMAGE_RESERVE_SIZE]; uint8_t occParmBlock[sizeof(OCCPstateParmBlock)]; // PPMR + 128KB - uint8_t occParmBlockReserve[OCC_PARAM_BLOCK_ALLOC - sizeof(OCCPstateParmBlock)]; + uint8_t occParmBlockReserve[OCC_PSTATE_PARAM_BLOCK_REGION_SIZE - sizeof(OCCPstateParmBlock)]; uint8_t pstateTable[sizeof(GeneratedPstateInfo)]; // PPMR + 144KB - uint8_t pstateTableReserve[PSTATE_OUTPUT_TABLE_ALLOC - sizeof(GeneratedPstateInfo)]; + uint8_t pstateTableReserve[PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE - sizeof(GeneratedPstateInfo)]; } PPMRLayout_t; /** @@ -769,8 +593,8 @@ typedef struct typedef struct { SgpeLayout_t sgpeRegion; - uint8_t qpmrReserve1[CACHE_SCOM_START - sizeof(SgpeLayout_t)]; - uint8_t cacheScomRegion[CACHE_SCOM_RESTORE_SIZE]; + uint8_t qpmrReserve1[QUAD_SCOM_RESTORE_QPMR_OFFSET - sizeof(SgpeLayout_t)]; + uint8_t cacheScomRegion[QUAD_SCOM_RESTORE_SIZE_TOTAL]; } QPMRLayout_t; /** diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index b263302ce..49959dd34 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -60,11 +60,11 @@ using namespace stopImageSection; extern "C" { - /** - * @brief aligns DATA_SIZE to 8B. - * @param TEMP_LEN temp storage - * @param DATA_SIZE size to be aligned. Aligned size is saved in same variable. - */ +/** + * @brief aligns DATA_SIZE to 8B. + * @param TEMP_LEN temp storage + * @param DATA_SIZE size to be aligned. Aligned size is saved in same variable. + */ #define ALIGN_DWORD(TEMP_LEN, DATA_SIZE) \ {TEMP_LEN = (DATA_SIZE % RING_ALIGN_BOUNDARY); \ if( TEMP_LEN ) \ @@ -73,11 +73,11 @@ extern "C" } \ } - /** - * @brief aligns start of scan ring to 8B boundary. - * @param RING_REGION_BASE start location of scan ring region in HOMER. - * @param RING_LOC start of scan ring. - */ +/** + * @brief aligns start of scan ring to 8B boundary. + * @param RING_REGION_BASE start location of scan ring region in HOMER. + * @param RING_LOC start of scan ring. + */ #define ALIGN_RING_LOC(RING_REGION_BASE, RING_LOC) \ { \ uint8_t tempDiff = \ @@ -88,9 +88,9 @@ extern "C" } \ } - /** - * @brief round of ring size to multiple of 32B - */ +/** + * @brief round of ring size to multiple of 32B + */ #define ROUND_OFF_32B( ROUND_SIZE) \ { \ uint32_t tempSize = ROUND_SIZE; \ @@ -99,210 +99,210 @@ extern "C" ROUND_SIZE = (( ( tempSize + 31 )/32 ) * 32 ); \ } \ } - namespace p9_hcodeImageBuild - { +namespace p9_hcodeImageBuild +{ - /** - * @brief some misc local constants - */ - enum +/** + * @brief some misc local constants + */ +enum +{ + ENABLE_ALL_CORE = 0x000FFFF, + RISK_LEVEL = 0x01, + QUAD_COMMON_RING_INDEX_SIZE = sizeof(QuadCmnRingsList_t), + QUAD_SPEC_RING_INDEX_SIZE = ((sizeof(QuadSpecRingsList_t)) / sizeof(uint16_t)), + QUAD_SPEC_RING_INDEX_LEN = (QUAD_SPEC_RING_INDEX_SIZE * 2 * MAX_QUADS_PER_CHIP), + CORE_COMMON_RING_INDEX_SIZE = sizeof(CoreCmnRingsList_t), + CORE_SPEC_RING_INDEX_SIZE = sizeof(CoreSpecRingList_t), + RING_START_TO_RS4_OFFSET = 8, + TOR_VER_ONE = 1, + TOR_VER_TWO = 2, + QUAD_BIT_POS = 24, + ODD_EVEN_EX_POS = 0x00000400, +}; + +/** + * @brief struct used to manipulate scan ring in HOMER. + */ +struct RingBufData +{ + void* iv_pRingBuffer; + uint32_t iv_ringBufSize; + void* iv_pWorkBuf1; + uint32_t iv_sizeWorkBuf1; + void* iv_pWorkBuf2; + uint32_t iv_sizeWorkBuf2; + + RingBufData( void* i_pRingBuf1, const uint32_t i_ringSize, + void* i_pWorkBuf1, const uint32_t i_sizeWorkBuf1, + void* i_pWorkBuf2, const uint32_t i_sizeWorkBuf2 ) : + iv_pRingBuffer( i_pRingBuf1), + iv_ringBufSize(i_ringSize), + iv_pWorkBuf1( i_pWorkBuf1 ), + iv_sizeWorkBuf1( i_sizeWorkBuf1 ), + iv_pWorkBuf2( i_pWorkBuf2 ), + iv_sizeWorkBuf2( i_sizeWorkBuf2 ) + + {} + + RingBufData(): + iv_pRingBuffer( NULL ), + iv_ringBufSize( 0 ), + iv_pWorkBuf1( NULL ), + iv_sizeWorkBuf1( 0 ), + iv_pWorkBuf2( NULL ), + iv_sizeWorkBuf2( 0 ) + { } +}; + +/** + * @brief models a section in HOMER. + */ +struct ImgSec +{ + PlatId iv_plat; + uint8_t iv_secId; + ImgSec( PlatId i_plat, uint8_t i_secId ): + iv_plat( i_plat ), + iv_secId( i_secId ) + { } + ImgSec(): iv_plat (PLAT_SELF), iv_secId (0 ) + { } +}; + +/** + * @brief operator < overloading for ImgSec. + */ +bool operator < ( const ImgSec& i_lhs, const ImgSec& i_rhs ) +{ + if( i_lhs.iv_plat == i_rhs.iv_plat ) { - ENABLE_ALL_CORE = 0x000FFFF, - RISK_LEVEL = 0x01, - QUAD_COMMON_RING_INDEX_SIZE = sizeof(QuadCmnRingsList_t), - QUAD_SPEC_RING_INDEX_SIZE = ((sizeof(QuadSpecRingsList_t)) / sizeof(uint16_t)), - QUAD_SPEC_RING_INDEX_LEN = (QUAD_SPEC_RING_INDEX_SIZE * 2 * MAX_CACHE_CHIPLET), - CORE_COMMON_RING_INDEX_SIZE = sizeof(CoreCmnRingsList_t), - CORE_SPEC_RING_INDEX_SIZE = sizeof(CoreSpecRingList_t), - RING_START_TO_RS4_OFFSET = 8, - TOR_VER_ONE = 1, - TOR_VER_TWO = 2, - QUAD_BIT_POS = 24, - ODD_EVEN_EX_POS = 0x00000400, - }; - - /** - * @brief struct used to manipulate scan ring in HOMER. - */ - struct RingBufData + return i_lhs.iv_secId < i_rhs.iv_secId; + } + else { - void* iv_pRingBuffer; - uint32_t iv_ringBufSize; - void* iv_pWorkBuf1; - uint32_t iv_sizeWorkBuf1; - void* iv_pWorkBuf2; - uint32_t iv_sizeWorkBuf2; - - RingBufData( void* i_pRingBuf1, const uint32_t i_ringSize, - void* i_pWorkBuf1, const uint32_t i_sizeWorkBuf1, - void* i_pWorkBuf2, const uint32_t i_sizeWorkBuf2 ) : - iv_pRingBuffer( i_pRingBuf1), - iv_ringBufSize(i_ringSize), - iv_pWorkBuf1( i_pWorkBuf1 ), - iv_sizeWorkBuf1( i_sizeWorkBuf1 ), - iv_pWorkBuf2( i_pWorkBuf2 ), - iv_sizeWorkBuf2( i_sizeWorkBuf2 ) - - {} - - RingBufData(): - iv_pRingBuffer( NULL ), - iv_ringBufSize( 0 ), - iv_pWorkBuf1( NULL ), - iv_sizeWorkBuf1( 0 ), - iv_pWorkBuf2( NULL ), - iv_sizeWorkBuf2( 0 ) - { } - }; + return i_lhs.iv_plat < i_rhs.iv_plat; + } +} - /** - * @brief models a section in HOMER. - */ - struct ImgSec - { - PlatId iv_plat; - uint8_t iv_secId; - ImgSec( PlatId i_plat, uint8_t i_secId ): - iv_plat( i_plat ), - iv_secId( i_secId ) - { } - ImgSec(): iv_plat (PLAT_SELF), iv_secId (0 ) - { } - }; +/** + * @brief operator == overloading for ImgSec. + */ +bool operator == ( const ImgSec& i_lhs, const ImgSec& i_rhs ) +{ + bool equal = false; - /** - * @brief operator < overloading for ImgSec. - */ - bool operator < ( const ImgSec& i_lhs, const ImgSec& i_rhs ) + if( i_lhs.iv_plat == i_rhs.iv_plat ) { - if( i_lhs.iv_plat == i_rhs.iv_plat ) - { - return i_lhs.iv_secId < i_rhs.iv_secId; - } - else + if( i_lhs.iv_secId == i_rhs.iv_secId ) { - return i_lhs.iv_plat < i_rhs.iv_plat; + equal = true; } } - /** - * @brief operator == overloading for ImgSec. - */ - bool operator == ( const ImgSec& i_lhs, const ImgSec& i_rhs ) - { - bool equal = false; + return equal; +} - if( i_lhs.iv_plat == i_rhs.iv_plat ) - { - if( i_lhs.iv_secId == i_rhs.iv_secId ) - { - equal = true; - } - } - - return equal; - } - - /** - * @brief compares size of a given image's section with maximum allowed size. - */ - class ImgSizeBank - { - public: - ImgSizeBank(); - ~ImgSizeBank() {}; - uint32_t isSizeGood( PlatId i_plat, uint8_t i_sec, uint32_t i_size ); +/** + * @brief compares size of a given image's section with maximum allowed size. + */ +class ImgSizeBank +{ + public: + ImgSizeBank(); + ~ImgSizeBank() {}; + uint32_t isSizeGood( PlatId i_plat, uint8_t i_sec, uint32_t i_size ); - private: - std::map< ImgSec, uint32_t> iv_secSize; + private: + std::map< ImgSec, uint32_t> iv_secSize; - }; +}; - /** - * @brief constructor - */ - ImgSizeBank::ImgSizeBank() - { - iv_secSize[ImgSec(PLAT_SELF, P9_XIP_SECTION_RESTORE_SELF)] = SELF_REST_SIZE; - iv_secSize[ImgSec(PLAT_SELF, P9_XIP_SECTION_RESTORE_CPMR)] = CPMR_HEADER_SIZE; - iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_QPMR)] = HALF_KB; - iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_LVL1_BL)] = SGPE_LVL_1_BOOT_LOAD_SIZE; - iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_LVL2_BL)] = SGPE_LVL_2_BOOT_LOAD_SIZE; - iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_HCODE)] = SGPE_IMAGE_SIZE; - - iv_secSize[ImgSec(PLAT_CME, P9_XIP_SECTION_CME_HCODE)] = CME_SRAM_SIZE; - - iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_PPMR)] = HALF_KB; - iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL1_BL)] = PGPE_LVL_1_BOOT_LOAD_SIZE ; - iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL2_BL)] = PGPE_LVL_2_BOOT_LOAD_SIZE ; - iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_HCODE)] = PGPE_MAX_AREA_SIZE; - } +/** + * @brief constructor + */ +ImgSizeBank::ImgSizeBank() +{ + iv_secSize[ImgSec(PLAT_SELF, P9_XIP_SECTION_RESTORE_SELF)] = SELF_RESTORE_CODE_SIZE; + iv_secSize[ImgSec(PLAT_SELF, P9_XIP_SECTION_RESTORE_CPMR)] = CPMR_HEADER_SIZE; + iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_QPMR)] = HALF_KB; + iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_LVL1_BL)] = SGPE_BOOT_COPIER_SIZE; + iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_LVL2_BL)] = SGPE_BOOT_LOADER_SIZE; + iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_HCODE)] = SGPE_IMAGE_SIZE; + + iv_secSize[ImgSec(PLAT_CME, P9_XIP_SECTION_CME_HCODE)] = CME_SRAM_SIZE; + + iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_PPMR)] = HALF_KB; + iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL1_BL)] = PGPE_BOOT_COPIER_SIZE; + iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL2_BL)] = PGPE_BOOT_LOADER_SIZE; + iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_HCODE)] = PGPE_IMAGE_SIZE; +} + +/** + * @brief verifies actual section size against max size allowed. + * @param i_plat platform associated with image section. + * @param i_sec image section. + * @param i_size actual image section size. + * @return zero if size within limit else max size allowed. + */ +uint32_t ImgSizeBank::isSizeGood( PlatId i_plat, uint8_t i_sec, uint32_t i_size ) +{ + uint32_t size = -1; + ImgSec key( i_plat, i_sec ); + std::map< ImgSec, uint32_t>::iterator it; - /** - * @brief verifies actual section size against max size allowed. - * @param i_plat platform associated with image section. - * @param i_sec image section. - * @param i_size actual image section size. - * @return zero if size within limit else max size allowed. - */ - uint32_t ImgSizeBank::isSizeGood( PlatId i_plat, uint8_t i_sec, uint32_t i_size ) + for( it = iv_secSize.begin(); it != iv_secSize.end(); it++ ) { - uint32_t size = -1; - ImgSec key( i_plat, i_sec ); - std::map< ImgSec, uint32_t>::iterator it; - - for( it = iv_secSize.begin(); it != iv_secSize.end(); it++ ) + if( it->first == key ) { - if( it->first == key ) - { - size = 0; - - if( it->second < i_size ) - { - size = it->second; - } + size = 0; - break; + if( it->second < i_size ) + { + size = it->second; } - } - FAPI_DBG(" Sec Size 0x%08X", size); - return size; + break; + } } + FAPI_DBG(" Sec Size 0x%08X", size); + return size; +} + +/** + * @brief models an Ex pair. + */ +struct ExpairId +{ + uint16_t iv_evenExId; + uint16_t iv_oddExId; /** - * @brief models an Ex pair. + * @brief constructor */ - struct ExpairId - { - uint16_t iv_evenExId; - uint16_t iv_oddExId; - /** - * @brief constructor - */ - ExpairId( uint32_t i_evenExId, uint32_t i_oddExId ): - iv_evenExId( i_evenExId ), - iv_oddExId( i_oddExId ) - { } - - /** - * @brief constructor - */ - ExpairId() { }; - }; + ExpairId( uint32_t i_evenExId, uint32_t i_oddExId ): + iv_evenExId( i_evenExId ), + iv_oddExId( i_oddExId ) + { } /** - * @brief a map to resolve Ex chiplet Id associated with all six quads in P9. + * @brief constructor */ - class ExIdMap - { - public: - ExIdMap(); - ~ExIdMap() {}; - uint32_t getInstanceId( uint32_t i_eqId, uint32_t i_ringOrder ); - private: - std::map<uint32_t, ExpairId> iv_idMap; - }; + ExpairId() { }; +}; + +/** + * @brief a map to resolve Ex chiplet Id associated with all six quads in P9. + */ +class ExIdMap +{ + public: + ExIdMap(); + ~ExIdMap() {}; + uint32_t getInstanceId( uint32_t i_eqId, uint32_t i_ringOrder ); + private: + std::map<uint32_t, ExpairId> iv_idMap; +}; #define ALIGN_DBWORD( OUTSIZE, INSIZE ) \ { \ @@ -313,2054 +313,2165 @@ extern "C" } \ } - /** - * @brief constructor - */ - ExIdMap::ExIdMap() - { - ExpairId exPairIdMap[6] = { { 0x10, 0x11}, - { 0x12, 0x13 }, - { 0x14, 0x15 }, - { 0x16, 0x17 }, - { 0x18, 0x19 }, - { 0x1A, 0x1B } - }; +/** + * @brief constructor + */ +ExIdMap::ExIdMap() +{ + ExpairId exPairIdMap[6] = { { 0x10, 0x11}, + { 0x12, 0x13 }, + { 0x14, 0x15 }, + { 0x16, 0x17 }, + { 0x18, 0x19 }, + { 0x1A, 0x1B } + }; - for( uint32_t eqCnt = 0; eqCnt < MAX_CACHE_CHIPLET; eqCnt++ ) - { - iv_idMap[CACH0_CHIPLET_ID + eqCnt] = exPairIdMap[eqCnt]; - } + for( uint32_t eqCnt = 0; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ ) + { + iv_idMap[CACHE0_CHIPLET_ID + eqCnt] = exPairIdMap[eqCnt]; } +} //------------------------------------------------------------------------- - /** - * @brief returns ex chiplet ID associated with a scan ring and EQ id. - * @param i_eqId chiplet id for a given quad. - * @param i_ringOrder serial number associated with a scan ring in HOMER. - * @return chiplet Id associated with a scan ring. - */ - uint32_t ExIdMap::getInstanceId( uint32_t i_eqId, uint32_t i_ringOrder ) - { - uint32_t exChipletId = 0xFFFFFFFF; - std::map<uint32_t, ExpairId>::iterator itChipId = iv_idMap.find( i_eqId ); +/** + * @brief returns ex chiplet ID associated with a scan ring and EQ id. + * @param i_eqId chiplet id for a given quad. + * @param i_ringOrder serial number associated with a scan ring in HOMER. + * @return chiplet Id associated with a scan ring. + */ +uint32_t ExIdMap::getInstanceId( uint32_t i_eqId, uint32_t i_ringOrder ) +{ + uint32_t exChipletId = 0xFFFFFFFF; + std::map<uint32_t, ExpairId>::iterator itChipId = iv_idMap.find( i_eqId ); - do + do + { + if ( itChipId == iv_idMap.end() ) { - if ( itChipId == iv_idMap.end() ) - { - break; - } - else + break; + } + else + { + switch( i_ringOrder ) { - switch( i_ringOrder ) - { - case 0: - exChipletId = i_eqId; - break; - - case 1: - case 3: - case 5: - case 7: - exChipletId = itChipId->second.iv_evenExId; - break; - - case 2: - case 4: - case 6: - case 8: - exChipletId = itChipId->second.iv_oddExId; - break; - - default: - break; - } - } + case 0: + exChipletId = i_eqId; + break; + + case 1: + case 3: + case 5: + case 7: + exChipletId = itChipId->second.iv_evenExId; + break; + + case 2: + case 4: + case 6: + case 8: + exChipletId = itChipId->second.iv_oddExId; + break; + default: + break; + } } - while(0); - FAPI_DBG("Resolved Ex Id 0x%02x", exChipletId ); - return exChipletId; } + while(0); + + FAPI_DBG("Resolved Ex Id 0x%02x", exChipletId ); + return exChipletId; +} //------------------------------------------------------------------------- - uint32_t validateSramImageSize( Homerlayout_t* i_pChipHomer, uint32_t& o_sramImgSize ) - { - FAPI_DBG(">validateSramImageSize" ); - uint32_t rc = IMG_BUILD_SUCCESS; +uint32_t validateSramImageSize( Homerlayout_t* i_pChipHomer, uint32_t& o_sramImgSize ) +{ + FAPI_DBG(">validateSramImageSize" ); + uint32_t rc = IMG_BUILD_SUCCESS; - do - { - ImgSizeBank sizebank; - sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT]; - cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) i_pChipHomer->ppmrRegion.ppmrHeader; + do + { + ImgSizeBank sizebank; + sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; + cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) i_pChipHomer->ppmrRegion.ppmrHeader; - //FIXME size will change once SCOM and 24x7 are handled - o_sramImgSize = SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_offset); + //FIXME size will change once SCOM and 24x7 are handled + o_sramImgSize = SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_offset); - rc = sizebank.isSizeGood( PLAT_SGPE, P9_XIP_SECTION_SGPE_HCODE, o_sramImgSize ); - FAPI_DBG("SGPE SRAM Image : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" ); + rc = sizebank.isSizeGood( PLAT_SGPE, P9_XIP_SECTION_SGPE_HCODE, o_sramImgSize ); + FAPI_DBG("SGPE SRAM Image : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" ); - if( rc ) - { - rc = SGPE_SRAM_IMG_SIZE_ERR; - break; - } + if( rc ) + { + rc = SGPE_SRAM_IMG_SIZE_ERR; + break; + } - o_sramImgSize = (SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset) << CME_BLK_SIZE_SHIFT) + - SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_length); + o_sramImgSize = (SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset) << CME_BLK_SIZE_SHIFT) + + SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_length); - FAPI_DBG("CME Offset 0x%08X size 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset), o_sramImgSize ); - rc = sizebank.isSizeGood( PLAT_CME, P9_XIP_SECTION_CME_HCODE, o_sramImgSize ); - FAPI_DBG("CME SRAM Image : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" ); + FAPI_DBG("CME Offset 0x%08X size 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset), o_sramImgSize ); + rc = sizebank.isSizeGood( PLAT_CME, P9_XIP_SECTION_CME_HCODE, o_sramImgSize ); + FAPI_DBG("CME SRAM Image : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" ); - if( rc ) - { - rc = CME_SRAM_IMG_SIZE_ERR; - break; - } + if( rc ) + { + rc = CME_SRAM_IMG_SIZE_ERR; + break; + } - o_sramImgSize = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pgpe_sram_img_size); - rc = sizebank.isSizeGood( PLAT_PGPE, P9_XIP_SECTION_PGPE_HCODE, o_sramImgSize ); - FAPI_DBG("PGPE SRAM Image : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" ); + o_sramImgSize = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pgpe_sram_img_size); + rc = sizebank.isSizeGood( PLAT_PGPE, P9_XIP_SECTION_PGPE_HCODE, o_sramImgSize ); + FAPI_DBG("PGPE SRAM Image : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" ); - if( rc ) - { - rc = PGPE_SRAM_IMG_SIZE_ERR; - break; - } + if( rc ) + { + rc = PGPE_SRAM_IMG_SIZE_ERR; + break; } - while(0); + } + while(0); - FAPI_DBG("<validateSramImageSize" ); + FAPI_DBG("<validateSramImageSize" ); - return rc; - } + return rc; +} //------------------------------------------------------------------------- - /** - * @brief validates arguments passed for hcode image build - * @param refer to p9_hcode_image_build arguments - * @return fapi2 return code - */ - fapi2::ReturnCode validateInputArguments( void* const i_pImageIn, void* i_pImageOut, - SysPhase_t i_phase, ImageType_t i_imgType, - void* i_pBuf1, uint32_t i_bufSize1, void* i_pBuf2, - uint32_t i_bufSize2, void* i_pBuf3, uint32_t i_bufSize3 ) - { - uint32_t l_rc = IMG_BUILD_SUCCESS; - uint32_t hwImagSize = 0; - - FAPI_DBG("Entering validateInputArguments ..."); - - FAPI_ASSERT( (( i_pImageIn != NULL ) && ( i_pImageOut != NULL ) && - ( i_pImageIn != i_pImageOut )), - fapi2::IMG_PTR_ERROR() - .set_HW_IMG_BUF_PTR( i_pImageIn ) - .set_HOMER_IMG_BUF_PTR( i_pImageOut ), - "Bad pointer to HW Image or HOMER Image" ); - l_rc = p9_xip_image_size( i_pImageIn, &hwImagSize ); - - FAPI_DBG("size is 0x%08X; xip_image_size RC is 0x%02x HARDWARE_IMG_SIZE 0x%08X Sz 0x%08X", - hwImagSize, l_rc, HARDWARE_IMG_SIZE, hwImagSize ); - - FAPI_ASSERT( (( IMG_BUILD_SUCCESS == l_rc ) && ( hwImagSize > 0 ) && - ( HARDWARE_IMG_SIZE >= hwImagSize )), - fapi2::HW_IMAGE_INVALID_SIZE() - .set_HW_IMG_SIZE( hwImagSize ) - .set_MAX_HW_IMG_SIZE( HARDWARE_IMG_SIZE ), - "Hardware image size found out of range" ); - FAPI_ASSERT( (( i_phase > PHASE_NA ) && ( i_phase < PHASE_END )), - fapi2::HCODE_INVALID_PHASE() - .set_SYS_PHASE( i_phase ), - "Invalid value passed as build phase" ); - - FAPI_ASSERT( ( i_pBuf1 != NULL ), - fapi2::HCODE_INVALID_TEMP_BUF() - .set_TEMP_BUF_PTR( i_pBuf1 ), - "Invalid temp buffer1 passed for hcode image build" ); - - FAPI_ASSERT( (( i_bufSize1 != 0 ) && ( i_bufSize2 != 0 ) && ( i_bufSize3 != 0 )), - fapi2::HCODE_TEMP_BUF_SIZE() - .set_TEMP_BUF1_SIZE( i_bufSize1 ) - .set_TEMP_BUF2_SIZE( i_bufSize2 ) - .set_TEMP_BUF3_SIZE( i_bufSize3 ), - "Invalid work buffer size " ); - - FAPI_ASSERT( ( i_pBuf2 != NULL ), - fapi2::HCODE_INVALID_TEMP_BUF() - .set_TEMP_BUF_PTR( i_pBuf2 ), - "Invalid temp buffer2 passed for hcode image build" ); - - FAPI_ASSERT( ( i_pBuf3 != NULL ), - fapi2::HCODE_INVALID_TEMP_BUF() - .set_TEMP_BUF_PTR( i_pBuf3 ), - "Invalid temp buffer3 passed for hcode image build" ); - - FAPI_ASSERT( ( i_imgType.isBuildValid() ), - fapi2::HCODE_INVALID_IMG_TYPE(), - "Invalid temp buffer passed for hcode image build" ); - FAPI_DBG("Exiting validateInputArguments ..."); - - fapi_try_exit: - return fapi2::current_err; - } +/** + * @brief validates arguments passed for hcode image build + * @param refer to p9_hcode_image_build arguments + * @return fapi2 return code +*/ +fapi2::ReturnCode validateInputArguments( void* const i_pImageIn, void* i_pImageOut, + SysPhase_t i_phase, ImageType_t i_imgType, + void* i_pBuf1, uint32_t i_bufSize1, void* i_pBuf2, + uint32_t i_bufSize2, void* i_pBuf3, uint32_t i_bufSize3 ) +{ + uint32_t l_rc = IMG_BUILD_SUCCESS; + uint32_t hwImagSize = 0; + + FAPI_DBG("Entering validateInputArguments ..."); + + FAPI_ASSERT( (( i_pImageIn != NULL ) && ( i_pImageOut != NULL ) && + ( i_pImageIn != i_pImageOut )), + fapi2::IMG_PTR_ERROR() + .set_HW_IMG_BUF_PTR( i_pImageIn ) + .set_HOMER_IMG_BUF_PTR( i_pImageOut ), + "Bad pointer to HW Image or HOMER Image" ); + l_rc = p9_xip_image_size( i_pImageIn, &hwImagSize ); + + FAPI_DBG("size is 0x%08X; xip_image_size RC is 0x%02x HARDWARE_IMG_SIZE 0x%08X Sz 0x%08X", + hwImagSize, l_rc, HARDWARE_IMG_SIZE, hwImagSize ); + + FAPI_ASSERT( (( IMG_BUILD_SUCCESS == l_rc ) && ( hwImagSize > 0 ) && + ( HARDWARE_IMG_SIZE >= hwImagSize )), + fapi2::HW_IMAGE_INVALID_SIZE() + .set_HW_IMG_SIZE( hwImagSize ) + .set_MAX_HW_IMG_SIZE( HARDWARE_IMG_SIZE ), + "Hardware image size found out of range" ); + FAPI_ASSERT( (( i_phase > PHASE_NA ) && ( i_phase < PHASE_END )), + fapi2::HCODE_INVALID_PHASE() + .set_SYS_PHASE( i_phase ), + "Invalid value passed as build phase" ); + + FAPI_ASSERT( ( i_pBuf1 != NULL ), + fapi2::HCODE_INVALID_TEMP_BUF() + .set_TEMP_BUF_PTR( i_pBuf1 ), + "Invalid temp buffer1 passed for hcode image build" ); + + FAPI_ASSERT( (( i_bufSize1 != 0 ) && ( i_bufSize2 != 0 ) && ( i_bufSize3 != 0 )), + fapi2::HCODE_TEMP_BUF_SIZE() + .set_TEMP_BUF1_SIZE( i_bufSize1 ) + .set_TEMP_BUF2_SIZE( i_bufSize2 ) + .set_TEMP_BUF3_SIZE( i_bufSize3 ), + "Invalid work buffer size " ); + + FAPI_ASSERT( ( i_pBuf2 != NULL ), + fapi2::HCODE_INVALID_TEMP_BUF() + .set_TEMP_BUF_PTR( i_pBuf2 ), + "Invalid temp buffer2 passed for hcode image build" ); + + FAPI_ASSERT( ( i_pBuf3 != NULL ), + fapi2::HCODE_INVALID_TEMP_BUF() + .set_TEMP_BUF_PTR( i_pBuf3 ), + "Invalid temp buffer3 passed for hcode image build" ); + + FAPI_ASSERT( ( i_imgType.isBuildValid() ), + fapi2::HCODE_INVALID_IMG_TYPE(), + "Invalid temp buffer passed for hcode image build" ); + FAPI_DBG("Exiting validateInputArguments ..."); + +fapi_try_exit: + return fapi2::current_err; +} //------------------------------------------------------------------------------ - /** - * @brief Copies section of hardware image to HOMER - * @param i_destPtr a location in HOMER - * @param i_srcPtr a location in HW Image. - * @param i_secId XIP Section id to be copied. - * @param i_platId platform associated with the given section. - * @param o_ppeSection contains section details. - * @return IMG_BUILD_SUCCESS if successful, error code otherwise. - */ - uint32_t copySectionToHomer( uint8_t* i_destPtr, uint8_t* i_srcPtr, uint8_t i_secId, PlatId i_platId , - P9XipSection& o_ppeSection ) +/** + * @brief Copies section of hardware image to HOMER + * @param i_destPtr a location in HOMER + * @param i_srcPtr a location in HW Image. + * @param i_secId XIP Section id to be copied. + * @param i_platId platform associated with the given section. + * @param o_ppeSection contains section details. + * @return IMG_BUILD_SUCCESS if successful, error code otherwise. + */ +uint32_t copySectionToHomer( uint8_t* i_destPtr, uint8_t* i_srcPtr, uint8_t i_secId, PlatId i_platId , + P9XipSection& o_ppeSection ) +{ + FAPI_INF("> copySectionToHomer"); + uint32_t retCode = IMG_BUILD_SUCCESS; + ImgSizeBank sizebank; + + do { - FAPI_INF("> copySectionToHomer"); - uint32_t retCode = IMG_BUILD_SUCCESS; - ImgSizeBank sizebank; + o_ppeSection.iv_offset = 0; + o_ppeSection.iv_size = 0; + uint32_t rcTemp = p9_xip_get_section( i_srcPtr, i_secId, &o_ppeSection ); - do + if( rcTemp ) { - o_ppeSection.iv_offset = 0; - o_ppeSection.iv_size = 0; - uint32_t rcTemp = p9_xip_get_section( i_srcPtr, i_secId, &o_ppeSection ); - - if( rcTemp ) - { - FAPI_ERR("Failed to get section 0x%08X of Plat 0x%08X", i_secId, i_platId ); - retCode = BUILD_FAIL_INVALID_SECTN; - break; - } - - FAPI_DBG("o_ppeSection.iv_offset = %X, " - "o_ppeSection.iv_size = %X, " - "i_secId %d", - o_ppeSection.iv_offset, - o_ppeSection.iv_size, - i_secId); + FAPI_ERR("Failed to get section 0x%08X of Plat 0x%08X", i_secId, i_platId ); + retCode = BUILD_FAIL_INVALID_SECTN; + break; + } - rcTemp = sizebank.isSizeGood( i_platId, i_secId, o_ppeSection.iv_size ); + FAPI_DBG("o_ppeSection.iv_offset = %X, " + "o_ppeSection.iv_size = %X, " + "i_secId %d", + o_ppeSection.iv_offset, + o_ppeSection.iv_size, + i_secId); - if ( rcTemp ) - { - FAPI_ERR("??????????Size Exceeds the permissible limit???????" ); - FAPI_ERR("Max Allowed 0x%08X (%08d) Actual Size 0x%08X (%08d)", - rcTemp, rcTemp, o_ppeSection.iv_size, o_ppeSection.iv_size); - retCode = BUILD_SEC_SIZE_OVERFLOW; - break; - } + rcTemp = sizebank.isSizeGood( i_platId, i_secId, o_ppeSection.iv_size ); - memcpy( i_destPtr, i_srcPtr + o_ppeSection.iv_offset, o_ppeSection.iv_size ); + if ( rcTemp ) + { + FAPI_ERR("??????????Size Exceeds the permissible limit???????" ); + FAPI_ERR("Max Allowed 0x%08X (%08d) Actual Size 0x%08X (%08d)", + rcTemp, rcTemp, o_ppeSection.iv_size, o_ppeSection.iv_size); + retCode = BUILD_SEC_SIZE_OVERFLOW; + break; } - while(0); - FAPI_INF("< copySectionToHomer"); - return retCode; + memcpy( i_destPtr, i_srcPtr + o_ppeSection.iv_offset, o_ppeSection.iv_size ); } + while(0); + + FAPI_INF("< copySectionToHomer"); + return retCode; +} //------------------------------------------------------------------------------ - /** - * @brief Update the CME/SGPE Image Header Flag field. - * @param i_pChipHomer points to HOMER image. - * @return fapi2 return code. - */ - fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer ) - { - uint8_t attrVal = 0; - uint32_t cmeFlag = 0; - uint32_t sgpeFlag = 0; - pgpe_flags_t pgpeFlags; +/** + * @brief Update the CME/SGPE Image Header Flag field. + * @param i_pChipHomer points to HOMER image. + * @return fapi2 return code. + */ +fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer ) +{ + uint8_t attrVal = 0; + uint32_t cmeFlag = 0; + uint32_t sgpeFlag = 0; + pgpe_flags_t pgpeFlags; - const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; - cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT]; - PgpeHeader_t* pPgpeHdr = (PgpeHeader_t*)& i_pChipHomer->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR]; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; + PgpeHeader_t* pPgpeHdr = (PgpeHeader_t*)& i_pChipHomer->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR_SIZE]; - //Handling flags common to CME and SGPE + //Handling flags common to CME and SGPE - FAPI_DBG(" ==================== CME/SGPE Flags ================="); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP4_DISABLE, - FAPI_SYSTEM, - attrVal), - "Error from FAPI_ATTR_GET for attribute ATTR_STOP4_DISABLE"); + FAPI_DBG(" ==================== CME/SGPE Flags ================="); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP4_DISABLE, + FAPI_SYSTEM, + attrVal), + "Error from FAPI_ATTR_GET for attribute ATTR_STOP4_DISABLE"); - if( attrVal ) - { - cmeFlag |= CME_STOP_4_TO_2_BIT_POS; - sgpeFlag |= SGPE_STOP_4_TO_2_BIT_POS; - } + if( attrVal ) + { + cmeFlag |= CME_STOP_4_TO_2_BIT_POS; + sgpeFlag |= SGPE_STOP_4_TO_2_BIT_POS; + } - FAPI_DBG("STOP_4_to_2 : %s", attrVal ? "TRUE" : "FALSE" ); + FAPI_DBG("STOP_4_to_2 : %s", attrVal ? "TRUE" : "FALSE" ); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP5_DISABLE, - FAPI_SYSTEM, - attrVal), - "Error from FAPI_ATTR_GET for attribute ATTR_STOP5_DISABLE"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP5_DISABLE, + FAPI_SYSTEM, + attrVal), + "Error from FAPI_ATTR_GET for attribute ATTR_STOP5_DISABLE"); - if( attrVal ) - { - cmeFlag |= CME_STOP_5_TO_4_BIT_POS; - sgpeFlag |= SGPE_STOP_5_TO_4_BIT_POS; - } + if( attrVal ) + { + cmeFlag |= CME_STOP_5_TO_4_BIT_POS; + sgpeFlag |= SGPE_STOP_5_TO_4_BIT_POS; + } - FAPI_DBG("STOP_5_to_4 : %s", attrVal ? "TRUE" : "FALSE"); + FAPI_DBG("STOP_5_to_4 : %s", attrVal ? "TRUE" : "FALSE"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP8_DISABLE, - FAPI_SYSTEM, - attrVal), - "Error from FAPI_ATTR_GET for attribute ATTR_STOP8_DISABLE"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP8_DISABLE, + FAPI_SYSTEM, + attrVal), + "Error from FAPI_ATTR_GET for attribute ATTR_STOP8_DISABLE"); - if( attrVal ) - { - cmeFlag |= CME_STOP_8_TO_5_BIT_POS; - sgpeFlag |= SGPE_STOP_8_TO_5_BIT_POS; - } + if( attrVal ) + { + cmeFlag |= CME_STOP_8_TO_5_BIT_POS; + sgpeFlag |= SGPE_STOP_8_TO_5_BIT_POS; + } - FAPI_DBG("STOP_8_to_5 : %s", attrVal ? "TRUE" : "FALSE" ); + FAPI_DBG("STOP_8_to_5 : %s", attrVal ? "TRUE" : "FALSE" ); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP11_DISABLE, - FAPI_SYSTEM, - attrVal), - "Error from FAPI_ATTR_GET for attribute ATTR_STOP11_DISABLE"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP11_DISABLE, + FAPI_SYSTEM, + attrVal), + "Error from FAPI_ATTR_GET for attribute ATTR_STOP11_DISABLE"); - if( attrVal ) - { - cmeFlag |= CME_STOP_11_TO_8_BIT_POS; - sgpeFlag |= SGPE_STOP_11_TO_8_BIT_POS; - } + if( attrVal ) + { + cmeFlag |= CME_STOP_11_TO_8_BIT_POS; + sgpeFlag |= SGPE_STOP_11_TO_8_BIT_POS; + } - FAPI_DBG("STOP_11_to_8 : %s", attrVal ? "TRUE" : "FALSE" ); + FAPI_DBG("STOP_11_to_8 : %s", attrVal ? "TRUE" : "FALSE" ); - // Set PGPE Header Flags from Attributes - FAPI_DBG(" -------------------- PGPE Flags -----------------"); - pgpeFlags.value = 0; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PGPE_HCODE_FUNCTION_ENABLE, - FAPI_SYSTEM, - attrVal), - "Error from FAPI_ATTR_GET for attribute ATTR_PGPE_HCODE_FUNCTION_ENABLE"); + // Set PGPE Header Flags from Attributes + FAPI_DBG(" -------------------- PGPE Flags -----------------"); + pgpeFlags.value = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PGPE_HCODE_FUNCTION_ENABLE, + FAPI_SYSTEM, + attrVal), + "Error from FAPI_ATTR_GET for attribute ATTR_PGPE_HCODE_FUNCTION_ENABLE"); - // If 0 (Hcode disabled), then set the occ_opc_immed_response flag bit - if( !attrVal ) - { - pgpeFlags.fields.occ_ipc_immed_response = 1; - } + // If 0 (Hcode disabled), then set the occ_opc_immed_response flag bit + if( !attrVal ) + { + pgpeFlags.fields.occ_ipc_immed_response = 1; + } - FAPI_DBG("PGPE Hcode Mode : %s", attrVal ? "PSTATES Enabled" : "OCC IPC Immediate Response Mode" ); + FAPI_DBG("PGPE Hcode Mode : %s", attrVal ? "PSTATES Enabled" : "OCC IPC Immediate Response Mode" ); - // Updating flag fields in the headers - pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(cmeFlag); - pSgpeHdr->g_sgpe_reserve_flags = SWIZZLE_4_BYTE(sgpeFlag); - pPgpeHdr->g_pgpe_flags = SWIZZLE_2_BYTE(pgpeFlags.value); + // Updating flag fields in the headers + pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(cmeFlag); + pSgpeHdr->g_sgpe_reserve_flags = SWIZZLE_4_BYTE(sgpeFlag); + pPgpeHdr->g_pgpe_flags = SWIZZLE_2_BYTE(pgpeFlags.value); - FAPI_INF("CME Flag Value : 0x%08x", SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags)); - FAPI_INF("SGPE Flag Value : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags)); - FAPI_INF("PGPE Flag Value : 0x%08x", SWIZZLE_2_BYTE(pPgpeHdr->g_pgpe_flags)); - FAPI_DBG(" -------------------- CME/SGPE Flags Ends ---------------=="); + FAPI_INF("CME Flag Value : 0x%08x", SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags)); + FAPI_INF("SGPE Flag Value : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags)); + FAPI_INF("PGPE Flag Value : 0x%08x", SWIZZLE_2_BYTE(pPgpeHdr->g_pgpe_flags)); + FAPI_DBG(" -------------------- CME/SGPE Flags Ends ---------------=="); - fapi_try_exit: - return fapi2::current_err; - } +fapi_try_exit: + return fapi2::current_err; +} //------------------------------------------------------------------------------ - /** - * @brief updates various CPMR fields which are associated with scan rings. - * @param i_pChipHomer points to start of P9 HOMER. - */ - void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer ) +/** + * @brief updates various CPMR fields which are associated with scan rings. + * @param i_pChipHomer points to start of P9 HOMER. + */ +void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer ) +{ + cpmrHeader_t* pCpmrHdr = + (cpmrHeader_t*) & (i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); + cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + + //Updating CPMR Header using info from CME Header + pCpmrHdr->cmeImgOffset = SWIZZLE_4_BYTE((CME_IMAGE_CPMR_OFFSET >> CME_BLK_SIZE_SHIFT)); + pCpmrHdr->cmePstateOffset = CME_IMAGE_CPMR_OFFSET + SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset); + pCpmrHdr->cmePstateOffset = SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset); + pCpmrHdr->cmePstateLength = pCmeHdr->g_cme_pstate_region_length; + pCpmrHdr->cmeImgLength = pCmeHdr->g_cme_hcode_length;// already swizzled + pCpmrHdr->coreScomOffset = SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_CPMR_OFFSET); + pCpmrHdr->coreScomLength = SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_SIZE_TOTAL); + + if( pCmeHdr->g_cme_common_ring_length ) { - cpmrHeader_t* pCpmrHdr = - (cpmrHeader_t*) & (i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); - cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - - //Updating CPMR Header using info from CME Header - pCpmrHdr->cmeImgOffset = SWIZZLE_4_BYTE((CPMR_CME_HCODE_OFFSET >> CME_BLK_SIZE_SHIFT)); - pCpmrHdr->cmePstateOffset = CPMR_CME_HCODE_OFFSET + SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset); - pCpmrHdr->cmePstateOffset = SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset); - pCpmrHdr->cmePstateLength = pCmeHdr->g_cme_pstate_region_length; - pCpmrHdr->cmeImgLength = pCmeHdr->g_cme_hcode_length;// already swizzled - pCpmrHdr->coreScomOffset = SWIZZLE_4_BYTE(CORE_SCOM_START); - pCpmrHdr->coreScomLength = SWIZZLE_4_BYTE(CORE_SCOM_RES_SIZE); - - if( pCmeHdr->g_cme_common_ring_length ) - { - pCpmrHdr->cmeCommonRingOffset = CPMR_CME_HCODE_OFFSET + SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset); - pCpmrHdr->cmeCommonRingOffset = SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset); - pCpmrHdr->cmeCommonRingLength = pCmeHdr->g_cme_common_ring_length; - } - - if( pCmeHdr->g_cme_max_spec_ring_length ) - { - pCpmrHdr->coreSpecRingOffset = ( SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) << CME_BLK_SIZE_SHIFT ) + - SWIZZLE_4_BYTE( pCpmrHdr->cmeImgLength) + - SWIZZLE_4_BYTE(pCpmrHdr->cmePstateLength) + - SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength); - pCpmrHdr->coreSpecRingOffset = (pCpmrHdr->coreSpecRingOffset + CME_BLOCK_READ_LEN - 1) >> CME_BLK_SIZE_SHIFT; - pCpmrHdr->coreSpecRingOffset = SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset); - pCpmrHdr->coreSpecRingLength = pCmeHdr->g_cme_max_spec_ring_length; // already swizzled - } - - //Updating CME Image header - pCmeHdr->g_cme_magic_number = SWIZZLE_8_BYTE(CME_MAGIC_NUMBER); - pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length) + - SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length) + - SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length); - pCmeHdr->g_cme_scom_offset = - ((pCmeHdr->g_cme_scom_offset + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT); - //Adding to it instance ring length which is already a multiple of 32B - pCmeHdr->g_cme_scom_offset += SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length); - pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset); - pCmeHdr->g_cme_scom_length = SWIZZLE_4_BYTE(CORE_SCOM_PER_CME); - - FAPI_INF("========================= CME Header Start =================================="); - char magicWord[16] = {0}; - uint64_t temp = pCmeHdr->g_cme_magic_number; - memcpy(magicWord, &temp, sizeof(uint64_t)); - FAPI_DBG(" Magic Num : %s", magicWord); - FAPI_INF(" HC Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_offset)); - FAPI_INF(" HC Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length)); - FAPI_INF(" PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset)); - FAPI_INF(" PS Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length)); - FAPI_INF(" CR Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset)); - FAPI_INF(" CR Ovrd Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_cmn_ring_ovrd_offset )); - FAPI_INF(" CR Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length)); - FAPI_INF(" CSR Offset : 0x%08X (Real offset / 32) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset)); - FAPI_INF(" CSR Length : 0x%08X (Real length / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length) ); - FAPI_INF(" SCOM Offset : 0x%08X (Real offset / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset)); - FAPI_INF(" SCOM Area Len : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_length)); - FAPI_INF(" CPMR Phy Add : 0x%016lx", SWIZZLE_8_BYTE(pCmeHdr->g_cme_cpmr_PhyAddr)); - FAPI_INF("========================= CME Header End =================================="); - - FAPI_INF("==========================CPMR Header==========================================="); - temp = pCpmrHdr->magic_number; - memcpy(magicWord, &temp, sizeof(uint64_t)); - FAPI_DBG(" Magic Num : %s", magicWord); - FAPI_INF(" CME HC Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset)); - FAPI_INF(" CME HC Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength)); - FAPI_INF(" PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset)); - FAPI_INF(" PS Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateLength)); - FAPI_INF(" CR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset)); - FAPI_INF(" CR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength)); - FAPI_INF(" CSR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset)); - FAPI_INF(" CSR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingLength)); - FAPI_INF(" Core SCOM Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomOffset)); - FAPI_INF(" Core SCOM Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomLength )); - FAPI_INF("==================================CPMR Ends====================================="); - + pCpmrHdr->cmeCommonRingOffset = CME_IMAGE_CPMR_OFFSET + SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset); + pCpmrHdr->cmeCommonRingOffset = SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset); + pCpmrHdr->cmeCommonRingLength = pCmeHdr->g_cme_common_ring_length; } -//------------------------------------------------------------------------------ - /** - * @brief updates various CPMR fields which are associated with self restore code. - * @param i_pChipHomer points to start of P9 HOMER. - * @param i_fuseState core fuse status - */ - void updateCpmrHeaderSR( Homerlayout_t* i_pChipHomer, uint8_t i_fusedState ) + if( pCmeHdr->g_cme_max_spec_ring_length ) { - FAPI_INF("> updateCpmrHeaderSR"); - cpmrHeader_t* pCpmrHdr = - (cpmrHeader_t*) & (i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); - - cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - //populate CPMR header - pCpmrHdr->fusedModeStatus = i_fusedState ? FUSED_MODE : NONFUSED_MODE; - pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(i_fusedState ? 1 : 0); - - FAPI_INF("CPMR SR"); - FAPI_INF(" Fuse Mode = 0x%08X CME Image Flag = 0x%08X", pCpmrHdr->fusedModeStatus, - SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags)); - FAPI_DBG(" Offset = 0x%08X, Header value 0x%08X (Real offset / 32)", - SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) * 32, - SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset)); - FAPI_DBG(" Size = 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength)); - - FAPI_INF("< updateCpmrHeaderSR"); + pCpmrHdr->coreSpecRingOffset = ( SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) << CME_BLK_SIZE_SHIFT ) + + SWIZZLE_4_BYTE( pCpmrHdr->cmeImgLength) + + SWIZZLE_4_BYTE(pCpmrHdr->cmePstateLength) + + SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength); + pCpmrHdr->coreSpecRingOffset = (pCpmrHdr->coreSpecRingOffset + CME_BLOCK_READ_LEN - 1) >> CME_BLK_SIZE_SHIFT; + pCpmrHdr->coreSpecRingOffset = SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset); + pCpmrHdr->coreSpecRingLength = pCmeHdr->g_cme_max_spec_ring_length; // already swizzled } -//------------------------------------------------------------------------------ - /** - * @brief updates various QPMR header region in HOMER. - * @param i_pChipHomer points to start of P9 HOMER. - * @param io_qpmrHdr temp instance of QpmrHeaderLayout_t used for data collection. - */ - uint32_t updateQpmrHeader( Homerlayout_t* i_pChipHomer, QpmrHeaderLayout_t& io_qpmrHdr ) - { - uint32_t rc = IMG_BUILD_SUCCESS; + //Updating CME Image header + pCmeHdr->g_cme_magic_number = SWIZZLE_8_BYTE(CME_MAGIC_NUMBER); + pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length) + + SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length) + + SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length); + pCmeHdr->g_cme_scom_offset = + ((pCmeHdr->g_cme_scom_offset + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT); + //Adding to it instance ring length which is already a multiple of 32B + pCmeHdr->g_cme_scom_offset += SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length); + pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset); + pCmeHdr->g_cme_scom_length = SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_SIZE_PER_CME); + + FAPI_INF("========================= CME Header Start =================================="); + char magicWord[16] = {0}; + uint64_t temp = pCmeHdr->g_cme_magic_number; + memcpy(magicWord, &temp, sizeof(uint64_t)); + FAPI_DBG(" Magic Num : %s", magicWord); + FAPI_INF(" HC Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_offset)); + FAPI_INF(" HC Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length)); + FAPI_INF(" PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset)); + FAPI_INF(" PS Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length)); + FAPI_INF(" CR Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset)); + FAPI_INF(" CR Ovrd Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_cmn_ring_ovrd_offset )); + FAPI_INF(" CR Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length)); + FAPI_INF(" CSR Offset : 0x%08X (Real offset / 32) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset)); + FAPI_INF(" CSR Length : 0x%08X (Real length / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length) ); + FAPI_INF(" SCOM Offset : 0x%08X (Real offset / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset)); + FAPI_INF(" SCOM Area Len : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_length)); + FAPI_INF(" CPMR Phy Add : 0x%016lx", SWIZZLE_8_BYTE(pCmeHdr->g_cme_cpmr_PhyAddr)); + FAPI_INF("========================= CME Header End =================================="); + + FAPI_INF("==========================CPMR Header==========================================="); + temp = pCpmrHdr->magic_number; + memcpy(magicWord, &temp, sizeof(uint64_t)); + FAPI_DBG(" Magic Num : %s", magicWord); + FAPI_INF(" CME HC Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset)); + FAPI_INF(" CME HC Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength)); + FAPI_INF(" PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset)); + FAPI_INF(" PS Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateLength)); + FAPI_INF(" CR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset)); + FAPI_INF(" CR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength)); + FAPI_INF(" CSR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset)); + FAPI_INF(" CSR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingLength)); + FAPI_INF(" Core SCOM Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomOffset)); + FAPI_INF(" Core SCOM Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomLength )); + FAPI_INF("==================================CPMR Ends====================================="); + +} +//------------------------------------------------------------------------------ +/** + * @brief updates various CPMR fields which are associated with self restore code. + * @param i_pChipHomer points to start of P9 HOMER. + * @param i_fuseState core fuse status + */ +void updateCpmrHeaderSR( Homerlayout_t* i_pChipHomer, uint8_t i_fusedState ) +{ + FAPI_INF("> updateCpmrHeaderSR"); + cpmrHeader_t* pCpmrHdr = + (cpmrHeader_t*) & (i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); + + cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + //populate CPMR header + pCpmrHdr->fusedModeStatus = i_fusedState ? uint32_t(FUSED_CORE_MODE) : + uint32_t(NONFUSED_CORE_MODE); + pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(i_fusedState ? 1 : 0); + + FAPI_INF("CPMR SR"); + FAPI_INF(" Fuse Mode = 0x%08X CME Image Flag = 0x%08X", pCpmrHdr->fusedModeStatus, + SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags)); + FAPI_DBG(" Offset = 0x%08X, Header value 0x%08X (Real offset / 32)", + SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) * 32, + SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset)); + FAPI_DBG(" Size = 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength)); + + FAPI_INF("< updateCpmrHeaderSR"); +} - QpmrHeaderLayout_t* pQpmrHdr = ( QpmrHeaderLayout_t*) & (i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader); - sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT]; - memcpy( pQpmrHdr, &io_qpmrHdr, sizeof( QpmrHeaderLayout_t ) ); - //FIXME Populating headers fields with max possible values for now. This is to keep things in line with SGPE - //bootloader design. SGPE bootloader doesn't expect a hole in image layout how ever due to current design of - //hcode image build there are holes between various section of image say common and instance ring. - - pQpmrHdr->magic_number = SWIZZLE_8_BYTE(QPMR_MAGIC_NUMBER); - pSgpeHdr->g_sgpe_magic_number = SWIZZLE_8_BYTE(SGPE_MAGIC_NUMBER); - - FAPI_INF("==============================QPMR=================================="); - char magicWord[16] = {0}; - uint64_t temp = pQpmrHdr->magic_number; - memcpy(magicWord, &temp, sizeof(uint64_t)); - FAPI_DBG(" Magic Num : %s", magicWord); - FAPI_DBG(" Build Date : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->buildDate)); - FAPI_DBG(" Version : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->buildVersion)); - FAPI_DBG(" BC Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootCopierOffset)); - FAPI_DBG(" BL Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootLoaderOffset)); - FAPI_DBG(" BL Size : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootLoaderLength)); - FAPI_DBG(" HC Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgOffset)); - FAPI_DBG(" HC Size : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgLength)); - FAPI_DBG(" Cmn Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingOffset) ); - FAPI_DBG(" Cmn Ring Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingLength) ); - FAPI_DBG(" Cmn Ring Ovrd Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonOvrdOffset) ); - FAPI_DBG(" Cmn Ring Ovrd Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonOvrdLength) ); - FAPI_DBG(" Quad Spec Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingOffset) ); - FAPI_DBG(" Quad Spec Ring Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingLength) ); - FAPI_DBG("==============================QPMR Ends=============================="); - - FAPI_DBG("===========================SGPE Image Hdr============================="); - temp = pSgpeHdr->g_sgpe_magic_number; - memcpy(magicWord, &temp, sizeof(uint64_t)); - FAPI_DBG(" Magic Num : %s", magicWord); - FAPI_DBG(" Cmn Ring Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_occ_offset )); - FAPI_DBG(" Override Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_ovrd_occ_offset )); - FAPI_DBG(" Flags : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags )); - FAPI_DBG(" Quad Spec Ring Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_spec_ring_occ_offset )); - FAPI_DBG(" Quad SCOM SRAM Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_offset)); - FAPI_DBG(" Quad SCOM Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_mem_offset)); - FAPI_DBG(" Quad SCOM Mem Length : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_mem_length )); - FAPI_DBG(" 24x7 Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_24x7_offset )); - FAPI_DBG(" 24x7 Length : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_24x7_length )); - FAPI_DBG("========================SGPE Image Hdr Ends==========================="); - - return rc; - } +//------------------------------------------------------------------------------ +/** + * @brief updates various QPMR header region in HOMER. + * @param i_pChipHomer points to start of P9 HOMER. + * @param io_qpmrHdr temp instance of QpmrHeaderLayout_t used for data collection. + */ +uint32_t updateQpmrHeader( Homerlayout_t* i_pChipHomer, QpmrHeaderLayout_t& io_qpmrHdr ) +{ + uint32_t rc = IMG_BUILD_SUCCESS; + + + QpmrHeaderLayout_t* pQpmrHdr = ( QpmrHeaderLayout_t*) & (i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader); + sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; + memcpy( pQpmrHdr, &io_qpmrHdr, sizeof( QpmrHeaderLayout_t ) ); + //FIXME Populating headers fields with max possible values for now. This is to keep things in line with SGPE + //bootloader design. SGPE bootloader doesn't expect a hole in image layout how ever due to current design of + //hcode image build there are holes between various section of image say common and instance ring. + + pQpmrHdr->magic_number = SWIZZLE_8_BYTE(QPMR_MAGIC_NUMBER); + pSgpeHdr->g_sgpe_magic_number = SWIZZLE_8_BYTE(SGPE_MAGIC_NUMBER); + + FAPI_INF("==============================QPMR=================================="); + char magicWord[16] = {0}; + uint64_t temp = pQpmrHdr->magic_number; + memcpy(magicWord, &temp, sizeof(uint64_t)); + FAPI_DBG(" Magic Num : %s", magicWord); + FAPI_DBG(" Build Date : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->buildDate)); + FAPI_DBG(" Version : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->buildVersion)); + FAPI_DBG(" BC Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootCopierOffset)); + FAPI_DBG(" BL Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootLoaderOffset)); + FAPI_DBG(" BL Size : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootLoaderLength)); + FAPI_DBG(" HC Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgOffset)); + FAPI_DBG(" HC Size : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgLength)); + FAPI_DBG(" Cmn Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingOffset) ); + FAPI_DBG(" Cmn Ring Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingLength) ); + FAPI_DBG(" Cmn Ring Ovrd Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonOvrdOffset) ); + FAPI_DBG(" Cmn Ring Ovrd Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonOvrdLength) ); + FAPI_DBG(" Quad Spec Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingOffset) ); + FAPI_DBG(" Quad Spec Ring Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingLength) ); + FAPI_DBG("==============================QPMR Ends=============================="); + + FAPI_DBG("===========================SGPE Image Hdr============================="); + temp = pSgpeHdr->g_sgpe_magic_number; + memcpy(magicWord, &temp, sizeof(uint64_t)); + FAPI_DBG(" Magic Num : %s", magicWord); + FAPI_DBG(" Cmn Ring Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_occ_offset )); + FAPI_DBG(" Override Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_ovrd_occ_offset )); + FAPI_DBG(" Flags : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags )); + FAPI_DBG(" Quad Spec Ring Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_spec_ring_occ_offset )); + FAPI_DBG(" Quad SCOM SRAM Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_offset)); + FAPI_DBG(" Quad SCOM Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_mem_offset)); + FAPI_DBG(" Quad SCOM Mem Length : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_mem_length )); + FAPI_DBG(" 24x7 Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_24x7_offset )); + FAPI_DBG(" 24x7 Length : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_24x7_length )); + FAPI_DBG("========================SGPE Image Hdr Ends==========================="); + + return rc; +} //------------------------------------------------------------------------------ - /** - * @brief copies image section associated with SGPE from HW Image to HOMER - * @param[in] i_pImageIn points to start of hardware image. - * @param[in] i_pChipHomer points to HOMER image. - * @param[in] i_imgType image sections to be built - */ - uint32_t buildSgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChipHomer, ImageType_t i_imgType, - QpmrHeaderLayout_t& o_qpmrHdr ) +/** + * @brief copies image section associated with SGPE from HW Image to HOMER + * @param[in] i_pImageIn points to start of hardware image. + * @param[in] i_pChipHomer points to HOMER image. + * @param[in] i_imgType image sections to be built + */ +uint32_t buildSgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChipHomer, ImageType_t i_imgType, + QpmrHeaderLayout_t& o_qpmrHdr ) +{ + FAPI_INF("> buildSgpeImage"); + uint32_t retCode = IMG_BUILD_SUCCESS; + + do { - FAPI_INF("> buildSgpeImage"); - uint32_t retCode = IMG_BUILD_SUCCESS; + uint32_t rcTemp = 0; + //Let us find XIP Header for SGPE + P9XipSection ppeSection; + uint8_t* pSgpeImg = NULL; - do + if(!i_imgType.sgpeHcodeBuild ) { - uint32_t rcTemp = 0; - //Let us find XIP Header for SGPE - P9XipSection ppeSection; - uint8_t* pSgpeImg = NULL; - - if(!i_imgType.sgpeHcodeBuild ) - { - break; - } + break; + } - // Let us start with a clean slate in quad common ring area. - memset( (uint8_t*)&i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage, 0x00, SGPE_IMAGE_SIZE ); - rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_SGPE, &ppeSection ); + // Let us start with a clean slate in quad common ring area. + memset( (uint8_t*)&i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage, 0x00, SGPE_IMAGE_SIZE ); + rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_SGPE, &ppeSection ); - if( rcTemp ) - { - FAPI_ERR("Failed to get SGPE XIP Image Header" ); - retCode = BUILD_FAIL_SGPE_IMAGE; - break; - } - - pSgpeImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); - FAPI_DBG("HW image SGPE Offset = 0x%08X", ppeSection.iv_offset); + if( rcTemp ) + { + FAPI_ERR("Failed to get SGPE XIP Image Header" ); + retCode = BUILD_FAIL_SGPE_IMAGE; + break; + } - FAPI_INF("QPMR Header"); - rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader, - pSgpeImg, - P9_XIP_SECTION_SGPE_QPMR, - PLAT_SGPE, - ppeSection ); + pSgpeImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); + FAPI_DBG("HW image SGPE Offset = 0x%08X", ppeSection.iv_offset); - if( rcTemp ) - { - FAPI_ERR("Failed to copy QPMR Header"); - retCode = BUILD_FAIL_SGPE_QPMR; - break; - } + FAPI_INF("QPMR Header"); + rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader, + pSgpeImg, + P9_XIP_SECTION_SGPE_QPMR, + PLAT_SGPE, + ppeSection ); - //updating local instance of QPMR header - memcpy( &o_qpmrHdr, i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader, sizeof(QpmrHeaderLayout_t)); + if( rcTemp ) + { + FAPI_ERR("Failed to copy QPMR Header"); + retCode = BUILD_FAIL_SGPE_QPMR; + break; + } - FAPI_DBG("SGPE Boot Copier"); - rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.l1BootLoader, - pSgpeImg, - P9_XIP_SECTION_SGPE_LVL1_BL, - PLAT_SGPE, - ppeSection ); + //updating local instance of QPMR header + memcpy( &o_qpmrHdr, i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader, sizeof(QpmrHeaderLayout_t)); - if( rcTemp ) - { - FAPI_ERR("Failed to copy Level1 bootloader"); - retCode = BUILD_FAIL_SGPE_BL1; - break; - } + FAPI_DBG("SGPE Boot Copier"); + rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.l1BootLoader, + pSgpeImg, + P9_XIP_SECTION_SGPE_LVL1_BL, + PLAT_SGPE, + ppeSection ); - o_qpmrHdr.bootCopierOffset = QPMR_HEADER_SIZE; - FAPI_DBG("SGPE Boot Copier Size = 0x%08X", - o_qpmrHdr.bootCopierOffset); + if( rcTemp ) + { + FAPI_ERR("Failed to copy Level1 bootloader"); + retCode = BUILD_FAIL_SGPE_BL1; + break; + } - FAPI_DBG(" SGPE Boot Loader"); + o_qpmrHdr.bootCopierOffset = QPMR_HEADER_SIZE; + FAPI_DBG("SGPE Boot Copier Size = 0x%08X", + o_qpmrHdr.bootCopierOffset); - rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.l2BootLoader, - pSgpeImg, - P9_XIP_SECTION_SGPE_LVL2_BL, - PLAT_SGPE, - ppeSection ); + FAPI_DBG(" SGPE Boot Loader"); - if( rcTemp ) - { - FAPI_ERR("Failed to copy Level2 bootloader"); - retCode = BUILD_FAIL_SGPE_BL2; - break; - } + rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.l2BootLoader, + pSgpeImg, + P9_XIP_SECTION_SGPE_LVL2_BL, + PLAT_SGPE, + ppeSection ); - o_qpmrHdr.bootLoaderOffset = o_qpmrHdr.bootCopierOffset + SGPE_LVL_1_BOOT_LOAD_SIZE; - o_qpmrHdr.bootLoaderLength = ppeSection.iv_size; + if( rcTemp ) + { + FAPI_ERR("Failed to copy Level2 bootloader"); + retCode = BUILD_FAIL_SGPE_BL2; + break; + } - FAPI_INF("SGPE Boot Loader QPMR Offset = 0x%08X, Size = 0x%08X", - o_qpmrHdr.bootLoaderOffset, o_qpmrHdr.bootLoaderLength); + o_qpmrHdr.bootLoaderOffset = o_qpmrHdr.bootCopierOffset + SGPE_BOOT_COPIER_SIZE; + o_qpmrHdr.bootLoaderLength = ppeSection.iv_size; - rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage, - pSgpeImg, - P9_XIP_SECTION_SGPE_HCODE, - PLAT_SGPE, - ppeSection ); + FAPI_INF("SGPE Boot Loader QPMR Offset = 0x%08X, Size = 0x%08X", + o_qpmrHdr.bootLoaderOffset, o_qpmrHdr.bootLoaderLength); - if( rcTemp ) - { - FAPI_ERR("Failed to copy SGPE hcode"); - retCode = BUILD_FAIL_SGPE_HCODE; - break; - } + rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage, + pSgpeImg, + P9_XIP_SECTION_SGPE_HCODE, + PLAT_SGPE, + ppeSection ); - memset( i_pChipHomer->qpmrRegion.cacheScomRegion, 0x00, - CACHE_SCOM_RESTORE_SIZE ); + if( rcTemp ) + { + FAPI_ERR("Failed to copy SGPE hcode"); + retCode = BUILD_FAIL_SGPE_HCODE; + break; + } - o_qpmrHdr.sgpeImgOffset = o_qpmrHdr.bootLoaderOffset + SGPE_LVL_2_BOOT_LOAD_SIZE; + memset( i_pChipHomer->qpmrRegion.cacheScomRegion, 0x00, + QUAD_SCOM_RESTORE_SIZE_TOTAL ); - FAPI_DBG("SGPE Hcode QPMR Offset = 0x%08X, Size = 0x%08X", - SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgOffset), - SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgLength)); + o_qpmrHdr.sgpeImgOffset = o_qpmrHdr.bootLoaderOffset + SGPE_BOOT_LOADER_SIZE; - o_qpmrHdr.sgpeImgOffset = o_qpmrHdr.bootLoaderOffset + SGPE_LVL_2_BOOT_LOAD_SIZE; + FAPI_DBG("SGPE Hcode QPMR Offset = 0x%08X, Size = 0x%08X", + SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgOffset), + SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgLength)); - o_qpmrHdr.sgpeImgLength = SWIZZLE_4_BYTE(ppeSection.iv_size); - o_qpmrHdr.bootLoaderOffset = SWIZZLE_4_BYTE(o_qpmrHdr.bootLoaderOffset); - //let us take care of endianess now. - o_qpmrHdr.bootCopierOffset = SWIZZLE_4_BYTE(o_qpmrHdr.bootCopierOffset); - o_qpmrHdr.bootLoaderLength = SWIZZLE_4_BYTE(o_qpmrHdr.bootLoaderLength); - o_qpmrHdr.sgpeImgOffset = SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgOffset); + o_qpmrHdr.sgpeImgOffset = o_qpmrHdr.bootLoaderOffset + SGPE_BOOT_LOADER_SIZE; + o_qpmrHdr.sgpeImgLength = SWIZZLE_4_BYTE(ppeSection.iv_size); + o_qpmrHdr.bootLoaderOffset = SWIZZLE_4_BYTE(o_qpmrHdr.bootLoaderOffset); + //let us take care of endianess now. + o_qpmrHdr.bootCopierOffset = SWIZZLE_4_BYTE(o_qpmrHdr.bootCopierOffset); + o_qpmrHdr.bootLoaderLength = SWIZZLE_4_BYTE(o_qpmrHdr.bootLoaderLength); + o_qpmrHdr.sgpeImgOffset = SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgOffset); - //FIXME Need to confirm it - o_qpmrHdr.quadScomOffset = SWIZZLE_4_BYTE(CACHE_SCOM_START); - sgpeHeader_t* pImgHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT]; - pImgHdr->g_sgpe_cmn_ring_occ_offset = o_qpmrHdr.sgpeImgLength; - pImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset = 0; - pImgHdr->g_sgpe_spec_ring_occ_offset = 0; - pImgHdr->g_sgpe_scom_offset = 0; + //FIXME Need to confirm it + o_qpmrHdr.quadScomOffset = SWIZZLE_4_BYTE(QUAD_SCOM_RESTORE_QPMR_OFFSET); + sgpeHeader_t* pImgHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; + pImgHdr->g_sgpe_ivpr_address = OCC_SRAM_SGPE_BASE_ADDR; + pImgHdr->g_sgpe_cmn_ring_occ_offset = o_qpmrHdr.sgpeImgLength; + pImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset = 0; + pImgHdr->g_sgpe_spec_ring_occ_offset = 0; + pImgHdr->g_sgpe_scom_offset = 0; - FAPI_INF("SGPE Header"); - FAPI_INF(" Magic Num = 0x%16lX", SWIZZLE_8_BYTE(pImgHdr->g_sgpe_magic_number)); - FAPI_INF(" Reset Addr = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_reset_address)); - FAPI_INF(" IVPR Addr = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_ivpr_address)); - FAPI_INF(" Build Date = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_build_date)); - FAPI_INF(" Version = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_build_ver)); - FAPI_INF(" CR OCC Offset = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_cmn_ring_occ_offset)); - FAPI_INF(" CR Ovrd Offset = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset)); - } - while(0); + FAPI_INF("SGPE Header"); + FAPI_INF(" Magic Num = 0x%16lX", SWIZZLE_8_BYTE(pImgHdr->g_sgpe_magic_number)); + FAPI_INF(" Reset Addr = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_reset_address)); + FAPI_INF(" IVPR Addr = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_ivpr_address)); + FAPI_INF(" Build Date = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_build_date)); + FAPI_INF(" Version = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_build_ver)); + FAPI_INF(" CR OCC Offset = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_cmn_ring_occ_offset)); + FAPI_INF(" CR Ovrd Offset = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset)); - FAPI_INF("< buildSgpeImag") - return retCode; } + while(0); + + FAPI_INF("< buildSgpeImag") + return retCode; +} //------------------------------------------------------------------------------ - /** - * @brief copies core self restore section from hardware image to HOMER. - * @param[in] i_pImageIn points to start of hardware image. - * @param[in] i_pChipHomer points to HOMER image. - * @param[in] i_imgType image sections to be built - * @param[in] i_fuseState fuse state of core. - * @return IMG_BUILD_SUCCESS if function succeeds, error code otherwise. - */ - uint32_t buildCoreRestoreImage( void* const i_pImageIn, - Homerlayout_t* i_pChipHomer, ImageType_t i_imgType, - uint8_t i_fusedState ) +/** + * @brief copies core self restore section from hardware image to HOMER. + * @param[in] i_pImageIn points to start of hardware image. + * @param[in] i_pChipHomer points to HOMER image. + * @param[in] i_imgType image sections to be built + * @param[in] i_fuseState fuse state of core. + * @return IMG_BUILD_SUCCESS if function succeeds, error code otherwise. + */ +uint32_t buildCoreRestoreImage( void* const i_pImageIn, + Homerlayout_t* i_pChipHomer, ImageType_t i_imgType, + uint8_t i_fusedState ) +{ + uint32_t retCode = IMG_BUILD_SUCCESS; + + do { - uint32_t retCode = IMG_BUILD_SUCCESS; + uint32_t rcTemp = 0; + //Let us find XIP Header for Core Self Restore Image + P9XipSection ppeSection; + uint8_t* pSelfRestImg = NULL; + rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_RESTORE, &ppeSection ); - do + if( rcTemp ) { - uint32_t rcTemp = 0; - //Let us find XIP Header for Core Self Restore Image - P9XipSection ppeSection; - uint8_t* pSelfRestImg = NULL; - rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_RESTORE, &ppeSection ); - - if( rcTemp ) - { - FAPI_ERR("Failed to get P9 Self restore Image Header" ); - retCode = BUILD_FAIL_SELF_REST_IMAGE; - break; - } - - pSelfRestImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); - - if( i_imgType.selfRestoreBuild ) - { - // first 256 bytes is expected to be zero here. It is by purpose. Just after this step, - // we will add CPMR header in that area. - FAPI_INF("Self Restore Image install"); - FAPI_INF(" Offset = 0x%08X, Size = 0x%08X", - ppeSection.iv_offset, ppeSection.iv_size); - rcTemp = copySectionToHomer( i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.region, - pSelfRestImg, - P9_XIP_SECTION_RESTORE_SELF, - PLAT_SELF, - ppeSection ); - - if( rcTemp ) - { - FAPI_ERR("Failed to copy SRESET Handler"); - retCode = BUILD_FAIL_SRESET_HNDLR; - break; - } + FAPI_ERR("Failed to get P9 Self restore Image Header" ); + retCode = BUILD_FAIL_SELF_REST_IMAGE; + break; + } - } + pSelfRestImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); - // adding CPMR header in first 256 bytes of the CPMR. - FAPI_INF("Overlay CPMR Header at the beginning of CPMR"); + if( i_imgType.selfRestoreBuild ) + { + // first 256 bytes is expected to be zero here. It is by purpose. Just after this step, + // we will add CPMR header in that area. + FAPI_INF("Self Restore Image install"); + FAPI_INF(" Offset = 0x%08X, Size = 0x%08X", + ppeSection.iv_offset, ppeSection.iv_size); rcTemp = copySectionToHomer( i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.region, pSelfRestImg, - P9_XIP_SECTION_RESTORE_CPMR, + P9_XIP_SECTION_RESTORE_SELF, PLAT_SELF, ppeSection ); if( rcTemp ) { - FAPI_ERR("Failed to copy CPMR header"); - retCode = BUILD_FAIL_CPMR_HDR; + FAPI_ERR("Failed to copy SRESET Handler"); + retCode = BUILD_FAIL_SRESET_HNDLR; break; } - //Pad undefined or runtime section with ATTN Opcode - //Padding SPR restore area with ATTN Opcode - FAPI_INF("Padding CPMR Core Restore portion with Attn opcodes"); - uint32_t wordCnt = 0; - uint32_t l_fillBlr = SWIZZLE_4_BYTE(BLR_INST); - uint32_t l_fillAttn = SWIZZLE_4_BYTE(PAD_OPCODE); + } - while( wordCnt < CORE_RESTORE_SIZE ) - { + // adding CPMR header in first 256 bytes of the CPMR. + FAPI_INF("Overlay CPMR Header at the beginning of CPMR"); + rcTemp = copySectionToHomer( i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.region, + pSelfRestImg, + P9_XIP_SECTION_RESTORE_CPMR, + PLAT_SELF, + ppeSection ); - uint32_t l_fillPattern = 0; + if( rcTemp ) + { + FAPI_ERR("Failed to copy CPMR header"); + retCode = BUILD_FAIL_CPMR_HDR; + break; + } - if( ( 0 == wordCnt ) || ( 0 == ( wordCnt % THREAD_RESTORE_AREA_SIZE ) )) - { - l_fillPattern = l_fillBlr; - } - else - { - l_fillPattern = l_fillAttn; - } + //Pad undefined or runtime section with ATTN Opcode + //Padding SPR restore area with ATTN Opcode + FAPI_INF("Padding CPMR Core Restore portion with Attn opcodes"); + uint32_t wordCnt = 0; + uint32_t l_fillBlr = SWIZZLE_4_BYTE(SELF_RESTORE_BLR_INST); + uint32_t l_fillAttn = SWIZZLE_4_BYTE(CORE_RESTORE_PAD_OPCODE); + + while( wordCnt < SELF_RESTORE_CORE_REGS_SIZE ) + { - //Lab Need: First instruction in thread SPR restore region should be a blr instruction. - //This helps in a specific lab scenario. If Self Restore region is populated only for - //select number of threads, other threads will not hit attention during the self restore - //sequence. Instead, execution will hit a blr and control should return to thread launcher - //region. + uint32_t l_fillPattern = 0; - memcpy( (uint32_t*)&i_pChipHomer->cpmrRegion.selfRestoreRegion.coreSelfRestore[wordCnt], - &l_fillPattern, - sizeof( uint32_t )); - wordCnt += 4; + if( ( 0 == wordCnt ) || ( 0 == ( wordCnt % CORE_RESTORE_SIZE_PER_THREAD ) )) + { + l_fillPattern = l_fillBlr; + } + else + { + l_fillPattern = l_fillAttn; } - updateCpmrHeaderSR( i_pChipHomer, i_fusedState ); + //Lab Need: First instruction in thread SPR restore region should be a blr instruction. + //This helps in a specific lab scenario. If Self Restore region is populated only for + //select number of threads, other threads will not hit attention during the self restore + //sequence. Instead, execution will hit a blr and control should return to thread launcher + //region. - memset( i_pChipHomer->cpmrRegion.selfRestoreRegion.coreScom, - 0x00, CORE_SCOM_RES_SIZE ); + memcpy( (uint32_t*)&i_pChipHomer->cpmrRegion.selfRestoreRegion.coreSelfRestore[wordCnt], + &l_fillPattern, + sizeof( uint32_t )); + wordCnt += 4; } - while(0); - return retCode; + updateCpmrHeaderSR( i_pChipHomer, i_fusedState ); + + memset( i_pChipHomer->cpmrRegion.selfRestoreRegion.coreScom, + 0x00, CORE_SCOM_RESTORE_SIZE_TOTAL ); } + while(0); + + return retCode; +} //------------------------------------------------------------------------------ - /** - * @brief copies cme section from hardware image to HOMER. - * @param[in] i_pImageIn points to start of hardware image. - * @param[in] i_pChipHomer points to HOMER image. - * @param[in] i_imgType image sections to be built - * @return IMG_BUILD_SUCCESS if function succeeds, error code otherwise. - */ - uint32_t buildCmeImage( void* const i_pImageIn, Homerlayout_t* i_pChipHomer, - ImageType_t i_imgType, uint64_t i_cpmrPhyAdd ) - { - uint32_t retCode = IMG_BUILD_SUCCESS; +/** + * @brief copies cme section from hardware image to HOMER. + * @param[in] i_pImageIn points to start of hardware image. + * @param[in] i_pChipHomer points to HOMER image. + * @param[in] i_imgType image sections to be built + * @return IMG_BUILD_SUCCESS if function succeeds, error code otherwise. + */ +uint32_t buildCmeImage( void* const i_pImageIn, Homerlayout_t* i_pChipHomer, + ImageType_t i_imgType, uint64_t i_cpmrPhyAdd ) +{ + uint32_t retCode = IMG_BUILD_SUCCESS; - do - { - uint32_t rcTemp = 0; - //Let us find XIP Header for CME Image - P9XipSection ppeSection; - uint8_t* pCmeImg = NULL; + do + { + uint32_t rcTemp = 0; + //Let us find XIP Header for CME Image + P9XipSection ppeSection; + uint8_t* pCmeImg = NULL; - rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_CME, &ppeSection ); + rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_CME, &ppeSection ); - if( rcTemp ) - { - FAPI_ERR("Failed to get CME Image XIP header" ); - retCode = BUILD_FAIL_CME_IMAGE; - break; - } + if( rcTemp ) + { + FAPI_ERR("Failed to get CME Image XIP header" ); + retCode = BUILD_FAIL_CME_IMAGE; + break; + } - pCmeImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); - FAPI_DBG("ppeSection.iv_offset = 0x%08X, ppeSection.iv_size = 0x%08X", - ppeSection.iv_offset, ppeSection.iv_size); + pCmeImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); + FAPI_DBG("ppeSection.iv_offset = 0x%08X, ppeSection.iv_size = 0x%08X", + ppeSection.iv_offset, ppeSection.iv_size); - if( !i_imgType.cmeHcodeBuild ) - { - break; - } + if( !i_imgType.cmeHcodeBuild ) + { + break; + } - memset(i_pChipHomer->cpmrRegion.cmeSramRegion, 0x00, CME_REGION_SIZE); + memset(i_pChipHomer->cpmrRegion.cmeSramRegion, 0x00, CME_REGION_SIZE); - // The image in the HW Image has the Interrupt Vectors, CME Header and Debug - // Pointers already included. - rcTemp = copySectionToHomer( i_pChipHomer->cpmrRegion.cmeSramRegion, pCmeImg, - P9_XIP_SECTION_CME_HCODE, - PLAT_CME, - ppeSection ); + // The image in the HW Image has the Interrupt Vectors, CME Header and Debug + // Pointers already included. + rcTemp = copySectionToHomer( i_pChipHomer->cpmrRegion.cmeSramRegion, pCmeImg, + P9_XIP_SECTION_CME_HCODE, + PLAT_CME, + ppeSection ); - if( rcTemp ) - { - FAPI_ERR("Failed to append CME Hcode"); - retCode = BUILD_FAIL_CME_HCODE; - break; - } + if( rcTemp ) + { + FAPI_ERR("Failed to append CME Hcode"); + retCode = BUILD_FAIL_CME_HCODE; + break; + } - // Initializing CME Image header - // Names have g_ prefix as these global variables for CME Hcode - // Note: Only the *memory* addresses are updated - cmeHeader_t* pImgHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - pImgHdr->g_cme_hcode_offset = CME_SRAM_HCODE_OFFSET; - pImgHdr->g_cme_hcode_length = ppeSection.iv_size; - - //Populating common ring offset here. So, that other scan ring related field can be updated. - pImgHdr->g_cme_cpmr_PhyAddr = (i_cpmrPhyAdd | CPMR_OFFSET); - pImgHdr->g_cme_pstate_region_offset = pImgHdr->g_cme_hcode_offset + pImgHdr->g_cme_hcode_length; - pImgHdr->g_cme_pstate_region_length = 0; - pImgHdr->g_cme_common_ring_offset = pImgHdr->g_cme_pstate_region_offset + pImgHdr->g_cme_pstate_region_length; - pImgHdr->g_cme_common_ring_length = 0; - pImgHdr->g_cme_scom_offset = 0; - pImgHdr->g_cme_scom_length = CORE_SCOM_PER_CME; - pImgHdr->g_cme_core_spec_ring_offset = 0; // multiple of 32B blocks - pImgHdr->g_cme_max_spec_ring_length = 0; // multiple of 32B blocks - - //Let us handle the endianess at the end - pImgHdr->g_cme_pstate_region_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_pstate_region_offset); - pImgHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_common_ring_offset); - pImgHdr->g_cme_hcode_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_hcode_offset); - pImgHdr->g_cme_hcode_length = SWIZZLE_4_BYTE(pImgHdr->g_cme_hcode_length); - pImgHdr->g_cme_scom_length = SWIZZLE_4_BYTE(pImgHdr->g_cme_scom_length); - pImgHdr->g_cme_cpmr_PhyAddr = SWIZZLE_8_BYTE(pImgHdr->g_cme_cpmr_PhyAddr); - } - while(0); - - return retCode; + // Initializing CME Image header + // Names have g_ prefix as these global variables for CME Hcode + // Note: Only the *memory* addresses are updated + cmeHeader_t* pImgHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + pImgHdr->g_cme_hcode_offset = CME_SRAM_HCODE_OFFSET; + pImgHdr->g_cme_hcode_length = ppeSection.iv_size; + + //Populating common ring offset here. So, that other scan ring related field can be updated. + pImgHdr->g_cme_cpmr_PhyAddr = (i_cpmrPhyAdd | CPMR_HOMER_OFFSET); + pImgHdr->g_cme_pstate_region_offset = pImgHdr->g_cme_hcode_offset + pImgHdr->g_cme_hcode_length; + pImgHdr->g_cme_pstate_region_length = 0; + pImgHdr->g_cme_common_ring_offset = pImgHdr->g_cme_pstate_region_offset + pImgHdr->g_cme_pstate_region_length; + pImgHdr->g_cme_common_ring_length = 0; + pImgHdr->g_cme_scom_offset = 0; + pImgHdr->g_cme_scom_length = CORE_SCOM_RESTORE_SIZE_PER_CME; + pImgHdr->g_cme_core_spec_ring_offset = 0; // multiple of 32B blocks + pImgHdr->g_cme_max_spec_ring_length = 0; // multiple of 32B blocks + + //Let us handle the endianess at the end + pImgHdr->g_cme_pstate_region_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_pstate_region_offset); + pImgHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_common_ring_offset); + pImgHdr->g_cme_hcode_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_hcode_offset); + pImgHdr->g_cme_hcode_length = SWIZZLE_4_BYTE(pImgHdr->g_cme_hcode_length); + pImgHdr->g_cme_scom_length = SWIZZLE_4_BYTE(pImgHdr->g_cme_scom_length); + pImgHdr->g_cme_cpmr_PhyAddr = SWIZZLE_8_BYTE(pImgHdr->g_cme_cpmr_PhyAddr); } + while(0); + + return retCode; +} //------------------------------------------------------------------------------ - /** - * @brief copies PGPE section from hardware image to HOMER. - * @param[in] i_pImageIn points to start of hardware image. - * @param[in] i_pChipHomer points to HOMER image in main memory. - * @param[io] io_ppmrHdr an instance of PpmrHeader_t - * @param[in] i_imgType image sections to be built - * @return IMG_BUILD_SUCCESS if function succeeds, error code otherwise. - */ - uint32_t buildPgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChipHomer, - PpmrHeader_t& io_ppmrHdr, ImageType_t i_imgType ) +/** + * @brief copies PGPE section from hardware image to HOMER. + * @param[in] i_pImageIn points to start of hardware image. + * @param[in] i_pChipHomer points to HOMER image in main memory. + * @param[io] io_ppmrHdr an instance of PpmrHeader_t + * @param[in] i_imgType image sections to be built + * @return IMG_BUILD_SUCCESS if function succeeds, error code otherwise. + */ +uint32_t buildPgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChipHomer, + PpmrHeader_t& io_ppmrHdr, ImageType_t i_imgType ) +{ + uint32_t retCode = IMG_BUILD_SUCCESS; + FAPI_INF("> PGPE Img build") + + do { - uint32_t retCode = IMG_BUILD_SUCCESS; - FAPI_INF("> PGPE Img build") + uint32_t rcTemp = 0; + //Let us find XIP Header for SGPE + P9XipSection ppeSection; + uint8_t* pPgpeImg = NULL; + + //Init PGPE region with zero + memset( i_pChipHomer->ppmrRegion.ppmrHeader, 0x00, ONE_MB ); - do + PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) i_pChipHomer->ppmrRegion.ppmrHeader; + + if(!i_imgType.pgpeImageBuild ) { - uint32_t rcTemp = 0; - //Let us find XIP Header for SGPE - P9XipSection ppeSection; - uint8_t* pPgpeImg = NULL; + break; + } - //Init PGPE region with zero - memset( i_pChipHomer->ppmrRegion.ppmrHeader, 0x00, ONE_MB ); + rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_PGPE, &ppeSection ); - PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) i_pChipHomer->ppmrRegion.ppmrHeader; + if( rcTemp ) + { + FAPI_ERR("Failed to get PGPE XIP Image Header" ); + retCode = BUILD_FAIL_PGPE_IMAGE; + break; + } - if(!i_imgType.pgpeImageBuild ) - { - break; - } + pPgpeImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); + FAPI_DBG("HW image PGPE Offset = 0x%08X", ppeSection.iv_offset); - rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_PGPE, &ppeSection ); + FAPI_INF("PPMR Header"); + rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.ppmrHeader, + pPgpeImg, + P9_XIP_SECTION_PGPE_PPMR, + PLAT_PGPE, + ppeSection ); - if( rcTemp ) - { - FAPI_ERR("Failed to get PGPE XIP Image Header" ); - retCode = BUILD_FAIL_PGPE_IMAGE; - break; - } + if( rcTemp ) + { + FAPI_ERR("Failed to copy PPMR Header"); + retCode = BUILD_FAIL_PGPE_PPMR; + break; + } - pPgpeImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); - FAPI_DBG("HW image PGPE Offset = 0x%08X", ppeSection.iv_offset); + memcpy( &io_ppmrHdr, pPpmrHdr, sizeof(PpmrHeader_t)); - FAPI_INF("PPMR Header"); - rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.ppmrHeader, - pPgpeImg, - P9_XIP_SECTION_PGPE_PPMR, - PLAT_PGPE, - ppeSection ); + rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.l1BootLoader, + pPgpeImg, + P9_XIP_SECTION_PGPE_LVL1_BL, + PLAT_PGPE, + ppeSection ); - if( rcTemp ) - { - FAPI_ERR("Failed to copy PPMR Header"); - retCode = BUILD_FAIL_PGPE_PPMR; - break; - } + if( rcTemp ) + { + FAPI_ERR("Failed to copy PGPE Level1 bootloader"); + retCode = BUILD_FAIL_PGPE_BL1; + break; + } - memcpy( &io_ppmrHdr, pPpmrHdr, sizeof(PpmrHeader_t)); + io_ppmrHdr.g_ppmr_bc_offset = PPMR_HEADER_SIZE; - rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.l1BootLoader, - pPgpeImg, - P9_XIP_SECTION_PGPE_LVL1_BL, - PLAT_PGPE, - ppeSection ); - if( rcTemp ) - { - FAPI_ERR("Failed to copy PGPE Level1 bootloader"); - retCode = BUILD_FAIL_PGPE_BL1; - break; - } + rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.l2BootLoader, + pPgpeImg, + P9_XIP_SECTION_PGPE_LVL2_BL, + PLAT_PGPE, + ppeSection ); - io_ppmrHdr.g_ppmr_bc_offset = PPMR_HEADER_LEN; + if( rcTemp ) + { + FAPI_ERR("Failed to copy PGPE Level2 bootloader"); + retCode = BUILD_FAIL_PGPE_BL2; + break; + } + io_ppmrHdr.g_ppmr_bl_offset = io_ppmrHdr.g_ppmr_bc_offset + PGPE_BOOT_COPIER_SIZE; + io_ppmrHdr.g_ppmr_bl_length = ppeSection.iv_size; - rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.l2BootLoader, - pPgpeImg, - P9_XIP_SECTION_PGPE_LVL2_BL, - PLAT_PGPE, - ppeSection ); + rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.pgpeSramImage, + pPgpeImg, + P9_XIP_SECTION_PGPE_HCODE, + PLAT_PGPE, + ppeSection ); - if( rcTemp ) - { - FAPI_ERR("Failed to copy PGPE Level2 bootloader"); - retCode = BUILD_FAIL_PGPE_BL2; - break; - } + if( rcTemp ) + { + FAPI_ERR("Failed to copy PGPE hcode"); + retCode = BUILD_FAIL_PGPE_HCODE; + break; + } - io_ppmrHdr.g_ppmr_bl_offset = io_ppmrHdr.g_ppmr_bc_offset + PGPE_LVL_1_BOOT_LOAD_SIZE; - io_ppmrHdr.g_ppmr_bl_length = ppeSection.iv_size; + io_ppmrHdr.g_ppmr_hcode_offset = io_ppmrHdr.g_ppmr_bl_offset + PGPE_BOOT_LOADER_SIZE; + io_ppmrHdr.g_ppmr_hcode_length = ppeSection.iv_size; - rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.pgpeSramImage, - pPgpeImg, - P9_XIP_SECTION_PGPE_HCODE, - PLAT_PGPE, - ppeSection ); + //Finally let us take care of endianess + io_ppmrHdr.g_ppmr_bc_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bc_offset); + io_ppmrHdr.g_ppmr_bl_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bl_offset); + io_ppmrHdr.g_ppmr_bl_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bl_length); + io_ppmrHdr.g_ppmr_hcode_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_offset); + io_ppmrHdr.g_ppmr_hcode_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); + } + while(0); - if( rcTemp ) - { - FAPI_ERR("Failed to copy PGPE hcode"); - retCode = BUILD_FAIL_PGPE_HCODE; - break; - } + FAPI_INF("< PGPE Img build") + return retCode; +} - io_ppmrHdr.g_ppmr_hcode_offset = io_ppmrHdr.g_ppmr_bl_offset + PGPE_LVL_2_BOOT_LOAD_SIZE; - io_ppmrHdr.g_ppmr_hcode_length = ppeSection.iv_size; +//------------------------------------------------------------------------------ + +/** + * @brief get a blob of platform rings in a temp buffer. + * @param i_hwImage points to hardware image. + * @param i_procTgt processor target + * @param i_ringData temp data struct + */ +uint32_t getPpeScanRings( void* const i_pHwImage, + PlatId i_ppeType, + CONST_FAPI2_PROC& i_procTgt, + RingBufData& i_ringData, + ImageType_t i_imgType ) +{ + FAPI_INF(">getPpeScanRings"); + uint32_t retCode = IMG_BUILD_SUCCESS; + uint32_t hwImageSize = 0; - //Finally let us take care of endianess - io_ppmrHdr.g_ppmr_bc_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bc_offset); - io_ppmrHdr.g_ppmr_bl_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bl_offset); - io_ppmrHdr.g_ppmr_bl_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bl_length); - io_ppmrHdr.g_ppmr_hcode_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_offset); - io_ppmrHdr.g_ppmr_hcode_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); + do + { + if(( !i_imgType.cmeCommonRingBuild && !i_imgType.cmeCoreSpecificRingBuild ) || + ( i_imgType.sgpeCommonRingBuild && !i_imgType.sgpeCacheSpecificRingBuild )) + { + break; } - while(0); - FAPI_INF("< PGPE Img build") - return retCode; + p9_xip_image_size( i_pHwImage, &hwImageSize ); + + P9XipSection ppeSection; + retCode = p9_xip_get_section( i_pHwImage, P9_XIP_SECTION_HW_RINGS, &ppeSection ); + + if( retCode ) + { + FAPI_ERR("Failed to access scan rings for %s", (i_ppeType == PLAT_CME ) ? "CME" : "SGPE" ); + retCode = BUILD_FAIL_RING_EXTRACTN; + break; + } + + if( 0 == ppeSection.iv_size ) + { + retCode = BUILD_FAIL_RING_EXTRACTN; + FAPI_ERR("Empty .rings section not allowed: <.rings>.iv_size = %d Plat %s", + ppeSection.iv_size, (i_ppeType == PLAT_CME ) ? "CME" : "SGPE" ); + break; + } + + FAPI_DBG("------------------ Input Buffer Specs --------------------"); + FAPI_DBG("Ring section (buf,size)=(0x%016llX,0x%08X)", + (uintptr_t)(i_ringData.iv_pRingBuffer), i_ringData.iv_ringBufSize); + FAPI_DBG("Work buf1 (buf,size)=(0x%016llX,0x%08X)", + (uintptr_t)(i_ringData.iv_pWorkBuf1), i_ringData.iv_sizeWorkBuf1); + FAPI_DBG("Work buf2 (buf,size)=(0x%016llX,0x%08X)", + (uintptr_t)(i_ringData.iv_pWorkBuf2), i_ringData.iv_sizeWorkBuf2); + FAPI_DBG("---------------=== Buffer Specs Ends --------------------"); + + uint32_t l_bootMask = ENABLE_ALL_CORE; + fapi2::ReturnCode l_fapiRc = fapi2::FAPI2_RC_SUCCESS; + + FAPI_EXEC_HWP( l_fapiRc, + p9_xip_customize, + i_procTgt, + i_pHwImage, + hwImageSize, + i_ringData.iv_pRingBuffer, + i_ringData.iv_ringBufSize, + (i_ppeType == PLAT_CME) ? SYSPHASE_RT_CME : SYSPHASE_RT_SGPE, + MODEBUILD_IPL, + i_ringData.iv_pWorkBuf1, + i_ringData.iv_sizeWorkBuf1, + i_ringData.iv_pWorkBuf2, + i_ringData.iv_sizeWorkBuf2, + l_bootMask ); + + if( l_fapiRc ) + { + retCode = BUILD_FAIL_RING_EXTRACTN; + FAPI_ERR("p9_xip_customize failed to extract rings for %s", + (i_ppeType == PLAT_CME ) ? "CME" : "SGPE" ); + break; + } } + while(0); + + FAPI_INF("<getPpeScanRings " ); + return retCode; +} //------------------------------------------------------------------------------ - /** - * @brief get a blob of platform rings in a temp buffer. - * @param i_hwImage points to hardware image. - * @param i_procTgt processor target - * @param i_ringData temp data struct - */ - uint32_t getPpeScanRings( void* const i_pHwImage, - PlatId i_ppeType, - CONST_FAPI2_PROC& i_procTgt, - RingBufData& i_ringData, - ImageType_t i_imgType ) - { - FAPI_INF(">getPpeScanRings"); - uint32_t retCode = IMG_BUILD_SUCCESS; - uint32_t hwImageSize = 0; +uint32_t layoutSgpeScanOverride( Homerlayout_t* i_pHomer, + void* i_pOverride, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + QpmrHeaderLayout_t& i_qpmrHdr, + ImageType_t i_imgType ) +{ + FAPI_INF("> layoutSgpeScanOverride "); + uint32_t rc = IMG_BUILD_SUCCESS; + sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)&i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; + RingBucket sgpeOvrdRings( PLAT_SGPE, + (uint8_t*)&i_pHomer->qpmrRegion, + i_debugMode ); - do + do + { + if( !i_imgType.sgpeCommonRingBuild ) { - if(( !i_imgType.cmeCommonRingBuild && !i_imgType.cmeCoreSpecificRingBuild ) || - ( i_imgType.sgpeCommonRingBuild && !i_imgType.sgpeCacheSpecificRingBuild )) - { - break; - } + break; + } - p9_xip_image_size( i_pHwImage, &hwImageSize ); + if( !i_pOverride ) + { + break; + } - P9XipSection ppeSection; - retCode = p9_xip_get_section( i_pHwImage, P9_XIP_SECTION_HW_RINGS, &ppeSection ); + uint32_t commonRingLength = i_qpmrHdr.quadCommonRingLength; - if( retCode ) - { - FAPI_ERR("Failed to access scan rings for %s", (i_ppeType == PLAT_CME ) ? "CME" : "SGPE" ); - retCode = BUILD_FAIL_RING_EXTRACTN; - break; - } + //Start override ring from the actual end of base common rings. Remeber overrides reside within area + //earmarked for common rings + uint8_t* pOverrideStart = + &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[commonRingLength + SWIZZLE_4_BYTE(i_qpmrHdr.sgpeImgLength)]; + uint16_t* pScanRingIndex = (uint16_t*)pOverrideStart; - if( 0 == ppeSection.iv_size ) - { - retCode = BUILD_FAIL_RING_EXTRACTN; - FAPI_ERR("Empty .rings section not allowed: <.rings>.iv_size = %d Plat %s", - ppeSection.iv_size, (i_ppeType == PLAT_CME ) ? "CME" : "SGPE" ); - break; - } + //get core common rings + uint8_t* pOvrdRingPayload = pOverrideStart + QUAD_COMMON_RING_INDEX_SIZE; + uint32_t tempRingLength = 0; + uint32_t tempBufSize = 0; + bool overrideNotFound = true; + uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; + FAPI_DBG("TOR Version : 0x%02x", P9_TOR::tor_version() ); - FAPI_DBG("------------------ Input Buffer Specs --------------------"); - FAPI_DBG("Ring section (buf,size)=(0x%016llX,0x%08X)", - (uintptr_t)(i_ringData.iv_pRingBuffer), i_ringData.iv_ringBufSize); - FAPI_DBG("Work buf1 (buf,size)=(0x%016llX,0x%08X)", - (uintptr_t)(i_ringData.iv_pWorkBuf1), i_ringData.iv_sizeWorkBuf1); - FAPI_DBG("Work buf2 (buf,size)=(0x%016llX,0x%08X)", - (uintptr_t)(i_ringData.iv_pWorkBuf2), i_ringData.iv_sizeWorkBuf2); - FAPI_DBG("---------------=== Buffer Specs Ends --------------------"); + for( uint32_t ringIndex = 0; ringIndex < EQ::g_eqData.iv_num_common_rings; + ringIndex++ ) + { + tempBufSize = i_ringData.iv_sizeWorkBuf1; - uint32_t l_bootMask = ENABLE_ALL_CORE; - fapi2::ReturnCode l_fapiRc = fapi2::FAPI2_RC_SUCCESS; + FAPI_DBG("Calling P9_TOR::tor_get_single_ring ring 0x%08X", ringIndex); + rc = tor_get_single_ring( i_pOverride, + P9_XIP_MAGIC_SEEPROM, + i_chipState.getChipLevel(), + sgpeOvrdRings.getCommonRingId( ringIndex ), + P9_TOR::SBE, + OVERRIDE, + CACHE0_CHIPLET_ID, + &i_ringData.iv_pWorkBuf2, + tempBufSize, + 0 ); - FAPI_EXEC_HWP( l_fapiRc, - p9_xip_customize, - i_procTgt, - i_pHwImage, - hwImageSize, - i_ringData.iv_pRingBuffer, - i_ringData.iv_ringBufSize, - (i_ppeType == PLAT_CME) ? SYSPHASE_RT_CME : SYSPHASE_RT_SGPE, - MODEBUILD_IPL, - i_ringData.iv_pWorkBuf1, - i_ringData.iv_sizeWorkBuf1, - i_ringData.iv_pWorkBuf2, - i_ringData.iv_sizeWorkBuf2, - l_bootMask ); - - if( l_fapiRc ) + if( (i_ringData.iv_sizeWorkBuf2 == tempBufSize) || (0 == tempBufSize ) || + ( 0 != rc ) ) { - retCode = BUILD_FAIL_RING_EXTRACTN; - FAPI_ERR("p9_xip_customize failed to extract rings for %s", - (i_ppeType == PLAT_CME ) ? "CME" : "SGPE" ); - break; + tempBufSize = 0; + continue; } - } - while(0); - FAPI_INF("<getPpeScanRings " ); - return retCode; - } + overrideNotFound = false; + ALIGN_DWORD(tempRingLength, tempBufSize) + ALIGN_RING_LOC( pOverrideStart, pOvrdRingPayload ); -//------------------------------------------------------------------------------ - uint32_t layoutSgpeScanOverride( Homerlayout_t* i_pHomer, - void* i_pOverride, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - QpmrHeaderLayout_t& i_qpmrHdr, - ImageType_t i_imgType ) - { - FAPI_INF("> layoutSgpeScanOverride "); - uint32_t rc = IMG_BUILD_SUCCESS; - sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)&i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT]; - RingBucket sgpeOvrdRings( PLAT_SGPE, - (uint8_t*)&i_pHomer->qpmrRegion, - i_debugMode ); + memcpy( pOvrdRingPayload, i_ringData.iv_pWorkBuf2, tempBufSize); + *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pOvrdRingPayload - pOverrideStart) + ringStartToHdrOffset); - do - { - if( !i_imgType.sgpeCommonRingBuild ) - { - break; - } + sgpeOvrdRings.setRingOffset(pOvrdRingPayload, sgpeOvrdRings.getCommonRingId( ringIndex )); + sgpeOvrdRings.setRingSize( sgpeOvrdRings.getCommonRingId( ringIndex ), tempBufSize ); + sgpeOvrdRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, sgpeOvrdRings.getCommonRingId( ringIndex ) ); - if( !i_pOverride ) - { - break; - } + pOvrdRingPayload = pOvrdRingPayload + tempBufSize; + } - uint32_t commonRingLength = i_qpmrHdr.quadCommonRingLength; + if( overrideNotFound ) + { + FAPI_INF("Overrides not found for SGPE"); + rc = BUILD_FAIL_OVERRIDE; // Not considered an error + break; + } - //Start override ring from the actual end of base common rings. Remeber overrides reside within area - //earmarked for common rings - uint8_t* pOverrideStart = - &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[commonRingLength + SWIZZLE_4_BYTE(i_qpmrHdr.sgpeImgLength)]; - uint16_t* pScanRingIndex = (uint16_t*)pOverrideStart; + tempRingLength = (pOvrdRingPayload - pOverrideStart ); + pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset = + SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset) + commonRingLength; + i_qpmrHdr.quadCommonRingLength = commonRingLength + tempRingLength; + i_qpmrHdr.quadCommonOvrdLength = tempRingLength; + i_qpmrHdr.quadCommonOvrdOffset = i_qpmrHdr.quadCommonRingOffset + commonRingLength; + pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset); - //get core common rings - uint8_t* pOvrdRingPayload = pOverrideStart + QUAD_COMMON_RING_INDEX_SIZE; - uint32_t tempRingLength = 0; - uint32_t tempBufSize = 0; - bool overrideNotFound = true; - uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; - FAPI_DBG("TOR Version : 0x%02x", P9_TOR::tor_version() ); + } + while(0); - for( uint32_t ringIndex = 0; ringIndex < EQ::g_eqData.iv_num_common_rings; - ringIndex++ ) - { - tempBufSize = i_ringData.iv_sizeWorkBuf1; + FAPI_DBG("--------------------SGPE Override Rings---------------=" ); + FAPI_DBG("--------------------SGPE Header --------------------===="); + FAPI_DBG("Override Ring Offset 0x%08X", SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset)); - FAPI_DBG("Calling P9_TOR::tor_get_single_ring ring 0x%08X", ringIndex); - rc = tor_get_single_ring( i_pOverride, - P9_XIP_MAGIC_SEEPROM, - i_chipState.getChipLevel(), - sgpeOvrdRings.getCommonRingId( ringIndex ), - P9_TOR::SBE, - OVERRIDE, - CACH0_CHIPLET_ID, - &i_ringData.iv_pWorkBuf2, - tempBufSize, - 0 ); + sgpeOvrdRings.dumpOverrideRings(); - if( (i_ringData.iv_sizeWorkBuf2 == tempBufSize) || (0 == tempBufSize ) || - ( 0 != rc ) ) - { - tempBufSize = 0; - continue; - } + FAPI_INF("< layoutSgpeScanOverride") + return rc; +} - overrideNotFound = false; - ALIGN_DWORD(tempRingLength, tempBufSize) - ALIGN_RING_LOC( pOverrideStart, pOvrdRingPayload ); +/** + * @brief update fields of PGPE image header region with parameter block info. + * @param i_pHomer points to start of chip's HOMER. + */ - memcpy( pOvrdRingPayload, i_ringData.iv_pWorkBuf2, tempBufSize); - *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pOvrdRingPayload - pOverrideStart) + ringStartToHdrOffset); +void updatePgpeHeader( void* const i_pHomer ) +{ + FAPI_DBG("> updatePgpeHeader"); + Homerlayout_t* pHomerLayout = (Homerlayout_t*)i_pHomer; + PgpeHeader_t* pPgpeHdr = (PgpeHeader_t*)&pHomerLayout->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR_SIZE]; + PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) pHomerLayout->ppmrRegion.ppmrHeader; + + //Updating PGPE Image Header + pPgpeHdr->g_pgpe_ivpr_addr = OCC_SRAM_PGPE_BASE_ADDR; + + //Global P-State Parameter Block SRAM address + pPgpeHdr->g_pgpe_gppb_sram_addr = 0; // set by PGPE Hcode + + //PGPE Hcode length + pPgpeHdr->g_pgpe_hcode_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_length); + + //Global P-State Parameter Block HOMER address + pPgpeHdr->g_pgpe_gppb_mem_offset = (HOMER_PPMR_BASE_ADDR | + (SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_offset))); + + //Global P-State Parameter Block length + pPgpeHdr->g_pgpe_gppb_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_length); + + //P-State Parameter Block HOMER offset + pPgpeHdr->g_pgpe_gen_pstables_mem_offset = (HOMER_PPMR_BASE_ADDR | + (SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_offset))); + + //P-State Table length + pPgpeHdr->g_pgpe_gen_pstables_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_length); + + //OCC P-State Table SRAM address + pPgpeHdr->g_pgpe_occ_pstables_sram_addr = 0; + + //OCC P-State Table Length + pPgpeHdr->g_pgpe_occ_pstables_len = 0; + + //PGPE Beacon SRAM address + pPgpeHdr->g_pgpe_beacon_addr = 0; + pPgpeHdr->g_quad_status_addr = 0; + pPgpeHdr->g_wof_table_addr = 0; + pPgpeHdr->g_wof_table_length = 0; + + //Finally handling the endianess + pPgpeHdr->g_pgpe_magic_number = SWIZZLE_8_BYTE(PGPE_MAGIC_NUMBER); + pPgpeHdr->g_pgpe_gppb_sram_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_sram_addr); + pPgpeHdr->g_pgpe_hcode_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_hcode_length); + pPgpeHdr->g_pgpe_gppb_mem_offset = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_mem_offset); + pPgpeHdr->g_pgpe_gppb_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_length); + pPgpeHdr->g_pgpe_gen_pstables_mem_offset = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_mem_offset); + pPgpeHdr->g_pgpe_gen_pstables_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_length); + pPgpeHdr->g_pgpe_occ_pstables_sram_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_sram_addr); + pPgpeHdr->g_pgpe_occ_pstables_len = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_len); + pPgpeHdr->g_pgpe_beacon_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_beacon_addr); + pPgpeHdr->g_quad_status_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_quad_status_addr); + pPgpeHdr->g_wof_table_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_addr); + pPgpeHdr->g_wof_table_length = SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_length); + + FAPI_DBG("================================PGPE Image Header==========================================") + char magicWord[16] = {0}; + uint64_t temp = pPgpeHdr->g_pgpe_magic_number; + memcpy(magicWord, &temp, sizeof(uint64_t)); + FAPI_DBG("PGPE Magic Word : %s", magicWord); + FAPI_DBG("Hcode Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_length)); + FAPI_DBG("GPPB SRAM : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_sram_addr)); + FAPI_DBG("GPPB Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_mem_offset)); + FAPI_DBG("GPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_length)); + FAPI_DBG("PS Table Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_mem_offset)); + FAPI_DBG("PS Table Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_length)); + FAPI_DBG("OCC PST SRAM : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_sram_addr)); + FAPI_DBG("OCC PST Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_len)); + FAPI_DBG("Beacon Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_beacon_addr)); + FAPI_DBG("Quad Status : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_quad_status_addr)); + FAPI_DBG("WOF Addr : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_addr)); + FAPI_DBG("WOF Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_length)); + FAPI_DBG("==============================PGPE Image Header End========================================") + + FAPI_DBG("< updatePgpeHeader"); +} - sgpeOvrdRings.setRingOffset(pOvrdRingPayload, sgpeOvrdRings.getCommonRingId( ringIndex )); - sgpeOvrdRings.setRingSize( sgpeOvrdRings.getCommonRingId( ringIndex ), tempBufSize ); - sgpeOvrdRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, sgpeOvrdRings.getCommonRingId( ringIndex ) ); +//--------------------------------------------------------------------------- - pOvrdRingPayload = pOvrdRingPayload + tempBufSize; - } +void updatePpmrHeader( void* const i_pHomer, PpmrHeader_t& io_ppmrHdr ) +{ + FAPI_DBG("> updatePpmrHeader"); + Homerlayout_t* pHomerLayout = (Homerlayout_t*)i_pHomer; + PpmrHeader_t* pPpmrHdr = (PpmrHeader_t*) &pHomerLayout->ppmrRegion.ppmrHeader; + memcpy( pPpmrHdr, &io_ppmrHdr, sizeof(PpmrHeader_t) ); + + FAPI_DBG("=========================== PPMR Header ====================================" ); + char magicWord[16] = {0}; + uint64_t temp = io_ppmrHdr.g_ppmr_magic_number; + memcpy(magicWord, &temp, sizeof(uint64_t)); + FAPI_DBG("Magic Word : %s", magicWord); + FAPI_DBG("BC Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bc_offset)); + FAPI_DBG("BL Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bl_offset)); + FAPI_DBG("BL Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bl_length)); + FAPI_DBG("Hcode Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_offset)); + FAPI_DBG("Hcode Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_length)); + FAPI_DBG("GPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_offset)); + FAPI_DBG("GPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_length)); + FAPI_DBG("LPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_lppb_offset)); + FAPI_DBG("LPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_lppb_length)); + FAPI_DBG("OPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_oppb_offset)); + FAPI_DBG("OPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_oppb_length)); + FAPI_DBG("PS Table Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_offset)); + FAPI_DBG("PS Table Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_length)); + FAPI_DBG("PSGPE SRAM Size : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pgpe_sram_img_size)); + FAPI_DBG("=========================== PPMR Header ends ==================================" ); + + updatePgpeHeader( i_pHomer ); + + FAPI_DBG("< updatePpmrHeader"); +} - if( overrideNotFound ) - { - FAPI_INF("Overrides not found for SGPE"); - rc = BUILD_FAIL_OVERRIDE; // Not considered an error - break; - } +//--------------------------------------------------------------------------- - tempRingLength = (pOvrdRingPayload - pOverrideStart ); - pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset = - SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset) + commonRingLength; - i_qpmrHdr.quadCommonRingLength = commonRingLength + tempRingLength; - i_qpmrHdr.quadCommonOvrdLength = tempRingLength; - i_qpmrHdr.quadCommonOvrdOffset = i_qpmrHdr.quadCommonRingOffset + commonRingLength; - pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset); +/** + * @brief updates the PState parameter block info in CPMR and PPMR region. + * @param i_pHomer points to start of of chip's HOMER. + * @param i_procTgt fapi2 target associated with P9 chip. + * @param i_imgType image type to be built. + * return fapi2::Returncode + */ +fapi2::ReturnCode buildParameterBlock( void* const i_pHomer, CONST_FAPI2_PROC& i_procTgt, + PpmrHeader_t& io_ppmrHdr, + ImageType_t i_imgType ) +{ + FAPI_INF("buildParameterBlock entered"); + do + { + if( !i_imgType.pgpePstateParmBlockBuild ) + { + break; } - while(0); - FAPI_DBG("--------------------SGPE Override Rings---------------=" ); - FAPI_DBG("--------------------SGPE Header --------------------===="); - FAPI_DBG("Override Ring Offset 0x%08X", SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset)); + fapi2::ReturnCode retCode; + Homerlayout_t* pHomerLayout = (Homerlayout_t*)i_pHomer; + PPMRLayout_t* pPpmr = (PPMRLayout_t*) &pHomerLayout->ppmrRegion; + cmeHeader_t* pCmeHdr = (cmeHeader_t*) &pHomerLayout->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - sgpeOvrdRings.dumpOverrideRings(); + uint32_t ppmrRunningOffset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_offset) + + SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); - FAPI_INF("< layoutSgpeScanOverride") - return rc; - } + FAPI_DBG("Hcode ppmrRunningOffset 0x%08x", ppmrRunningOffset ); - /** - * @brief update fields of PGPE image header region with parameter block info. - * @param i_pHomer points to start of chip's HOMER. - */ + uint32_t pgpeRunningOffset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); + FAPI_DBG(" PGPE Hcode End 0x%08x", pgpeRunningOffset ); - void updatePgpeHeader( void* const i_pHomer ) - { - FAPI_DBG("> updatePgpeHeader"); - Homerlayout_t* pHomerLayout = (Homerlayout_t*)i_pHomer; - PgpeHeader_t* pPgpeHdr = (PgpeHeader_t*)&pHomerLayout->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR]; - PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) pHomerLayout->ppmrRegion.ppmrHeader; - //Updating PGPE Image Header - //Global P-State Parameter Block SRAM address - pPgpeHdr->g_pgpe_gppb_sram_addr = 0; // set by PGPE Hcode - - //PGPE Hcode length - pPgpeHdr->g_pgpe_hcode_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_length); - - //Global P-State Parameter Block HOMER address - pPgpeHdr->g_pgpe_gppb_mem_offset = (OCI_PBA_ADDR_BASE | - (SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_offset) + - PPMR_OFFSET )); - //Global P-State Parameter Block length - pPgpeHdr->g_pgpe_gppb_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_length); - - //P-State Parameter Block HOMER offset - pPgpeHdr->g_pgpe_gen_pstables_mem_offset = (OCI_PBA_ADDR_BASE | - (SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_offset) + - PPMR_OFFSET )); - - //P-State Table length - pPgpeHdr->g_pgpe_gen_pstables_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_length); - - //OCC P-State Table SRAM address - pPgpeHdr->g_pgpe_occ_pstables_sram_addr = 0; - - //OCC P-State Table Length - pPgpeHdr->g_pgpe_occ_pstables_len = 0; - - //PGPE Beacon SRAM address - pPgpeHdr->g_pgpe_beacon_addr = 0; - pPgpeHdr->g_quad_status_addr = 0; - pPgpeHdr->g_wof_table_addr = 0; - pPgpeHdr->g_wof_table_length = 0; - - //Finally handling the endianess - pPgpeHdr->g_pgpe_magic_number = SWIZZLE_8_BYTE(PGPE_MAGIC_NUMBER); - pPgpeHdr->g_pgpe_gppb_sram_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_sram_addr); - pPgpeHdr->g_pgpe_hcode_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_hcode_length); - pPgpeHdr->g_pgpe_gppb_mem_offset = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_mem_offset); - pPgpeHdr->g_pgpe_gppb_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_length); - pPgpeHdr->g_pgpe_gen_pstables_mem_offset = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_mem_offset); - pPgpeHdr->g_pgpe_gen_pstables_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_length); - pPgpeHdr->g_pgpe_occ_pstables_sram_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_sram_addr); - pPgpeHdr->g_pgpe_occ_pstables_len = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_len); - pPgpeHdr->g_pgpe_beacon_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_beacon_addr); - pPgpeHdr->g_quad_status_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_quad_status_addr); - pPgpeHdr->g_wof_table_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_addr); - pPgpeHdr->g_wof_table_length = SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_length); - - FAPI_DBG("================================PGPE Image Header==========================================") - char magicWord[16] = {0}; - uint64_t temp = pPgpeHdr->g_pgpe_magic_number; - memcpy(magicWord, &temp, sizeof(uint64_t)); - FAPI_DBG("PGPE Magic Word : %s", magicWord); - FAPI_DBG("Hcode Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_length)); - FAPI_DBG("GPPB SRAM : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_sram_addr)); - FAPI_DBG("GPPB Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_mem_offset)); - FAPI_DBG("GPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_length)); - FAPI_DBG("PS Table Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_mem_offset)); - FAPI_DBG("PS Table Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_length)); - FAPI_DBG("OCC PST SRAM : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_sram_addr)); - FAPI_DBG("OCC PST Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_len)); - FAPI_DBG("Beacon Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_beacon_addr)); - FAPI_DBG("Quad Status : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_quad_status_addr)); - FAPI_DBG("WOF Addr : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_addr)); - FAPI_DBG("WOF Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_length)); - FAPI_DBG("==============================PGPE Image Header End========================================") - - FAPI_DBG("< updatePgpeHeader"); - } + uint32_t sizeAligned = 0; + uint32_t sizePStateBlock = 0; + PstateSuperStructure pStateSupStruct; -//--------------------------------------------------------------------------- + //Building P-State Parameter block info by calling a HWP + FAPI_DBG("Generating P-State Parameter Block" ); + FAPI_EXEC_HWP(retCode, p9_pstate_parameter_block, i_procTgt, &pStateSupStruct); + FAPI_TRY(retCode); - void updatePpmrHeader( void* const i_pHomer, PpmrHeader_t& io_ppmrHdr ) - { - FAPI_DBG("> updatePpmrHeader"); - Homerlayout_t* pHomerLayout = (Homerlayout_t*)i_pHomer; - PpmrHeader_t* pPpmrHdr = (PpmrHeader_t*) &pHomerLayout->ppmrRegion.ppmrHeader; - memcpy( pPpmrHdr, &io_ppmrHdr, sizeof(PpmrHeader_t) ); - - FAPI_DBG("=========================== PPMR Header ====================================" ); - char magicWord[16] = {0}; - uint64_t temp = io_ppmrHdr.g_ppmr_magic_number; - memcpy(magicWord, &temp, sizeof(uint64_t)); - FAPI_DBG("Magic Word : %s", magicWord); - FAPI_DBG("BC Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bc_offset)); - FAPI_DBG("BL Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bl_offset)); - FAPI_DBG("BL Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bl_length)); - FAPI_DBG("Hcode Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_offset)); - FAPI_DBG("Hcode Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_length)); - FAPI_DBG("GPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_offset)); - FAPI_DBG("GPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_length)); - FAPI_DBG("LPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_lppb_offset)); - FAPI_DBG("LPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_lppb_length)); - FAPI_DBG("OPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_oppb_offset)); - FAPI_DBG("OPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_oppb_length)); - FAPI_DBG("PS Table Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_offset)); - FAPI_DBG("PS Table Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_length)); - FAPI_DBG("PSGPE SRAM Size : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pgpe_sram_img_size)); - FAPI_DBG("=========================== PPMR Header ends ==================================" ); - - updatePgpeHeader( i_pHomer ); - - FAPI_DBG("< updatePpmrHeader"); - } + //-------------------------- Local P-State Parameter Block ------------------------------ -//--------------------------------------------------------------------------- + uint32_t localPspbStartIndex = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length); + uint8_t* pLocalPState = &pHomerLayout->cpmrRegion.cmeSramRegion[localPspbStartIndex]; - /** - * @brief updates the PState parameter block info in CPMR and PPMR region. - * @param i_pHomer points to start of of chip's HOMER. - * @param i_procTgt fapi2 target associated with P9 chip. - * @param i_imgType image type to be built. - * return fapi2::Returncode - */ - fapi2::ReturnCode buildParameterBlock( void* const i_pHomer, CONST_FAPI2_PROC& i_procTgt, - PpmrHeader_t& io_ppmrHdr, - ImageType_t i_imgType ) - { - FAPI_INF("buildParameterBlock entered"); + sizePStateBlock = sizeof(LocalPstateParmBlock); - do - { - if( !i_imgType.pgpePstateParmBlockBuild ) - { - break; - } + FAPI_DBG("Copying Local P-State Parameter Block into CPMR" ); + memcpy( pLocalPState, &pStateSupStruct.localppb, sizePStateBlock ); + + ALIGN_DBWORD( sizeAligned, sizePStateBlock ) + uint32_t localPStateBlock = sizeAligned; + FAPI_DBG("LPSPB Actual size 0x%08x After Alignment 0x%08x", sizePStateBlock, sizeAligned ); + + pCmeHdr->g_cme_pstate_region_length = localPStateBlock; + pCmeHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset) + localPStateBlock; - fapi2::ReturnCode retCode; - Homerlayout_t* pHomerLayout = (Homerlayout_t*)i_pHomer; - PPMRLayout_t* pPpmr = (PPMRLayout_t*) &pHomerLayout->ppmrRegion; - cmeHeader_t* pCmeHdr = (cmeHeader_t*) &pHomerLayout->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + //-------------------------- Local P-State Parameter Block Ends -------------------------- - uint32_t ppmrRunningOffset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_offset) + - SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); + //-------------------------- Global P-State Parameter Block ------------------------------ - FAPI_DBG("Hcode ppmrRunningOffset 0x%08x", ppmrRunningOffset ); + FAPI_DBG("Copying Global P-State Parameter Block" ); + sizePStateBlock = sizeof(GlobalPstateParmBlock); + + // MAKE ASSERT + if (sizePStateBlock > PGPE_PSTATE_OUTPUT_TABLES_SIZE) + { + FAPI_ERR("GlobalPstateParmBlock exceeds allocation: size = %X (%d), allocation = %X (%d)", + sizePStateBlock, sizePStateBlock, + PGPE_PSTATE_OUTPUT_TABLES_SIZE, PGPE_PSTATE_OUTPUT_TABLES_SIZE); + } - uint32_t pgpeRunningOffset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); + FAPI_DBG("GPPBB pgpeRunningOffset 0x%08x", pgpeRunningOffset ); + memcpy( &pPpmr->pgpeSramImage[pgpeRunningOffset], &pStateSupStruct.globalppb, sizePStateBlock ); - FAPI_DBG(" PGPE Hcode End 0x%08x", pgpeRunningOffset ); + ALIGN_DBWORD( sizeAligned, sizePStateBlock ) + FAPI_DBG("GPSPB Actual size 0x%08x After Alignment 0x%08x", sizePStateBlock, sizeAligned ); - uint32_t sizeAligned = 0; - uint32_t sizePStateBlock = 0; - PstateSuperStructure pStateSupStruct; + //Updating PPMR header info with GPSPB offset and length + io_ppmrHdr.g_ppmr_gppb_offset = ppmrRunningOffset; + io_ppmrHdr.g_ppmr_gppb_length = sizeAligned; - //Building P-State Parameter block info by calling a HWP - FAPI_DBG("Generating P-State Parameter Block" ); - FAPI_EXEC_HWP(retCode, p9_pstate_parameter_block, i_procTgt, &pStateSupStruct); - FAPI_TRY(retCode); + ppmrRunningOffset += sizeAligned; + pgpeRunningOffset += sizeAligned; + FAPI_DBG("OPPB pgpeRunningOffset 0x%08x OPPB ppmrRunningOffset 0x%08x", + pgpeRunningOffset, ppmrRunningOffset ); - //-------------------------- Local P-State Parameter Block ------------------------------ + //------------------------------ Global P-State Parameter Block Ends ---------------------- - uint32_t localPspbStartIndex = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length); - uint8_t* pLocalPState = &pHomerLayout->cpmrRegion.cmeSramRegion[localPspbStartIndex]; + //------------------------------ OCC P-State Parameter Block ------------------------------ - sizePStateBlock = sizeof(LocalPstateParmBlock); + FAPI_INF("Copying OCC P-State Parameter Block" ); + sizePStateBlock = sizeof(OCCPstateParmBlock); + ALIGN_DBWORD( sizeAligned, sizePStateBlock ) - FAPI_DBG("Copying Local P-State Parameter Block into CPMR" ); - memcpy( pLocalPState, &pStateSupStruct.localppb, sizePStateBlock ); + FAPI_DBG("OPPB size 0x%08x (%d)", sizeAligned, sizeAligned ); + FAPI_DBG("OPSPB Actual size = 0x%08x (%d); After Alignment = 0x%08x (%d)", + sizePStateBlock, sizePStateBlock, + sizeAligned, sizeAligned ); - ALIGN_DBWORD( sizeAligned, sizePStateBlock ) - uint32_t localPStateBlock = sizeAligned; - FAPI_DBG("LPSPB Actual size 0x%08x After Alignment 0x%08x", sizePStateBlock, sizeAligned ); + // MAKE ASSERT + if (sizePStateBlock > OCC_PSTATE_PARAM_BLOCK_SIZE) + { + FAPI_ERR("OCCPstateParmBlock exceeds allocation: size = %X (%d), allocation = %X (%d)", + sizePStateBlock, sizePStateBlock, + OCC_PSTATE_PARAM_BLOCK_SIZE, OCC_PSTATE_PARAM_BLOCK_SIZE); + } - pCmeHdr->g_cme_pstate_region_length = localPStateBlock; - pCmeHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset) + localPStateBlock; + // The PPMR offset is from the begining --- which is the ppmrHeader + io_ppmrHdr.g_ppmr_oppb_offset = pPpmr->occParmBlock - pPpmr->ppmrHeader; + io_ppmrHdr.g_ppmr_oppb_length = sizeAligned; + FAPI_DBG("OPPB ppmrRunningOffset 0x%08x", io_ppmrHdr.g_ppmr_oppb_offset); - //-------------------------- Local P-State Parameter Block Ends -------------------------- + memcpy( &pPpmr->occParmBlock, &pStateSupStruct.occppb, sizePStateBlock ); - //-------------------------- Global P-State Parameter Block ------------------------------ + //-------------------------- OCC P-State Parameter Block Ends ------------------------------ - FAPI_DBG("Copying Global P-State Parameter Block" ); - sizePStateBlock = sizeof(GlobalPstateParmBlock); - // MAKE ASSERT - if (sizePStateBlock > PSTATE_OUTPUT_TABLE_SIZE) - { - FAPI_ERR("GlobalPstateParmBlock exceeds allocation: size = %X (%d), allocation = %X (%d)", - sizePStateBlock, sizePStateBlock, - PSTATE_OUTPUT_TABLE_SIZE, PSTATE_OUTPUT_TABLE_SIZE); - } - FAPI_DBG("GPPBB pgpeRunningOffset 0x%08x", pgpeRunningOffset ); - memcpy( &pPpmr->pgpeSramImage[pgpeRunningOffset], &pStateSupStruct.globalppb, sizePStateBlock ); + io_ppmrHdr.g_ppmr_lppb_offset = CPMR_HOMER_OFFSET + CME_IMAGE_CPMR_OFFSET + localPspbStartIndex; + io_ppmrHdr.g_ppmr_lppb_length = + localPStateBlock; //FIXME RTC 159737 Need to clarify it from booting perspective - ALIGN_DBWORD( sizeAligned, sizePStateBlock ) - FAPI_DBG("GPSPB Actual size 0x%08x After Alignment 0x%08x", sizePStateBlock, sizeAligned ); - //Updating PPMR header info with GPSPB offset and length - io_ppmrHdr.g_ppmr_gppb_offset = ppmrRunningOffset; - io_ppmrHdr.g_ppmr_gppb_length = sizeAligned; + //------------------------------ OCC P-State Table Allocation ------------------------------ - ppmrRunningOffset += sizeAligned; - pgpeRunningOffset += sizeAligned; - FAPI_DBG("OPPB pgpeRunningOffset 0x%08x OPPB ppmrRunningOffset 0x%08x", - pgpeRunningOffset, ppmrRunningOffset ); + // The PPMR offset is from the begining --- which is the ppmrHeader + io_ppmrHdr.g_ppmr_pstables_offset = pPpmr->pstateTable - pPpmr->ppmrHeader;; + io_ppmrHdr.g_ppmr_pstables_length = sizeof(GeneratedPstateInfo); - //------------------------------ Global P-State Parameter Block Ends ---------------------- + //------------------------------ OCC P-State Table Allocation Ends ------------------------- - //------------------------------ OCC P-State Parameter Block ------------------------------ - FAPI_INF("Copying OCC P-State Parameter Block" ); - sizePStateBlock = sizeof(OCCPstateParmBlock); - ALIGN_DBWORD( sizeAligned, sizePStateBlock ) + //------------------------------ Calculating total PGPE Image Size in SRAM ------------------------ - FAPI_DBG("OPPB size 0x%08x (%d)", sizeAligned, sizeAligned ); - FAPI_DBG("OPSPB Actual size = 0x%08x (%d); After Alignment = 0x%08x (%d)", - sizePStateBlock, sizePStateBlock, - sizeAligned, sizeAligned ); + io_ppmrHdr.g_ppmr_pgpe_sram_img_size = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length) + + io_ppmrHdr.g_ppmr_gppb_length; - // MAKE ASSERT - if (sizePStateBlock > OCC_PARAM_BLOCK_SIZE) - { - FAPI_ERR("OCCPstateParmBlock exceeds allocation: size = %X (%d), allocation = %X (%d)", - sizePStateBlock, sizePStateBlock, - OCC_PARAM_BLOCK_SIZE, OCC_PARAM_BLOCK_SIZE); - } + FAPI_DBG("OPPB pgpeRunningOffset 0x%08x io_ppmrHdr.g_ppmr_pgpe_sram_img_size 0x%08x", + pgpeRunningOffset, io_ppmrHdr.g_ppmr_pgpe_sram_img_size ); - // The PPMR offset is from the begining --- which is the ppmrHeader - io_ppmrHdr.g_ppmr_oppb_offset = pPpmr->occParmBlock - pPpmr->ppmrHeader; - io_ppmrHdr.g_ppmr_oppb_length = sizeAligned; - FAPI_DBG("OPPB ppmrRunningOffset 0x%08x", io_ppmrHdr.g_ppmr_oppb_offset); + //Finally let us handle endianess + //CME Header + pCmeHdr->g_cme_pstate_region_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length); + pCmeHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset); - memcpy( &pPpmr->occParmBlock, &pStateSupStruct.occppb, sizePStateBlock ); + //PPMR Header + io_ppmrHdr.g_ppmr_magic_number = SWIZZLE_8_BYTE(PPMR_MAGIC_NUMBER); + io_ppmrHdr.g_ppmr_gppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_gppb_offset); + io_ppmrHdr.g_ppmr_gppb_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_gppb_length); + io_ppmrHdr.g_ppmr_oppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_oppb_offset); + io_ppmrHdr.g_ppmr_oppb_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_oppb_length); + io_ppmrHdr.g_ppmr_lppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_lppb_offset); + io_ppmrHdr.g_ppmr_lppb_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_lppb_length); + io_ppmrHdr.g_ppmr_pstables_offset = SWIZZLE_4_BYTE( io_ppmrHdr.g_ppmr_pstables_offset); + io_ppmrHdr.g_ppmr_pstables_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_pstables_length); + io_ppmrHdr.g_ppmr_pgpe_sram_img_size = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_pgpe_sram_img_size); + } + while(0); - //-------------------------- OCC P-State Parameter Block Ends ------------------------------ +fapi_try_exit: + FAPI_INF("buildParameterBlock exit"); + return fapi2::current_err; +} +//--------------------------------------------------------------------------- - io_ppmrHdr.g_ppmr_lppb_offset = CPMR_OFFSET + CPMR_CME_HCODE_OFFSET + localPspbStartIndex; - io_ppmrHdr.g_ppmr_lppb_length = - localPStateBlock; //FIXME RTC 159737 Need to clarify it from booting perspective +/** + * @brief copies override flavor of scan rings + * @param i_pImageIn points to start of hardware image. + * @param i_pOverride points to override rings. + * @param o_pImageOut points to HOMER image. + * @param i_ddLevel dd level associated with P9 chip. + * @param i_pBuf1 work buffer1 + * @param i_bufSize1 work buffer1 size. + * @param i_pBuf2 work buffer2 + * @param i_bufSize2 work buffer2 size. + * @param i_imgType image type to be built. + * @param o_qpmr temp instance of QpmrHeaderLayout_t + * @param i_platId platform associated with scan ring. + * @return IMG_BUILD_SUCCESS if successful else error code. + */ +uint32_t layoutCmnRingsForCme( Homerlayout_t* i_pHomer, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + RingVariant_t i_ringVariant, + ImageType_t i_imgType, + RingBucket& io_cmeRings, + uint32_t& io_cmnRingSize ) +{ + FAPI_DBG( "> layoutCmnRingsForCme"); + uint32_t rc = IMG_BUILD_SUCCESS; + do + { - //------------------------------ OCC P-State Table Allocation ------------------------------ + uint32_t tempSize = 0; + uint32_t ringSize = 0; + uint8_t* pRingStart = &i_pHomer->cpmrRegion.cmeSramRegion[io_cmnRingSize]; + uint16_t* pScanRingIndex = (uint16_t*) pRingStart; + uint8_t* pRingPayload = pRingStart + CORE_COMMON_RING_INDEX_SIZE; + uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; - // The PPMR offset is from the begining --- which is the ppmrHeader - io_ppmrHdr.g_ppmr_pstables_offset = pPpmr->pstateTable - pPpmr->ppmrHeader;; - io_ppmrHdr.g_ppmr_pstables_length = sizeof(GeneratedPstateInfo); + if( !i_imgType.cmeCommonRingBuild ) + { + break; + } - //------------------------------ OCC P-State Table Allocation Ends ------------------------- + for( uint32_t ringIndex = 0; ringIndex < EC::g_ecData.iv_num_common_rings; + ringIndex++ ) + { + ringSize = i_ringData.iv_sizeWorkBuf1; + rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, + P9_XIP_MAGIC_CME, + i_chipState.getChipLevel(), + io_cmeRings.getCommonRingId( ringIndex ), + P9_TOR::CME, + i_ringVariant, + CORE0_CHIPLET_ID , + &i_ringData.iv_pWorkBuf1, + ringSize, + 0 ); + if( ( i_ringData.iv_sizeWorkBuf1 == ringSize ) || ( 0 == ringSize ) || + ( 0 != rc ) ) + { + FAPI_INF( "Did not find core common ring Id %d ", ringIndex ); + rc = 0; + ringSize = 0; + continue; + } - //------------------------------ Calculating total PGPE Image Size in SRAM ------------------------ + ALIGN_DWORD(tempSize, ringSize) + ALIGN_RING_LOC( pRingStart, pRingPayload ); - io_ppmrHdr.g_ppmr_pgpe_sram_img_size = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length) + - io_ppmrHdr.g_ppmr_gppb_length; + memcpy( pRingPayload, i_ringData.iv_pWorkBuf1, ringSize ); + *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pRingPayload - pRingStart) + ringStartToHdrOffset); - FAPI_DBG("OPPB pgpeRunningOffset 0x%08x io_ppmrHdr.g_ppmr_pgpe_sram_img_size 0x%08x", - pgpeRunningOffset, io_ppmrHdr.g_ppmr_pgpe_sram_img_size ); - //Finally let us handle endianess - //CME Header - pCmeHdr->g_cme_pstate_region_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length); - pCmeHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset); + io_cmeRings.setRingOffset( pRingPayload, io_cmeRings.getCommonRingId( ringIndex )); + io_cmeRings.setRingSize( io_cmeRings.getCommonRingId( ringIndex ), ringSize ); + io_cmeRings.extractRing( i_ringData.iv_pWorkBuf1, ringSize, io_cmeRings.getCommonRingId( ringIndex ) ); - //PPMR Header - io_ppmrHdr.g_ppmr_magic_number = SWIZZLE_8_BYTE(PPMR_MAGIC_NUMBER); - io_ppmrHdr.g_ppmr_gppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_gppb_offset); - io_ppmrHdr.g_ppmr_gppb_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_gppb_length); - io_ppmrHdr.g_ppmr_oppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_oppb_offset); - io_ppmrHdr.g_ppmr_oppb_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_oppb_length); - io_ppmrHdr.g_ppmr_lppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_lppb_offset); - io_ppmrHdr.g_ppmr_lppb_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_lppb_length); - io_ppmrHdr.g_ppmr_pstables_offset = SWIZZLE_4_BYTE( io_ppmrHdr.g_ppmr_pstables_offset); - io_ppmrHdr.g_ppmr_pstables_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_pstables_length); - io_ppmrHdr.g_ppmr_pgpe_sram_img_size = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_pgpe_sram_img_size); + pRingPayload = pRingPayload + ringSize; } - while(0); - fapi_try_exit: - FAPI_INF("buildParameterBlock exit"); + ringSize = (pRingPayload - pRingStart); - return fapi2::current_err; + if( ringSize > CORE_COMMON_RING_INDEX_SIZE ) + { + io_cmnRingSize += (pRingPayload - pRingStart); + ALIGN_DWORD(tempSize, io_cmnRingSize) + } } + while(0); -//--------------------------------------------------------------------------- + FAPI_DBG( "< layoutCmnRingsForCme"); - /** - * @brief copies override flavor of scan rings - * @param i_pImageIn points to start of hardware image. - * @param i_pOverride points to override rings. - * @param o_pImageOut points to HOMER image. - * @param i_ddLevel dd level associated with P9 chip. - * @param i_pBuf1 work buffer1 - * @param i_bufSize1 work buffer1 size. - * @param i_pBuf2 work buffer2 - * @param i_bufSize2 work buffer2 size. - * @param i_imgType image type to be built. - * @param o_qpmr temp instance of QpmrHeaderLayout_t - * @param i_platId platform associated with scan ring. - * @return IMG_BUILD_SUCCESS if successful else error code. - */ - uint32_t layoutCmnRingsForCme( Homerlayout_t* i_pHomer, + return rc; +} + +//------------------------------------------------------------------------------ +/** + * @brief creates a lean scan ring layout for core specific rings in HOMER. + * @param i_pHOMER points to HOMER image. + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData scan ring related data + * @param i_debugMode debug type set for scan rings + * @param i_ringVariant scan ring flavor + * @param i_imgType image type to be built + * @param io_cmeRings instance of RingBucket + * @param io_ringLength input: CME region length populated. Output: Max possible size of instance spec ring + * @param IMG_BUILD_SUCCESS if function succeeds else error code. + */ + +uint32_t layoutInstRingsForCme( Homerlayout_t* i_pHomer, const P9FuncModel& i_chipState, RingBufData& i_ringData, RingDebugMode_t i_debugMode, RingVariant_t i_ringVariant, ImageType_t i_imgType, RingBucket& io_cmeRings, - uint32_t& io_cmnRingSize ) + uint32_t& io_ringLength ) +{ + FAPI_DBG( "> layoutInstRingsForCme"); + uint32_t rc = IMG_BUILD_SUCCESS; + // Let us find out ring-pair which is biggest in list of 12 ring pairs + uint32_t maxCoreSpecRingLength = 0; + uint32_t ringLength = 0; + uint32_t tempSize = 0; + uint32_t tempRepairLength = 0; + uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; + + do { - FAPI_DBG( "> layoutCmnRingsForCme"); - uint32_t rc = IMG_BUILD_SUCCESS; - - do + if( !i_imgType.cmeCoreSpecificRingBuild ) { + break; + } - uint32_t tempSize = 0; - uint32_t ringSize = 0; - uint8_t* pRingStart = &i_pHomer->cpmrRegion.cmeSramRegion[io_cmnRingSize]; - uint16_t* pScanRingIndex = (uint16_t*) pRingStart; - uint8_t* pRingPayload = pRingStart + CORE_COMMON_RING_INDEX_SIZE; - uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; - - if( !i_imgType.cmeCommonRingBuild ) + for( uint32_t exId = 0; exId < MAX_CMES_PER_CHIP; exId++ ) + { + if( !i_chipState.isExFunctional( exId ) ) { - break; + FAPI_DBG( "ignoring ex %d for instance ring size consideration", exId); + continue; } - for( uint32_t ringIndex = 0; ringIndex < EC::g_ecData.iv_num_common_rings; - ringIndex++ ) + ringLength = 0; + + for( uint32_t coreId = 0; coreId < MAX_CORES_PER_EX; coreId++ ) { - ringSize = i_ringData.iv_sizeWorkBuf1; + if( !i_chipState.isCoreFunctional( ((2 * exId ) + coreId)) ) + { + FAPI_DBG( "ignoring core %d for instance ring size consideration", (2 * exId ) + coreId ); + continue; + } + + tempSize = i_ringData.iv_sizeWorkBuf1; rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, P9_XIP_MAGIC_CME, i_chipState.getChipLevel(), - io_cmeRings.getCommonRingId( ringIndex ), + io_cmeRings.getInstRingId(0), P9_TOR::CME, i_ringVariant, - CORE0_CHIPLET_ID , + CORE0_CHIPLET_ID + ((2 * exId) + coreId), &i_ringData.iv_pWorkBuf1, - ringSize, + tempSize, 0 ); - if( ( i_ringData.iv_sizeWorkBuf1 == ringSize ) || ( 0 == ringSize ) || + if( (i_ringData.iv_sizeWorkBuf1 == tempSize) || (0 == tempSize ) || ( 0 != rc ) ) { - FAPI_INF( "Did not find core common ring Id %d ", ringIndex ); - rc = 0; - ringSize = 0; + FAPI_DBG( "could not determine size of ring id %d of core %d", + io_cmeRings.getInstRingId(0), ((2 * exId) + coreId) ); continue; } - ALIGN_DWORD(tempSize, ringSize) - ALIGN_RING_LOC( pRingStart, pRingPayload ); - - memcpy( pRingPayload, i_ringData.iv_pWorkBuf1, ringSize ); - *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pRingPayload - pRingStart) + ringStartToHdrOffset); - - - io_cmeRings.setRingOffset( pRingPayload, io_cmeRings.getCommonRingId( ringIndex )); - io_cmeRings.setRingSize( io_cmeRings.getCommonRingId( ringIndex ), ringSize ); - io_cmeRings.extractRing( i_ringData.iv_pWorkBuf1, ringSize, io_cmeRings.getCommonRingId( ringIndex ) ); - - pRingPayload = pRingPayload + ringSize; + ALIGN_DWORD(tempRepairLength, tempSize); + ringLength += tempSize; } - ringSize = (pRingPayload - pRingStart); - - if( ringSize > CORE_COMMON_RING_INDEX_SIZE ) - { - io_cmnRingSize += (pRingPayload - pRingStart); - ALIGN_DWORD(tempSize, io_cmnRingSize) - } + maxCoreSpecRingLength = ringLength > maxCoreSpecRingLength ? ringLength : maxCoreSpecRingLength; } - while(0); - - FAPI_DBG( "< layoutCmnRingsForCme"); - return rc; - } + if( maxCoreSpecRingLength > 0 ) + { + maxCoreSpecRingLength += sizeof(CoreSpecRingList_t); + ROUND_OFF_32B(maxCoreSpecRingLength); + } -//------------------------------------------------------------------------------ - /** - * @brief creates a lean scan ring layout for core specific rings in HOMER. - * @param i_pHOMER points to HOMER image. - * @param i_chipState functional state of all cores within P9 chip - * @param i_ringData scan ring related data - * @param i_debugMode debug type set for scan rings - * @param i_ringVariant scan ring flavor - * @param i_imgType image type to be built - * @param io_cmeRings instance of RingBucket - * @param io_ringLength input: CME region length populated. Output: Max possible size of instance spec ring - * @param IMG_BUILD_SUCCESS if function succeeds else error code. - */ + FAPI_DBG("Max Instance Spec Ring 0x%08X", maxCoreSpecRingLength); + // Let us copy the rings now. - uint32_t layoutInstRingsForCme( Homerlayout_t* i_pHomer, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - RingVariant_t i_ringVariant, - ImageType_t i_imgType, - RingBucket& io_cmeRings, - uint32_t& io_ringLength ) - { - FAPI_DBG( "> layoutInstRingsForCme"); - uint32_t rc = IMG_BUILD_SUCCESS; - // Let us find out ring-pair which is biggest in list of 12 ring pairs - uint32_t maxCoreSpecRingLength = 0; - uint32_t ringLength = 0; - uint32_t tempSize = 0; - uint32_t tempRepairLength = 0; - uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; + uint8_t* pRingStart = NULL; + uint8_t* pRingPayload = NULL; + uint16_t* pScanRingIndex = NULL; - do + for( uint32_t exId = 0; exId < MAX_CMES_PER_CHIP; exId++ ) { - if( !i_imgType.cmeCoreSpecificRingBuild ) + pRingStart = (uint8_t*)&i_pHomer->cpmrRegion.cmeSramRegion[io_ringLength + ( exId * maxCoreSpecRingLength ) ]; + pRingPayload = pRingStart + sizeof(CoreSpecRingList_t); + pScanRingIndex = (uint16_t*)pRingStart; + + if( !i_chipState.isExFunctional( exId ) ) { - break; + FAPI_DBG("skipping copy of core specific rings of ex %d", exId); + continue; } - for( uint32_t exId = 0; exId < MAX_CME_PER_CHIP; exId++ ) + for( uint32_t coreId = 0; coreId < MAX_CORES_PER_EX; coreId++ ) { - if( !i_chipState.isExFunctional( exId ) ) + if( !i_chipState.isCoreFunctional( ((2 * exId ) + coreId)) ) { - FAPI_DBG( "ignoring ex %d for instance ring size consideration", exId); + FAPI_DBG( "ignoring core %d for instance ring size consideration", (2 * exId ) + coreId ); continue; } - ringLength = 0; + tempSize = i_ringData.iv_sizeWorkBuf1; + rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, + P9_XIP_MAGIC_CME, + i_chipState.getChipLevel(), + io_cmeRings.getInstRingId(0), + P9_TOR::CME, + i_ringVariant, + CORE0_CHIPLET_ID + ((2 * exId) + coreId), + &i_ringData.iv_pWorkBuf1, + tempSize, + 0 ); - for( uint32_t coreId = 0; coreId < MAX_CORES_PER_EX; coreId++ ) + if( (i_ringData.iv_sizeWorkBuf1 == tempSize) || (0 == tempSize ) || + ( 0 != rc ) ) { - if( !i_chipState.isCoreFunctional( ((2 * exId ) + coreId)) ) - { - FAPI_DBG( "ignoring core %d for instance ring size consideration", (2 * exId ) + coreId ); - continue; - } - - tempSize = i_ringData.iv_sizeWorkBuf1; - rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, - P9_XIP_MAGIC_CME, - i_chipState.getChipLevel(), - io_cmeRings.getInstRingId(0), - P9_TOR::CME, - i_ringVariant, - CORE0_CHIPLET_ID + ((2 * exId) + coreId), - &i_ringData.iv_pWorkBuf1, - tempSize, - 0 ); - - if( (i_ringData.iv_sizeWorkBuf1 == tempSize) || (0 == tempSize ) || - ( 0 != rc ) ) - { - FAPI_DBG( "could not determine size of ring id %d of core %d", - io_cmeRings.getInstRingId(0), ((2 * exId) + coreId) ); - continue; - } - - ALIGN_DWORD(tempRepairLength, tempSize); - ringLength += tempSize; + FAPI_INF("Instance ring Id %d not found for EX %d core %d", + io_cmeRings.getInstRingId(0), exId, coreId ); + rc = 0; + tempSize = 0; + continue; } - maxCoreSpecRingLength = ringLength > maxCoreSpecRingLength ? ringLength : maxCoreSpecRingLength; - } + ALIGN_RING_LOC( pRingStart, pRingPayload ); + memcpy( pRingPayload, i_ringData.iv_pWorkBuf1, tempSize); + io_cmeRings.extractRing( i_ringData.iv_pWorkBuf1, tempSize, io_cmeRings.getInstRingId(0) ); + io_cmeRings.setRingOffset( pRingPayload, + io_cmeRings.getInstRingId(0), + ( MAX_CORES_PER_EX * exId ) + coreId ); + *(pScanRingIndex + coreId) = SWIZZLE_2_BYTE((pRingPayload - pRingStart ) + ringStartToHdrOffset); - if( maxCoreSpecRingLength > 0 ) - { - maxCoreSpecRingLength += sizeof(CoreSpecRingList_t); - ROUND_OFF_32B(maxCoreSpecRingLength); + pRingPayload = pRingPayload + tempSize; + io_cmeRings.setRingSize( io_cmeRings.getInstRingId(0), tempSize, ((MAX_CORES_PER_EX * exId) + coreId) ); } + } - FAPI_DBG("Max Instance Spec Ring 0x%08X", maxCoreSpecRingLength); - // Let us copy the rings now. + io_ringLength = maxCoreSpecRingLength; + } + while(0); - uint8_t* pRingStart = NULL; - uint8_t* pRingPayload = NULL; - uint16_t* pScanRingIndex = NULL; + FAPI_DBG( "< layoutInstRingsForCme"); - for( uint32_t exId = 0; exId < MAX_CME_PER_CHIP; exId++ ) - { - pRingStart = (uint8_t*)&i_pHomer->cpmrRegion.cmeSramRegion[io_ringLength + ( exId * maxCoreSpecRingLength ) ]; - pRingPayload = pRingStart + sizeof(CoreSpecRingList_t); - pScanRingIndex = (uint16_t*)pRingStart; + return rc; +} - if( !i_chipState.isExFunctional( exId ) ) - { - FAPI_DBG("skipping copy of core specific rings of ex %d", exId); - continue; - } +//------------------------------------------------------------------------------ - for( uint32_t coreId = 0; coreId < MAX_CORES_PER_EX; coreId++ ) - { - if( !i_chipState.isCoreFunctional( ((2 * exId ) + coreId)) ) - { - FAPI_DBG( "ignoring core %d for instance ring size consideration", (2 * exId ) + coreId ); - continue; - } - - tempSize = i_ringData.iv_sizeWorkBuf1; - rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, - P9_XIP_MAGIC_CME, - i_chipState.getChipLevel(), - io_cmeRings.getInstRingId(0), - P9_TOR::CME, - i_ringVariant, - CORE0_CHIPLET_ID + ((2 * exId) + coreId), - &i_ringData.iv_pWorkBuf1, - tempSize, - 0 ); - - if( (i_ringData.iv_sizeWorkBuf1 == tempSize) || (0 == tempSize ) || - ( 0 != rc ) ) - { - FAPI_INF("Instance ring Id %d not found for EX %d core %d", - io_cmeRings.getInstRingId(0), exId, coreId ); - rc = 0; - tempSize = 0; - continue; - } - - ALIGN_RING_LOC( pRingStart, pRingPayload ); - memcpy( pRingPayload, i_ringData.iv_pWorkBuf1, tempSize); - io_cmeRings.extractRing( i_ringData.iv_pWorkBuf1, tempSize, io_cmeRings.getInstRingId(0) ); - io_cmeRings.setRingOffset( pRingPayload, - io_cmeRings.getInstRingId(0), - ( MAX_CORES_PER_EX * exId ) + coreId ); - *(pScanRingIndex + coreId) = SWIZZLE_2_BYTE((pRingPayload - pRingStart ) + ringStartToHdrOffset); - - pRingPayload = pRingPayload + tempSize; - io_cmeRings.setRingSize( io_cmeRings.getInstRingId(0), tempSize, ((MAX_CORES_PER_EX * exId) + coreId) ); - } - } +uint32_t layoutCmeScanOverride( Homerlayout_t* i_pHomer, + void* i_pOverride, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + ImageType_t i_imgType, + uint32_t& io_ovrdRingLength ) +{ + FAPI_INF("> layoutCmeScanOverride" ); + uint32_t rc = IMG_BUILD_SUCCESS; + uint32_t tempRingLength = io_ovrdRingLength; + uint32_t tempBufSize = 0; + uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; + + RingBucket cmeOvrdRings( PLAT_CME, + (uint8_t*)&i_pHomer->cpmrRegion, + i_debugMode ); - io_ringLength = maxCoreSpecRingLength; + do + { + if( !i_imgType.cmeCommonRingBuild ) + { + break; } - while(0); - FAPI_DBG( "< layoutInstRingsForCme"); + //Start override ring from the actual end of base common rings. Remember overrides reside within + //common rings region + uint8_t* pOverrideStart = &i_pHomer->cpmrRegion.cmeSramRegion[tempRingLength]; + uint16_t* pScanRingIndex = (uint16_t*)pOverrideStart; - return rc; - } + //get core common rings + uint8_t* pOverrideRingPayload = pOverrideStart + CORE_COMMON_RING_INDEX_SIZE; + bool overrideNotFound = true; -//------------------------------------------------------------------------------ + for( uint8_t ringIndex = 0; ringIndex < EC::g_ecData.iv_num_common_rings; + ringIndex++ ) + { + tempBufSize = i_ringData.iv_sizeWorkBuf2; - uint32_t layoutCmeScanOverride( Homerlayout_t* i_pHomer, - void* i_pOverride, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - ImageType_t i_imgType, - uint32_t& io_ovrdRingLength ) - { - FAPI_INF("> layoutCmeScanOverride" ); - uint32_t rc = IMG_BUILD_SUCCESS; - uint32_t tempRingLength = io_ovrdRingLength; - uint32_t tempBufSize = 0; - uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; + FAPI_DBG("Calling P9_TOR::tor_get_single_ring ring 0x%08X", ringIndex); + rc = tor_get_single_ring( i_pOverride, + P9_XIP_MAGIC_SEEPROM, + i_chipState.getChipLevel(), + cmeOvrdRings.getCommonRingId( ringIndex ), + P9_TOR::SBE, + OVERRIDE, + CORE0_CHIPLET_ID, + &i_ringData.iv_pWorkBuf2, + tempBufSize, + 0 ); - RingBucket cmeOvrdRings( PLAT_CME, - (uint8_t*)&i_pHomer->cpmrRegion, - i_debugMode ); + if( (i_ringData.iv_sizeWorkBuf2 == tempBufSize) || (0 == tempBufSize ) || + ( 0 != rc ) ) - do - { - if( !i_imgType.cmeCommonRingBuild ) { - break; + tempBufSize = 0; + continue; } - //Start override ring from the actual end of base common rings. Remember overrides reside within - //common rings region - uint8_t* pOverrideStart = &i_pHomer->cpmrRegion.cmeSramRegion[tempRingLength]; - uint16_t* pScanRingIndex = (uint16_t*)pOverrideStart; + overrideNotFound = false; + ALIGN_DWORD(tempRingLength, tempBufSize) + ALIGN_RING_LOC( pOverrideStart, pOverrideRingPayload ); - //get core common rings - uint8_t* pOverrideRingPayload = pOverrideStart + CORE_COMMON_RING_INDEX_SIZE; - bool overrideNotFound = true; + memcpy( pOverrideRingPayload, i_ringData.iv_pWorkBuf2, tempBufSize); + *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pOverrideRingPayload - pOverrideStart) + ringStartToHdrOffset); - for( uint8_t ringIndex = 0; ringIndex < EC::g_ecData.iv_num_common_rings; - ringIndex++ ) - { - tempBufSize = i_ringData.iv_sizeWorkBuf2; + cmeOvrdRings.setRingOffset(pOverrideRingPayload, cmeOvrdRings.getCommonRingId( ringIndex )); + cmeOvrdRings.setRingSize( cmeOvrdRings.getCommonRingId( ringIndex ), tempBufSize ); + cmeOvrdRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, cmeOvrdRings.getCommonRingId( ringIndex ) ); - FAPI_DBG("Calling P9_TOR::tor_get_single_ring ring 0x%08X", ringIndex); - rc = tor_get_single_ring( i_pOverride, - P9_XIP_MAGIC_SEEPROM, - i_chipState.getChipLevel(), - cmeOvrdRings.getCommonRingId( ringIndex ), - P9_TOR::SBE, - OVERRIDE, - CORE0_CHIPLET_ID, - &i_ringData.iv_pWorkBuf2, - tempBufSize, - 0 ); + pOverrideRingPayload = pOverrideRingPayload + tempBufSize; + } - if( (i_ringData.iv_sizeWorkBuf2 == tempBufSize) || (0 == tempBufSize ) || - ( 0 != rc ) ) + if( overrideNotFound ) + { + FAPI_INF("Overrides not found for CME"); + rc = BUILD_FAIL_OVERRIDE; // Not considered an error + break; + } - { - tempBufSize = 0; - continue; - } + io_ovrdRingLength += (pOverrideRingPayload - pOverrideStart ); + ALIGN_DWORD(tempRingLength, io_ovrdRingLength) - overrideNotFound = false; - ALIGN_DWORD(tempRingLength, tempBufSize) - ALIGN_RING_LOC( pOverrideStart, pOverrideRingPayload ); + FAPI_DBG( "Override Ring Length 0x%08X", io_ovrdRingLength ); + } + while(0); - memcpy( pOverrideRingPayload, i_ringData.iv_pWorkBuf2, tempBufSize); - *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pOverrideRingPayload - pOverrideStart) + ringStartToHdrOffset); + cmeOvrdRings.dumpOverrideRings(); - cmeOvrdRings.setRingOffset(pOverrideRingPayload, cmeOvrdRings.getCommonRingId( ringIndex )); - cmeOvrdRings.setRingSize( cmeOvrdRings.getCommonRingId( ringIndex ), tempBufSize ); - cmeOvrdRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, cmeOvrdRings.getCommonRingId( ringIndex ) ); + FAPI_INF("< layoutCmeScanOverride" ); + return rc; +} - pOverrideRingPayload = pOverrideRingPayload + tempBufSize; - } +//------------------------------------------------------------------------------ + +/** + * @brief creates a lean scan ring layout for core rings in HOMER. + * @param i_pHOMER points to HOMER image. + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData processor target + * @param i_debugMode debug mode type for scan rings + * @param i_riskLevel IPL type + * @param i_imgType image type to be built + * @param i_pOverride points to override binary. + * @param IMG_BUILD_SUCCESS if function succeeds else error code. + */ +uint32_t layoutRingsForCME( Homerlayout_t* i_pHomer, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + uint32_t i_riskLevel, + ImageType_t i_imgType, + void* i_pOverride ) +{ + FAPI_DBG( "> layoutRingsForCME"); + uint32_t rc = IMG_BUILD_SUCCESS; + uint32_t ringLength = 0; + uint32_t tempLength = 0; + RingVariant_t l_ringVariant = BASE; + cmeHeader_t* pCmeHdr = (cmeHeader_t*) &i_pHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + RingBucket cmeRings( PLAT_CME, + (uint8_t*)&i_pHomer->cpmrRegion, + i_debugMode ); + + do + { + if( !i_imgType.cmeCommonRingBuild ) + { + break; + } + + // get all the rings pertaining to CME in a work buffer first. + if( i_riskLevel ) + { + l_ringVariant = RL; + } + + ringLength = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset) + SWIZZLE_4_BYTE( + pCmeHdr->g_cme_pstate_region_length); + //save the length where hcode ends + tempLength = ringLength; + + layoutCmnRingsForCme( i_pHomer, + i_chipState, + i_ringData, + i_debugMode, + l_ringVariant, + i_imgType, + cmeRings, + ringLength ); + + if( i_pOverride ) + { + uint32_t temp = 0; + uint32_t tempRc = 0; + ALIGN_DWORD( temp, ringLength ); + temp = ringLength; + + tempRc = layoutCmeScanOverride( i_pHomer, + i_pOverride, + i_chipState, + i_ringData, + i_debugMode, + i_imgType, + ringLength ); - if( overrideNotFound ) + if( BUILD_FAIL_OVERRIDE == tempRc ) { - FAPI_INF("Overrides not found for CME"); - rc = BUILD_FAIL_OVERRIDE; // Not considered an error - break; + //found no core overrides + pCmeHdr->g_cme_cmn_ring_ovrd_offset = 0; + } + else + { + pCmeHdr->g_cme_cmn_ring_ovrd_offset = temp; } + } - io_ovrdRingLength += (pOverrideRingPayload - pOverrideStart ); - ALIGN_DWORD(tempRingLength, io_ovrdRingLength) + pCmeHdr->g_cme_common_ring_length = ringLength - tempLength; //cmn ring end - hcode end - FAPI_DBG( "Override Ring Length 0x%08X", io_ovrdRingLength ); + if( !pCmeHdr->g_cme_common_ring_length ) + { + //No common ring , so force offset to be 0 + pCmeHdr->g_cme_common_ring_offset = 0; } - while(0); - cmeOvrdRings.dumpOverrideRings(); + tempLength = ringLength; + tempLength = (( tempLength + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT ); //multiple of 32B + ringLength = tempLength << CME_BLK_SIZE_SHIFT; //start position of instance rings - FAPI_INF("< layoutCmeScanOverride" ); - return rc; - } + layoutInstRingsForCme( i_pHomer, + i_chipState, + i_ringData, + i_debugMode, + BASE, // VPD rings are always BASE + i_imgType, + cmeRings, + ringLength ); -//------------------------------------------------------------------------------ + if( ringLength ) + { + pCmeHdr->g_cme_max_spec_ring_length = + ( ringLength + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT; + pCmeHdr->g_cme_core_spec_ring_offset = tempLength; + } - /** - * @brief creates a lean scan ring layout for core rings in HOMER. - * @param i_pHOMER points to HOMER image. - * @param i_chipState functional state of all cores within P9 chip - * @param i_ringData processor target - * @param i_debugMode debug mode type for scan rings - * @param i_riskLevel IPL type - * @param i_imgType image type to be built - * @param i_pOverride points to override binary. - * @param IMG_BUILD_SUCCESS if function succeeds else error code. - */ - uint32_t layoutRingsForCME( Homerlayout_t* i_pHomer, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - uint32_t i_riskLevel, - ImageType_t i_imgType, - void* i_pOverride ) - { - FAPI_DBG( "> layoutRingsForCME"); - uint32_t rc = IMG_BUILD_SUCCESS; - uint32_t ringLength = 0; - uint32_t tempLength = 0; - RingVariant_t l_ringVariant = BASE; - cmeHeader_t* pCmeHdr = (cmeHeader_t*) &i_pHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - RingBucket cmeRings( PLAT_CME, - (uint8_t*)&i_pHomer->cpmrRegion, - i_debugMode ); + //Let us handle endianess now + pCmeHdr->g_cme_common_ring_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length); + pCmeHdr->g_cme_core_spec_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset); + pCmeHdr->g_cme_max_spec_ring_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length); + pCmeHdr->g_cme_cmn_ring_ovrd_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_cmn_ring_ovrd_offset); + } + while(0); - do - { - if( !i_imgType.cmeCommonRingBuild ) - { - break; - } + cmeRings.dumpRings(); + FAPI_DBG("CME Header Ring Details "); + FAPI_DBG( "PS Offset %d (0x%08X)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset), + SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset)); + FAPI_DBG("PS Lengtrh %d (0x%08X)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length), + SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length) ); + FAPI_DBG("Common Ring Offset %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset), + SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset)); + FAPI_DBG("Common Ring Length %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length), + SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length)); + FAPI_DBG("Instance Ring Offset / 32 %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset), + SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset)); + FAPI_DBG("Instance Ring Length / 32 %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length), - // get all the rings pertaining to CME in a work buffer first. - if( i_riskLevel ) - { - l_ringVariant = RL; - } + SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length)); - ringLength = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset) + SWIZZLE_4_BYTE( - pCmeHdr->g_cme_pstate_region_length); - //save the length where hcode ends - tempLength = ringLength; - - layoutCmnRingsForCme( i_pHomer, - i_chipState, - i_ringData, - i_debugMode, - l_ringVariant, - i_imgType, - cmeRings, - ringLength ); - - if( i_pOverride ) - { - uint32_t temp = 0; - uint32_t tempRc = 0; - ALIGN_DWORD( temp, ringLength ); - temp = ringLength; - - tempRc = layoutCmeScanOverride( i_pHomer, - i_pOverride, - i_chipState, - i_ringData, - i_debugMode, - i_imgType, - ringLength ); - - if( BUILD_FAIL_OVERRIDE == tempRc ) - { - //found no core overrides - pCmeHdr->g_cme_cmn_ring_ovrd_offset = 0; - } - else - { - pCmeHdr->g_cme_cmn_ring_ovrd_offset = temp; - } - } + FAPI_DBG( "< layoutRingsForCME"); - pCmeHdr->g_cme_common_ring_length = ringLength - tempLength; //cmn ring end - hcode end + return rc; +} - if( !pCmeHdr->g_cme_common_ring_length ) - { - //No common ring , so force offset to be 0 - pCmeHdr->g_cme_common_ring_offset = 0; - } - tempLength = ringLength; - tempLength = (( tempLength + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT ); //multiple of 32B - ringLength = tempLength << CME_BLK_SIZE_SHIFT; //start position of instance rings +//------------------------------------------------------------------------------ - layoutInstRingsForCme( i_pHomer, - i_chipState, - i_ringData, - i_debugMode, - BASE, // VPD rings are always BASE - i_imgType, - cmeRings, - ringLength ); +/** + * @brief creates a scan ring layout for quad common rings in HOMER. + * @param i_pHOMER points to HOMER image. + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData contains ring buffers and respective sizes + * @param i_debugMode scan ring debug state + * @param i_ringVariant variant of the scan ring to be copied. + * @param io_qpmrHdr instance of QPMR header. + * @param i_imgType image type to be built + * @param io_sgpeRings stores position and length of all quad common rings. + * @param IMG_BUILD_SUCCESS if function succeeds else error code. + */ +uint32_t layoutCmnRingsForSgpe( Homerlayout_t* i_pHomer, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + RingVariant_t i_ringVariant, + QpmrHeaderLayout_t& io_qpmrHdr, + ImageType_t i_imgType, + RingBucket& io_sgpeRings ) +{ + FAPI_DBG("> layoutCmnRingsForSgpe"); + + uint32_t rc = IMG_BUILD_SUCCESS; + uint32_t sgpeHcodeSize = SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength); + uint8_t* pCmnRingPayload = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize + + QUAD_COMMON_RING_INDEX_SIZE];; + uint16_t* pCmnRingIndex = (uint16_t*)&i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize]; + uint8_t* pRingStart = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize]; + uint32_t ringIndex = 0; + uint32_t tempLength = 0; + uint32_t tempBufSize = i_ringData.iv_sizeWorkBuf1; + uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; + + RingBucket sgpeRings( PLAT_SGPE, + (uint8_t*)&i_pHomer->qpmrRegion, + i_debugMode ); + + do + { + if( !i_imgType.sgpeCommonRingBuild ) + { + break; + } - if( ringLength ) - { - pCmeHdr->g_cme_max_spec_ring_length = - ( ringLength + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT; - pCmeHdr->g_cme_core_spec_ring_offset = tempLength; - } + //get core common rings + for( ; ringIndex < EQ::g_eqData.iv_num_common_rings; ringIndex++ ) + { + tempBufSize = i_ringData.iv_sizeWorkBuf1; + + rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, + P9_XIP_MAGIC_SGPE, + i_chipState.getChipLevel(), + io_sgpeRings.getCommonRingId( ringIndex ), + P9_TOR::SGPE, + i_ringVariant, + CACHE0_CHIPLET_ID, + &i_ringData.iv_pWorkBuf1, + tempBufSize, + 0 ); + + if( (i_ringData.iv_sizeWorkBuf1 == tempBufSize) || (0 == tempBufSize ) || + ( 0 != rc ) ) + { + FAPI_INF( "did not find quad common ring %d", ringIndex ); + rc = IMG_BUILD_SUCCESS; + tempBufSize = 0; + continue; + } + + ALIGN_DWORD(tempLength, tempBufSize) + ALIGN_RING_LOC( pRingStart, pCmnRingPayload ); + + memcpy( pCmnRingPayload, i_ringData.iv_pWorkBuf1, tempBufSize); + io_sgpeRings.setRingOffset( pCmnRingPayload, io_sgpeRings.getCommonRingId( ringIndex ) ); + *(pCmnRingIndex + ringIndex) = SWIZZLE_2_BYTE((pCmnRingPayload - pRingStart ) + ringStartToHdrOffset); + io_sgpeRings.setRingSize( io_sgpeRings.getCommonRingId( ringIndex ), tempBufSize ); + io_sgpeRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, io_sgpeRings.getCommonRingId( ringIndex ) ); + pCmnRingPayload = pCmnRingPayload + tempBufSize; + + }//for common rings + + tempLength = pCmnRingPayload - pRingStart; + io_qpmrHdr.quadCommonRingLength = tempLength; + io_qpmrHdr.quadCommonRingOffset = i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage - + (uint8_t*)&i_pHomer->qpmrRegion; + io_qpmrHdr.quadCommonRingOffset += sgpeHcodeSize; + FAPI_DBG("Quad Cmn Ring Length 0x%08X", io_qpmrHdr.quadCommonRingLength ); - //Let us handle endianess now - pCmeHdr->g_cme_common_ring_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length); - pCmeHdr->g_cme_core_spec_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset); - pCmeHdr->g_cme_max_spec_ring_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length); - pCmeHdr->g_cme_cmn_ring_ovrd_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_cmn_ring_ovrd_offset); - } - while(0); - - cmeRings.dumpRings(); - FAPI_DBG("CME Header Ring Details "); - FAPI_DBG( "PS Offset %d (0x%08X)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset), - SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset)); - FAPI_DBG("PS Lengtrh %d (0x%08X)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length), - SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length) ); - FAPI_DBG("Common Ring Offset %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset), - SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset)); - FAPI_DBG("Common Ring Length %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length), - SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length)); - FAPI_DBG("Instance Ring Offset / 32 %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset), - SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset)); - FAPI_DBG("Instance Ring Length / 32 %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length), - - SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length)); - - FAPI_DBG( "< layoutRingsForCME"); - - return rc; } + while(0); //building common rings + + FAPI_DBG("< layoutCmnRingsForSgpe"); + return rc; +} //------------------------------------------------------------------------------ - /** - * @brief creates a scan ring layout for quad common rings in HOMER. - * @param i_pHOMER points to HOMER image. - * @param i_chipState functional state of all cores within P9 chip - * @param i_ringData contains ring buffers and respective sizes - * @param i_debugMode scan ring debug state - * @param i_ringVariant variant of the scan ring to be copied. - * @param io_qpmrHdr instance of QPMR header. - * @param i_imgType image type to be built - * @param io_sgpeRings stores position and length of all quad common rings. - * @param IMG_BUILD_SUCCESS if function succeeds else error code. - */ - uint32_t layoutCmnRingsForSgpe( Homerlayout_t* i_pHomer, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - RingVariant_t i_ringVariant, - QpmrHeaderLayout_t& io_qpmrHdr, - ImageType_t i_imgType, - RingBucket& io_sgpeRings ) +/** + * @brief creates a scan ring layout for quad common rings in HOMER. + * @param i_pHOMER points to HOMER image. + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData contains ring buffers and respective sizes + * @param i_debugMode scan ring debug state + * @param i_ringVariant variant of the scan ring to be copied. + * @param io_qpmrHdr instance of QPMR header. + * @param i_imgType image type to be built + * @param io_sgpeRings stores position and length of all quad common rings. + * @param IMG_BUILD_SUCCESS if function succeeds else error code. + */ +uint32_t layoutInstRingsForSgpe( Homerlayout_t* i_pHomer, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + RingVariant_t i_ringVariant, + QpmrHeaderLayout_t& io_qpmrHdr, + ImageType_t i_imgType, + RingBucket& io_sgpeRings ) +{ + uint32_t rc = IMG_BUILD_SUCCESS; + + do { - FAPI_DBG("> layoutCmnRingsForSgpe"); + if( !i_imgType.sgpeCacheSpecificRingBuild ) + { + break; + } - uint32_t rc = IMG_BUILD_SUCCESS; - uint32_t sgpeHcodeSize = SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength); - uint8_t* pCmnRingPayload = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize + - QUAD_COMMON_RING_INDEX_SIZE];; - uint16_t* pCmnRingIndex = (uint16_t*)&i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize]; - uint8_t* pRingStart = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize]; - uint32_t ringIndex = 0; - uint32_t tempLength = 0; - uint32_t tempBufSize = i_ringData.iv_sizeWorkBuf1; + uint32_t quadSpecRingStart = SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength) + io_qpmrHdr.quadCommonRingLength; + uint16_t* pCmnRingIndex = (uint16_t*)&i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[ quadSpecRingStart ]; + uint8_t* pRingStart = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[quadSpecRingStart]; + uint8_t* instRingPayLoad = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[ quadSpecRingStart + + QUAD_SPEC_RING_INDEX_LEN ]; uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; - RingBucket sgpeRings( PLAT_SGPE, - (uint8_t*)&i_pHomer->qpmrRegion, - i_debugMode ); - - do + for( uint32_t cacheInst = 0; cacheInst < MAX_QUADS_PER_CHIP; cacheInst++ ) { - if( !i_imgType.sgpeCommonRingBuild ) + if( !i_chipState.isQuadFunctional( cacheInst ) ) { - break; + pCmnRingIndex = pCmnRingIndex + QUAD_SPEC_RING_INDEX_SIZE; // Jump to next Quad Index + //Quad is not functional. Don't populate rings. Ring Index will be zero by design + FAPI_INF("Skipping copy of cache chiplet%d", cacheInst); + continue; } - //get core common rings - for( ; ringIndex < EQ::g_eqData.iv_num_common_rings; ringIndex++ ) + ExIdMap ExChipletRingMap; + uint32_t chipletId = 0; + uint32_t tempBufSize = 0; + uint32_t tempLength = 0; + + for( uint32_t ringIndex = 0; ringIndex < EQ::g_eqData.iv_num_instance_rings_scan_addrs; + ringIndex++ ) { tempBufSize = i_ringData.iv_sizeWorkBuf1; + chipletId = ExChipletRingMap.getInstanceId( CACHE0_CHIPLET_ID + cacheInst , ringIndex ); rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, P9_XIP_MAGIC_SGPE, i_chipState.getChipLevel(), - io_sgpeRings.getCommonRingId( ringIndex ), + io_sgpeRings.getInstRingId( ringIndex ), P9_TOR::SGPE, i_ringVariant, - CACH0_CHIPLET_ID, + chipletId, &i_ringData.iv_pWorkBuf1, tempBufSize, 0 ); @@ -2368,1050 +2479,946 @@ extern "C" if( (i_ringData.iv_sizeWorkBuf1 == tempBufSize) || (0 == tempBufSize ) || ( 0 != rc ) ) { - FAPI_INF( "did not find quad common ring %d", ringIndex ); - rc = IMG_BUILD_SUCCESS; + FAPI_DBG( "did not find quad spec ring %d for cache Inst %d", ringIndex , cacheInst ); + rc = 0; tempBufSize = 0; continue; } ALIGN_DWORD(tempLength, tempBufSize) - ALIGN_RING_LOC( pRingStart, pCmnRingPayload ); + ALIGN_RING_LOC( pRingStart, instRingPayLoad ); - memcpy( pCmnRingPayload, i_ringData.iv_pWorkBuf1, tempBufSize); - io_sgpeRings.setRingOffset( pCmnRingPayload, io_sgpeRings.getCommonRingId( ringIndex ) ); - *(pCmnRingIndex + ringIndex) = SWIZZLE_2_BYTE((pCmnRingPayload - pRingStart ) + ringStartToHdrOffset); - io_sgpeRings.setRingSize( io_sgpeRings.getCommonRingId( ringIndex ), tempBufSize ); - io_sgpeRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, io_sgpeRings.getCommonRingId( ringIndex ) ); - pCmnRingPayload = pCmnRingPayload + tempBufSize; + memcpy( instRingPayLoad, i_ringData.iv_pWorkBuf1, tempBufSize); + io_sgpeRings.setRingOffset( instRingPayLoad, io_sgpeRings.getInstRingId( ringIndex ), chipletId ); + *(pCmnRingIndex + ringIndex) = SWIZZLE_2_BYTE((instRingPayLoad - pRingStart ) + ringStartToHdrOffset); + io_sgpeRings.setRingSize( io_sgpeRings.getInstRingId( ringIndex ), tempBufSize, chipletId ); + instRingPayLoad = instRingPayLoad + tempBufSize; + io_sgpeRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, io_sgpeRings.getInstRingId( ringIndex ) ); - }//for common rings - - tempLength = pCmnRingPayload - pRingStart; - io_qpmrHdr.quadCommonRingLength = tempLength; - io_qpmrHdr.quadCommonRingOffset = i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage - - (uint8_t*)&i_pHomer->qpmrRegion; - io_qpmrHdr.quadCommonRingOffset += sgpeHcodeSize; - FAPI_DBG("Quad Cmn Ring Length 0x%08X", io_qpmrHdr.quadCommonRingLength ); + }//for quad spec rings + pCmnRingIndex = pCmnRingIndex + QUAD_SPEC_RING_INDEX_SIZE; // Jump to next Quad Index } - while(0); //building common rings - - FAPI_DBG("< layoutCmnRingsForSgpe"); - return rc; + io_qpmrHdr.quadSpecRingOffset = io_qpmrHdr.quadCommonRingOffset + io_qpmrHdr.quadCommonRingLength; + io_qpmrHdr.quadSpecRingLength = (instRingPayLoad - pRingStart); + FAPI_DBG("Instance Ring Length 0x%08X", io_qpmrHdr.quadSpecRingLength); } + while(0); + + return rc; +} //------------------------------------------------------------------------------ - /** - * @brief creates a scan ring layout for quad common rings in HOMER. - * @param i_pHOMER points to HOMER image. - * @param i_chipState functional state of all cores within P9 chip - * @param i_ringData contains ring buffers and respective sizes - * @param i_debugMode scan ring debug state - * @param i_ringVariant variant of the scan ring to be copied. - * @param io_qpmrHdr instance of QPMR header. - * @param i_imgType image type to be built - * @param io_sgpeRings stores position and length of all quad common rings. - * @param IMG_BUILD_SUCCESS if function succeeds else error code. - */ - uint32_t layoutInstRingsForSgpe( Homerlayout_t* i_pHomer, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - RingVariant_t i_ringVariant, - QpmrHeaderLayout_t& io_qpmrHdr, - ImageType_t i_imgType, - RingBucket& io_sgpeRings ) +/** + * @brief creates a scan ring layout for quad common rings in HOMER. + * @param i_pHOMER points to HOMER image. + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData contains ring buffers and respective sizes + * @param i_debugMode scan ring debug state + * @param i_riskLevel true if system IPL is in risk level mode else false. + * @param io_qpmrHdr instance of QPMR header. + * @param i_imgType image type to be built + * @param IMG_BUILD_SUCCESS if function succeeds else error code. + */ +uint32_t layoutRingsForSGPE( Homerlayout_t* i_pHomer, + void* i_pOverride, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + uint32_t i_riskLevel, + QpmrHeaderLayout_t& io_qpmrHdr, + ImageType_t i_imgType ) +{ + FAPI_DBG( "> layoutRingsForSGPE"); + uint32_t rc = IMG_BUILD_SUCCESS; + RingVariant_t l_ringVariant = BASE; + sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)& i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; + RingBucket sgpeRings( PLAT_SGPE, + (uint8_t*)&i_pHomer->qpmrRegion, + i_debugMode ); + + do { - uint32_t rc = IMG_BUILD_SUCCESS; - do + // get all the rings pertaining to CME in a work buffer first. + if( i_riskLevel ) { - if( !i_imgType.sgpeCacheSpecificRingBuild ) - { - break; - } - - uint32_t quadSpecRingStart = SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength) + io_qpmrHdr.quadCommonRingLength; - uint16_t* pCmnRingIndex = (uint16_t*)&i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[ quadSpecRingStart ]; - uint8_t* pRingStart = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[quadSpecRingStart]; - uint8_t* instRingPayLoad = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[ quadSpecRingStart + - QUAD_SPEC_RING_INDEX_LEN ]; - uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; - - for( uint32_t cacheInst = 0; cacheInst < MAX_CACHE_CHIPLET; cacheInst++ ) - { - if( !i_chipState.isQuadFunctional( cacheInst ) ) - { - pCmnRingIndex = pCmnRingIndex + QUAD_SPEC_RING_INDEX_SIZE; // Jump to next Quad Index - //Quad is not functional. Don't populate rings. Ring Index will be zero by design - FAPI_INF("Skipping copy of cache chiplet%d", cacheInst); - continue; - } - - ExIdMap ExChipletRingMap; - uint32_t chipletId = 0; - uint32_t tempBufSize = 0; - uint32_t tempLength = 0; - - for( uint32_t ringIndex = 0; ringIndex < EQ::g_eqData.iv_num_instance_rings_scan_addrs; - ringIndex++ ) - { - tempBufSize = i_ringData.iv_sizeWorkBuf1; - chipletId = ExChipletRingMap.getInstanceId( CACH0_CHIPLET_ID + cacheInst , ringIndex ); - - rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, - P9_XIP_MAGIC_SGPE, - i_chipState.getChipLevel(), - io_sgpeRings.getInstRingId( ringIndex ), - P9_TOR::SGPE, - i_ringVariant, - chipletId, - &i_ringData.iv_pWorkBuf1, - tempBufSize, - 0 ); - - if( (i_ringData.iv_sizeWorkBuf1 == tempBufSize) || (0 == tempBufSize ) || - ( 0 != rc ) ) - { - FAPI_DBG( "did not find quad spec ring %d for cache Inst %d", ringIndex , cacheInst ); - rc = 0; - tempBufSize = 0; - continue; - } - - ALIGN_DWORD(tempLength, tempBufSize) - ALIGN_RING_LOC( pRingStart, instRingPayLoad ); - - memcpy( instRingPayLoad, i_ringData.iv_pWorkBuf1, tempBufSize); - io_sgpeRings.setRingOffset( instRingPayLoad, io_sgpeRings.getInstRingId( ringIndex ), chipletId ); - *(pCmnRingIndex + ringIndex) = SWIZZLE_2_BYTE((instRingPayLoad - pRingStart ) + ringStartToHdrOffset); - io_sgpeRings.setRingSize( io_sgpeRings.getInstRingId( ringIndex ), tempBufSize, chipletId ); - instRingPayLoad = instRingPayLoad + tempBufSize; - io_sgpeRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, io_sgpeRings.getInstRingId( ringIndex ) ); - - }//for quad spec rings - - pCmnRingIndex = pCmnRingIndex + QUAD_SPEC_RING_INDEX_SIZE; // Jump to next Quad Index - } - - io_qpmrHdr.quadSpecRingOffset = io_qpmrHdr.quadCommonRingOffset + io_qpmrHdr.quadCommonRingLength; - io_qpmrHdr.quadSpecRingLength = (instRingPayLoad - pRingStart); - FAPI_DBG("Instance Ring Length 0x%08X", io_qpmrHdr.quadSpecRingLength); + l_ringVariant = RL; } - while(0); - - return rc; - } - -//------------------------------------------------------------------------------ - - /** - * @brief creates a scan ring layout for quad common rings in HOMER. - * @param i_pHOMER points to HOMER image. - * @param i_chipState functional state of all cores within P9 chip - * @param i_ringData contains ring buffers and respective sizes - * @param i_debugMode scan ring debug state - * @param i_riskLevel true if system IPL is in risk level mode else false. - * @param io_qpmrHdr instance of QPMR header. - * @param i_imgType image type to be built - * @param IMG_BUILD_SUCCESS if function succeeds else error code. - */ - uint32_t layoutRingsForSGPE( Homerlayout_t* i_pHomer, - void* i_pOverride, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - uint32_t i_riskLevel, - QpmrHeaderLayout_t& io_qpmrHdr, - ImageType_t i_imgType ) - { - FAPI_DBG( "> layoutRingsForSGPE"); - uint32_t rc = IMG_BUILD_SUCCESS; - RingVariant_t l_ringVariant = BASE; - sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)& i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT]; - RingBucket sgpeRings( PLAT_SGPE, - (uint8_t*)&i_pHomer->qpmrRegion, - i_debugMode ); - do + //Manage the Quad Common rings in HOMER + layoutCmnRingsForSgpe( i_pHomer, + i_chipState, + i_ringData, + i_debugMode, + l_ringVariant, + io_qpmrHdr, + i_imgType, + sgpeRings ); + + //Manage the Quad Override rings in HOMER + layoutSgpeScanOverride( i_pHomer, + i_pOverride, + i_chipState, + i_ringData, + i_debugMode, + io_qpmrHdr, + i_imgType ); + + //Manage the Quad specific rings in HOMER + layoutInstRingsForSgpe( i_pHomer, + i_chipState, + i_ringData, + i_debugMode, + BASE, // VPD rings are always BASE + io_qpmrHdr, + i_imgType, + sgpeRings ); + + if( 0 == io_qpmrHdr.quadCommonRingLength ) { + //If quad common rings don't exist ensure its offset in image header is zero + pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset = 0; + } - // get all the rings pertaining to CME in a work buffer first. - if( i_riskLevel ) - { - l_ringVariant = RL; - } - - //Manage the Quad Common rings in HOMER - layoutCmnRingsForSgpe( i_pHomer, - i_chipState, - i_ringData, - i_debugMode, - l_ringVariant, - io_qpmrHdr, - i_imgType, - sgpeRings ); - - //Manage the Quad Override rings in HOMER - layoutSgpeScanOverride( i_pHomer, - i_pOverride, - i_chipState, - i_ringData, - i_debugMode, - io_qpmrHdr, - i_imgType ); - - //Manage the Quad specific rings in HOMER - layoutInstRingsForSgpe( i_pHomer, - i_chipState, - i_ringData, - i_debugMode, - BASE, // VPD rings are always BASE - io_qpmrHdr, - i_imgType, - sgpeRings ); - - if( 0 == io_qpmrHdr.quadCommonRingLength ) - { - //If quad common rings don't exist ensure its offset in image header is zero - pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset = 0; - } - - if( io_qpmrHdr.quadSpecRingLength > 0 ) - { - pSgpeImgHdr->g_sgpe_spec_ring_occ_offset = io_qpmrHdr.quadCommonRingLength + - SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength); - pSgpeImgHdr->g_sgpe_scom_offset = - SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength) + io_qpmrHdr.quadCommonRingLength + - io_qpmrHdr.quadSpecRingLength; - } + if( io_qpmrHdr.quadSpecRingLength > 0 ) + { + pSgpeImgHdr->g_sgpe_spec_ring_occ_offset = io_qpmrHdr.quadCommonRingLength + + SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength); + pSgpeImgHdr->g_sgpe_scom_offset = + SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength) + io_qpmrHdr.quadCommonRingLength + + io_qpmrHdr.quadSpecRingLength; } - while(0); //building instance rings - - //Let us handle endianes at last - io_qpmrHdr.quadCommonRingOffset = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonRingOffset); - io_qpmrHdr.quadCommonRingLength = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonRingLength); - io_qpmrHdr.quadCommonOvrdOffset = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonOvrdOffset); - io_qpmrHdr.quadCommonOvrdLength = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonOvrdLength); - io_qpmrHdr.quadSpecRingOffset = SWIZZLE_4_BYTE(io_qpmrHdr.quadSpecRingOffset); - io_qpmrHdr.quadSpecRingLength = SWIZZLE_4_BYTE(io_qpmrHdr.quadSpecRingLength); - pSgpeImgHdr->g_sgpe_spec_ring_occ_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset); - pSgpeImgHdr->g_sgpe_scom_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_scom_offset); - sgpeRings.dumpRings(); - - FAPI_DBG("SGPE Header Ring Details "); - FAPI_DBG("Common Ring Offset %d (0x%08X) ", - SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset), - SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset)); - FAPI_DBG("Instance Ring Offset %d (0x%08X) ", - SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset), - SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset)); - - - return rc; } + while(0); //building instance rings + + //Let us handle endianes at last + io_qpmrHdr.quadCommonRingOffset = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonRingOffset); + io_qpmrHdr.quadCommonRingLength = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonRingLength); + io_qpmrHdr.quadCommonOvrdOffset = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonOvrdOffset); + io_qpmrHdr.quadCommonOvrdLength = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonOvrdLength); + io_qpmrHdr.quadSpecRingOffset = SWIZZLE_4_BYTE(io_qpmrHdr.quadSpecRingOffset); + io_qpmrHdr.quadSpecRingLength = SWIZZLE_4_BYTE(io_qpmrHdr.quadSpecRingLength); + pSgpeImgHdr->g_sgpe_spec_ring_occ_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset); + pSgpeImgHdr->g_sgpe_scom_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_scom_offset); + sgpeRings.dumpRings(); + + FAPI_DBG("SGPE Header Ring Details "); + FAPI_DBG("Common Ring Offset %d (0x%08X) ", + SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset), + SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset)); + FAPI_DBG("Instance Ring Offset %d (0x%08X) ", + SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset), + SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset)); + + + return rc; +} //--------------------------------------------------------------------------- - /** - * @brief updates the IVPR attributes for SGPE, PGPE. - * @brief i_pChipHomer points to start of HOMER - */ - fapi2::ReturnCode updateGpeAttributes( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) - { - QpmrHeaderLayout_t* pQpmrHdr = (QpmrHeaderLayout_t*)i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader; - PpmrHeader_t* pPpmrHdr = (PpmrHeader_t*) i_pChipHomer->ppmrRegion.ppmrHeader; +/** + * @brief updates the IVPR attributes for SGPE, PGPE. + * @brief i_pChipHomer points to start of HOMER + */ +fapi2::ReturnCode updateGpeAttributes( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) +{ + QpmrHeaderLayout_t* pQpmrHdr = (QpmrHeaderLayout_t*)i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader; + PpmrHeader_t* pPpmrHdr = (PpmrHeader_t*) i_pChipHomer->ppmrRegion.ppmrHeader; - uint32_t attrVal = SWIZZLE_4_BYTE(pQpmrHdr->bootCopierOffset); - attrVal |= (0x80000000 | ONE_MB); + uint32_t attrVal = SWIZZLE_4_BYTE(pQpmrHdr->bootCopierOffset); + attrVal |= (0x80000000 | ONE_MB); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET, - i_procTgt, - attrVal ), - "Error from FAPI_ATTR_SET for attribute ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET, + i_procTgt, + attrVal ), + "Error from FAPI_ATTR_SET for attribute ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET"); - FAPI_DBG("Set ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET to 0x%08X", attrVal ); + FAPI_DBG("Set ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET to 0x%08X", attrVal ); - attrVal = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bc_offset); - attrVal |= (0x80000000 | PPMR_OFFSET); + attrVal = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bc_offset); + attrVal |= (0x80000000 | PPMR_HOMER_OFFSET); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET, - i_procTgt, - attrVal ), - "Error from FAPI_ATTR_SET for attribute ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET, + i_procTgt, + attrVal ), + "Error from FAPI_ATTR_SET for attribute ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET"); - FAPI_DBG("Set ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET to 0x%08X", attrVal ); + FAPI_DBG("Set ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET to 0x%08X", attrVal ); - fapi_try_exit: - return fapi2::current_err; - } +fapi_try_exit: + return fapi2::current_err; +} //--------------------------------------------------------------------------- - /** - * @brief Set the Fabric System, Group and Chip IDs into SGPE and CME headers - * @brief i_pChipHomer points to start of HOMER - */ - fapi2::ReturnCode setFabricIds( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) - { +/** + * @brief Set the Fabric System, Group and Chip IDs into SGPE and CME headers + * @brief i_pChipHomer points to start of HOMER + */ +fapi2::ReturnCode setFabricIds( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) +{ - uint32_t l_system_id; - uint8_t l_group_id; - uint8_t l_chip_id; - fapi2::buffer<uint16_t> l_location_id = 0; - uint16_t l_locationVal = 0; + uint32_t l_system_id; + uint8_t l_group_id; + uint8_t l_chip_id; + fapi2::buffer<uint16_t> l_location_id = 0; + uint16_t l_locationVal = 0; - cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT]; + cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; - FAPI_DBG(" ==================== Fabric IDs ================="); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, - i_procTgt, - l_system_id), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_FABRIC_SYSTEM_ID"); + FAPI_DBG(" ==================== Fabric IDs ================="); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, + i_procTgt, + l_system_id), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_FABRIC_SYSTEM_ID"); - FAPI_DBG("Fabric System ID : 0x%04X", l_system_id); + FAPI_DBG("Fabric System ID : 0x%04X", l_system_id); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, - i_procTgt, - l_group_id), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_FABRIC_GROUP_ID"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, + i_procTgt, + l_group_id), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_FABRIC_GROUP_ID"); - FAPI_DBG("Fabric Group ID : 0x%01X", l_group_id); + FAPI_DBG("Fabric Group ID : 0x%01X", l_group_id); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, - i_procTgt, - l_chip_id), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_FABRIC_CHIP_ID"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, + i_procTgt, + l_chip_id), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_FABRIC_CHIP_ID"); - FAPI_DBG("Fabric Chip ID : 0x%01X", l_chip_id); + FAPI_DBG("Fabric Chip ID : 0x%01X", l_chip_id); - // Create a unit16_t Location Ids in the form of: - // 0:3 Group ID (loaded from ATTR_PROC_FABRIC_GROUP_ID) - // 4:6 Chip ID (loaded from ATTR_PROC_FABRIC_CHIP_ID) - // 7 0 - // 8:12 System ID (loaded from ATTR_PROC_FABRIC_SYSTEM_ID) - // 13:15 00 + // Create a unit16_t Location Ids in the form of: + // 0:3 Group ID (loaded from ATTR_PROC_FABRIC_GROUP_ID) + // 4:6 Chip ID (loaded from ATTR_PROC_FABRIC_CHIP_ID) + // 7 0 + // 8:12 System ID (loaded from ATTR_PROC_FABRIC_SYSTEM_ID) + // 13:15 00 - l_location_id.insert < 0, 4, 8 - 4, uint8_t > ( l_group_id ); - l_location_id.insert < 4, 3, 8 - 3, uint8_t > ( l_chip_id ); - l_location_id.insert < 8, 5, 32 - 5, uint32_t > ( l_system_id ); + l_location_id.insert < 0, 4, 8 - 4, uint8_t > ( l_group_id ); + l_location_id.insert < 4, 3, 8 - 3, uint8_t > ( l_chip_id ); + l_location_id.insert < 8, 5, 32 - 5, uint32_t > ( l_system_id ); - FAPI_DBG("Location ID : 0x%04X", l_location_id); + FAPI_DBG("Location ID : 0x%04X", l_location_id); - l_location_id.extract<0, 16>(l_locationVal); - // Populate the CME Header - pCmeHdr->g_cme_location_id = SWIZZLE_2_BYTE(l_locationVal); + l_location_id.extract<0, 16>(l_locationVal); + // Populate the CME Header + pCmeHdr->g_cme_location_id = SWIZZLE_2_BYTE(l_locationVal); - // Populate the SGPE Header - pSgpeHdr->g_sgpe_location_id = SWIZZLE_2_BYTE(l_locationVal); + // Populate the SGPE Header + pSgpeHdr->g_sgpe_location_id = SWIZZLE_2_BYTE(l_locationVal); - fapi_try_exit: - return fapi2::current_err; +fapi_try_exit: + return fapi2::current_err; - } +} //--------------------------------------------------------------------------------------------------- - /** - * @brief populates EQ SCOM restore region of HOMER with SCOM restore value for NCU RNG BAR ENABLE. - * @param i_pChipHomer points to start of P9 HOMER - * @param i_procTgt fapi2 target for p9 chip. - * @return faip2 return code. - */ - fapi2::ReturnCode populateNcuRingBarScomReg( void* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) +/** + * @brief populates EQ SCOM restore region of HOMER with SCOM restore value for NCU RNG BAR ENABLE. + * @param i_pChipHomer points to start of P9 HOMER + * @param i_procTgt fapi2 target for p9 chip. + * @return faip2 return code. + */ +fapi2::ReturnCode populateNcuRingBarScomReg( void* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) +{ + FAPI_DBG("> populateNcuRingBarScomReg"); + + do { - FAPI_DBG("> populateNcuRingBarScomReg"); - - do - { - uint8_t attrVal = 0; - uint64_t nxRangeBarAddrOffset = 0; - uint64_t regNcuRngBarData = 0; - uint64_t baseAddressNm0 = 0; - uint64_t baseAddressNm1 = 0; - uint64_t baseAddressMirror = 0; - uint32_t ncuBarRegisterAddr = 0; - const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; - - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_ENABLE, - i_procTgt, - attrVal ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_NX_RNG_BAR_ENABLE"); - - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET, - FAPI_SYSTEM, - nxRangeBarAddrOffset ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET"); - - FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_procTgt, - baseAddressNm0, - baseAddressNm1, - baseAddressMirror, - regNcuRngBarData), - "Failed in p9_fbc_utils_get_chip_base_address" ); - - - if( fapi2::ENUM_ATTR_PROC_NX_RNG_BAR_ENABLE_ENABLE == attrVal ) - { - //Set bit0 which corresponds to bit DARN_BAR_EN of reg NCU_DAR_BAR - regNcuRngBarData |= DARN_BAR_EN_POS ; - } + uint8_t attrVal = 0; + uint64_t nxRangeBarAddrOffset = 0; + uint64_t regNcuRngBarData = 0; + uint64_t baseAddressNm0 = 0; + uint64_t baseAddressNm1 = 0; + uint64_t baseAddressMirror = 0; + uint32_t ncuBarRegisterAddr = 0; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; - regNcuRngBarData += nxRangeBarAddrOffset; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_ENABLE, + i_procTgt, + attrVal ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_NX_RNG_BAR_ENABLE"); - for( uint32_t exIndex = 0; exIndex < MAX_CME_PER_CHIP; exIndex++ ) - { - ncuBarRegisterAddr = EX_0_NCU_DARN_BAR_REG; - ncuBarRegisterAddr |= (( exIndex >> 1) << 24 ); - ncuBarRegisterAddr |= ( exIndex & 0x01 ) ? 0x0400 : 0x0000; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET, + FAPI_SYSTEM, + nxRangeBarAddrOffset ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET"); - FAPI_DBG("CME%d NCU_DARN_BAR Addr 0x%08x Data 0x%016lx ", - exIndex, ncuBarRegisterAddr, regNcuRngBarData ); + FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_procTgt, + baseAddressNm0, + baseAddressNm1, + baseAddressMirror, + regNcuRngBarData), + "Failed in p9_fbc_utils_get_chip_base_address" ); - StopReturnCode_t stopRc = - stopImageSection::p9_stop_save_scom( i_pChipHomer, - ncuBarRegisterAddr, - regNcuRngBarData , - stopImageSection::P9_STOP_SCOM_REPLACE, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - if( stopRc ) - { - FAPI_ERR("Failed to update CME%d NCU_DARN_RNG_BAR Reg RC: 0x%08x", - exIndex, stopRc ); - break; - } - } + if( fapi2::ENUM_ATTR_PROC_NX_RNG_BAR_ENABLE_ENABLE == attrVal ) + { + //Set bit0 which corresponds to bit DARN_BAR_EN of reg NCU_DAR_BAR + regNcuRngBarData |= DARN_BAR_EN_POS ; + } + regNcuRngBarData += nxRangeBarAddrOffset; + + for( uint32_t exIndex = 0; exIndex < MAX_CMES_PER_CHIP; exIndex++ ) + { + ncuBarRegisterAddr = EX_0_NCU_DARN_BAR_REG; + ncuBarRegisterAddr |= (( exIndex >> 1) << 24 ); + ncuBarRegisterAddr |= ( exIndex & 0x01 ) ? 0x0400 : 0x0000; + + FAPI_DBG("CME%d NCU_DARN_BAR Addr 0x%08x Data 0x%016lx ", + exIndex, ncuBarRegisterAddr, regNcuRngBarData ); + + StopReturnCode_t stopRc = + stopImageSection::p9_stop_save_scom( i_pChipHomer, + ncuBarRegisterAddr, + regNcuRngBarData , + stopImageSection::P9_STOP_SCOM_REPLACE, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + + if( stopRc ) + { + FAPI_ERR("Failed to update CME%d NCU_DARN_RNG_BAR Reg RC: 0x%08x", + exIndex, stopRc ); + break; + } } - while(0); - FAPI_DBG("< populateNcuRingBarScomReg"); - fapi_try_exit: - return fapi2::current_err; } + while(0); + + FAPI_DBG("< populateNcuRingBarScomReg"); +fapi_try_exit: + return fapi2::current_err; +} //-------------------------------------------------------------------------------------------- - /** - * @brief populate L2 Epsilon SCOM register. - * @param i_pChipHomer points to start of P9 HOMER. - * @return fapi2 return code. - */ - fapi2::ReturnCode populateEpsilonL2ScomReg( void* i_pChipHomer ) +/** + * @brief populate L2 Epsilon SCOM register. + * @param i_pChipHomer points to start of P9 HOMER. + * @return fapi2 return code. + */ +fapi2::ReturnCode populateEpsilonL2ScomReg( void* i_pChipHomer ) +{ + FAPI_DBG("> populateEpsilonL2ScomReg"); + + do { - FAPI_DBG("> populateEpsilonL2ScomReg"); + uint32_t attrValT0 = 0; + uint32_t attrValT1 = 0; + uint32_t attrValT2 = 0; + uint32_t scomAddr = 0; + uint32_t rc = IMG_BUILD_SUCCESS; - do - { - uint32_t attrValT0 = 0; - uint32_t attrValT1 = 0; - uint32_t attrValT2 = 0; - uint32_t scomAddr = 0; - uint32_t rc = IMG_BUILD_SUCCESS; + uint64_t l_epsilonScomVal; + fapi2::buffer<uint64_t> epsilonValBuf; - uint64_t l_epsilonScomVal; - fapi2::buffer<uint64_t> epsilonValBuf; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; - const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + //============================================================================= + //Determine SCOM register data value for EX_L2_RD_EPS_REG by reading attributes + //============================================================================= - //============================================================================= - //Determine SCOM register data value for EX_L2_RD_EPS_REG by reading attributes - //============================================================================= + //----------------------------- Tier0(T0)-------------------------------------- - //----------------------------- Tier0(T0)-------------------------------------- + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, + FAPI_SYSTEM, + attrValT0 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T0"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, - FAPI_SYSTEM, - attrValT0 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T0"); + attrValT0 = attrValT0 / 8 + 1; + epsilonValBuf.insert<0, 12, 20, uint32_t>( attrValT0 ); - attrValT0 = attrValT0 / 8 + 1; - epsilonValBuf.insert<0, 12, 20, uint32_t>( attrValT0 ); + //----------------------------- Tier1(T1)-------------------------------------- - //----------------------------- Tier1(T1)-------------------------------------- + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T1, + FAPI_SYSTEM, + attrValT1 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T1"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T1, - FAPI_SYSTEM, - attrValT1 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T1"); + attrValT1 = attrValT1 / 8 + 1; + epsilonValBuf.insert<12, 12, 20, uint32_t>( attrValT1 ); - attrValT1 = attrValT1 / 8 + 1; - epsilonValBuf.insert<12, 12, 20, uint32_t>( attrValT1 ); + //----------------------------- Tier2(T2)-------------------------------------- - //----------------------------- Tier2(T2)-------------------------------------- + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, + FAPI_SYSTEM, + attrValT2 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T2"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, - FAPI_SYSTEM, - attrValT2 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T2"); - attrValT2 = attrValT2 / 8 + 1; - epsilonValBuf.insert<24, 12, 20, uint32_t>( attrValT2 ); + attrValT2 = attrValT2 / 8 + 1; + epsilonValBuf.insert<24, 12, 20, uint32_t>( attrValT2 ); - epsilonValBuf.extract<0, 64>(l_epsilonScomVal); + epsilonValBuf.extract<0, 64>(l_epsilonScomVal); - //----------------------- Updating SCOM Registers using STOP API -------------------- - uint32_t eqCnt = 0; + //----------------------- Updating SCOM Registers using STOP API -------------------- + uint32_t eqCnt = 0; - for( ; eqCnt < MAX_CACHE_CHIPLET; eqCnt++ ) - { - scomAddr = (EX_L2_RD_EPS_REG | (eqCnt << QUAD_BIT_POS)); - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + for( ; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ ) + { + scomAddr = (EX_L2_RD_EPS_REG | (eqCnt << QUAD_BIT_POS)); + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } + if( rc ) + { + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; + } - scomAddr |= ODD_EVEN_EX_POS; - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + scomAddr |= ODD_EVEN_EX_POS; + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } + if( rc ) + { + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; } + } - //=============================================================================== - //Determine SCOM register data value for EX_L2_WR_EPS_REG by reading attributes - //=============================================================================== - l_epsilonScomVal = 0; - epsilonValBuf.flush<0>(); - - //----------------------------- Tier1(T1)-------------------------------------- + //=============================================================================== + //Determine SCOM register data value for EX_L2_WR_EPS_REG by reading attributes + //=============================================================================== + l_epsilonScomVal = 0; + epsilonValBuf.flush<0>(); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1, - FAPI_SYSTEM, - attrValT1 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T1"); + //----------------------------- Tier1(T1)-------------------------------------- - attrValT1 = attrValT1 / 8 + 1; - epsilonValBuf.insert< 0, 12, 20, uint32_t >(attrValT1); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1, + FAPI_SYSTEM, + attrValT1 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T1"); - //----------------------------- Tier2(T2)-------------------------------------- + attrValT1 = attrValT1 / 8 + 1; + epsilonValBuf.insert< 0, 12, 20, uint32_t >(attrValT1); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2, - FAPI_SYSTEM, - attrValT2 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T2"); + //----------------------------- Tier2(T2)-------------------------------------- - attrValT2 = attrValT2 / 8 + 1; - epsilonValBuf.insert< 12, 12, 20, uint32_t >(attrValT2); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2, + FAPI_SYSTEM, + attrValT2 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T2"); - // p9.l2.scom.inifile: - // EPS_DIVIDER_MODE = 0001 - // EPS_MODE_SEL = 0 - // EPS_CNT_USE_L2_DIVIDER_EN = 0 - // L2_EPS_STEP_MODE = 0000 - epsilonValBuf.setBit<27>(); - epsilonValBuf.extract<0, 64>(l_epsilonScomVal); + attrValT2 = attrValT2 / 8 + 1; + epsilonValBuf.insert< 12, 12, 20, uint32_t >(attrValT2); - //----------------------- Updating SCOM Registers using STOP API -------------------- + // p9.l2.scom.inifile: + // EPS_DIVIDER_MODE = 0001 + // EPS_MODE_SEL = 0 + // EPS_CNT_USE_L2_DIVIDER_EN = 0 + // L2_EPS_STEP_MODE = 0000 + epsilonValBuf.setBit<27>(); - for( eqCnt = 0; eqCnt < MAX_CACHE_CHIPLET; eqCnt++ ) - { - scomAddr = (EX_L2_WR_EPS_REG | (eqCnt << QUAD_BIT_POS)); - FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", - scomAddr, l_epsilonScomVal); - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + epsilonValBuf.extract<0, 64>(l_epsilonScomVal); - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } + //----------------------- Updating SCOM Registers using STOP API -------------------- - scomAddr |= ODD_EVEN_EX_POS; - FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", - scomAddr, l_epsilonScomVal); - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + for( eqCnt = 0; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ ) + { + scomAddr = (EX_L2_WR_EPS_REG | (eqCnt << QUAD_BIT_POS)); + FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", + scomAddr, l_epsilonScomVal); + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } + if( rc ) + { + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; } - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ), - fapi2::EPSILON_SCOM_UPDATE_FAIL() - .set_STOP_API_SCOM_ERR( rc ) - .set_EPSILON_REG_ADDR( scomAddr ) - .set_EPSILON_REG_DATA( l_epsilonScomVal ), - "Failed to create restore entry for L2 Epsilon register" ); + scomAddr |= ODD_EVEN_EX_POS; + FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", + scomAddr, l_epsilonScomVal); + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + if( rc ) + { + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; + } } - while(0); - FAPI_DBG("< populateEpsilonL2ScomReg"); - fapi_try_exit: - return fapi2::current_err; + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ), + fapi2::EPSILON_SCOM_UPDATE_FAIL() + .set_STOP_API_SCOM_ERR( rc ) + .set_EPSILON_REG_ADDR( scomAddr ) + .set_EPSILON_REG_DATA( l_epsilonScomVal ), + "Failed to create restore entry for L2 Epsilon register" ); + } + while(0); + + FAPI_DBG("< populateEpsilonL2ScomReg"); +fapi_try_exit: + return fapi2::current_err; +} //--------------------------------------------------------------------------- - /** - * @brief populate L3 Epsilon SCOM register. - * @param i_pChipHomer points to start of P9 HOMER. - * @return fapi2 return code. - */ - fapi2::ReturnCode populateEpsilonL3ScomReg( void* i_pChipHomer ) +/** + * @brief populate L3 Epsilon SCOM register. + * @param i_pChipHomer points to start of P9 HOMER. + * @return fapi2 return code. + */ +fapi2::ReturnCode populateEpsilonL3ScomReg( void* i_pChipHomer ) +{ + FAPI_DBG("> populateEpsilonL3ScomReg"); + + do { - FAPI_DBG("> populateEpsilonL3ScomReg"); + uint32_t attrValT0 = 0; + uint32_t attrValT1 = 0; + uint32_t attrValT2 = 0; + uint32_t scomAddr = 0; + uint32_t rc = IMG_BUILD_SUCCESS; + uint64_t l_epsilonScomVal; + fapi2::buffer<uint64_t> epsilonValBuf; - do - { - uint32_t attrValT0 = 0; - uint32_t attrValT1 = 0; - uint32_t attrValT2 = 0; - uint32_t scomAddr = 0; - uint32_t rc = IMG_BUILD_SUCCESS; - uint64_t l_epsilonScomVal; - fapi2::buffer<uint64_t> epsilonValBuf; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; - const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + //===================================================================================== + //Determine SCOM register data value for EX_L3_RD_EPSILON_CFG_REG by reading attributes + //===================================================================================== - //===================================================================================== - //Determine SCOM register data value for EX_L3_RD_EPSILON_CFG_REG by reading attributes - //===================================================================================== + //----------------------------- Tier0(T0)-------------------------------------- - //----------------------------- Tier0(T0)-------------------------------------- + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, + FAPI_SYSTEM, + attrValT0 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T0"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, - FAPI_SYSTEM, - attrValT0 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T0"); + attrValT0 = attrValT0 / 8 + 1; + epsilonValBuf.insert<0, 12, 20, uint32_t>( attrValT0 ); - attrValT0 = attrValT0 / 8 + 1; - epsilonValBuf.insert<0, 12, 20, uint32_t>( attrValT0 ); + //----------------------------- Tier1(T1)-------------------------------------- - //----------------------------- Tier1(T1)-------------------------------------- + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T1, + FAPI_SYSTEM, + attrValT1 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T1"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T1, - FAPI_SYSTEM, - attrValT1 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T1"); + attrValT1 = attrValT1 / 8 + 1; + epsilonValBuf.insert<12, 12, 20, uint32_t>( attrValT1 ); - attrValT1 = attrValT1 / 8 + 1; - epsilonValBuf.insert<12, 12, 20, uint32_t>( attrValT1 ); + //----------------------------- Tier2(T2)-------------------------------------- - //----------------------------- Tier2(T2)-------------------------------------- + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, + FAPI_SYSTEM, + attrValT2 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T2"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, - FAPI_SYSTEM, - attrValT2 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T2"); + attrValT2 = attrValT2 / 8 + 1; + epsilonValBuf.insert<24, 12, 20, uint32_t>( attrValT2 ); - attrValT2 = attrValT2 / 8 + 1; - epsilonValBuf.insert<24, 12, 20, uint32_t>( attrValT2 ); + epsilonValBuf.extract<0, 64>(l_epsilonScomVal); - epsilonValBuf.extract<0, 64>(l_epsilonScomVal); + //----------------------- Updating SCOM Registers using STOP API -------------------- - //----------------------- Updating SCOM Registers using STOP API -------------------- + uint32_t eqCnt = 0; - uint32_t eqCnt = 0; + for( ; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ ) + { + scomAddr = (EX_L3_RD_EPSILON_CFG_REG | (eqCnt << QUAD_BIT_POS)); - for( ; eqCnt < MAX_CACHE_CHIPLET; eqCnt++ ) - { - scomAddr = (EX_L3_RD_EPSILON_CFG_REG | (eqCnt << QUAD_BIT_POS)); - - FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", - scomAddr, l_epsilonScomVal); - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", + scomAddr, l_epsilonScomVal); + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } + if( rc ) + { + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; + } - scomAddr |= ODD_EVEN_EX_POS; - FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", - scomAddr, l_epsilonScomVal); - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + scomAddr |= ODD_EVEN_EX_POS; + FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", + scomAddr, l_epsilonScomVal); + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } + if( rc ) + { + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; } + } - //===================================================================================== - //Determine SCOM register data value for EX_L3_L3_WR_EPSILON_CFG_REG by reading attributes - //===================================================================================== + //===================================================================================== + //Determine SCOM register data value for EX_L3_L3_WR_EPSILON_CFG_REG by reading attributes + //===================================================================================== - l_epsilonScomVal = 0; - epsilonValBuf.flush<0>(); + l_epsilonScomVal = 0; + epsilonValBuf.flush<0>(); - //----------------------------- Tier1(T1)-------------------------------------- + //----------------------------- Tier1(T1)-------------------------------------- - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1, - FAPI_SYSTEM, - attrValT1 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T1"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1, + FAPI_SYSTEM, + attrValT1 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T1"); - attrValT1 = attrValT1 / 8 + 1; - epsilonValBuf.insert< 0, 12, 20, uint32_t >(attrValT1); + attrValT1 = attrValT1 / 8 + 1; + epsilonValBuf.insert< 0, 12, 20, uint32_t >(attrValT1); - //----------------------------- Tier2(T2)-------------------------------------- + //----------------------------- Tier2(T2)-------------------------------------- - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2, - FAPI_SYSTEM, - attrValT2 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T2"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2, + FAPI_SYSTEM, + attrValT2 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T2"); - attrValT2 = attrValT2 / 8 + 1; - epsilonValBuf.insert< 12, 12, 20, uint32_t >(attrValT2); + attrValT2 = attrValT2 / 8 + 1; + epsilonValBuf.insert< 12, 12, 20, uint32_t >(attrValT2); - // p9.l3.scom.initfile: - // L3_EPS_STEP_MODE = 0000 - // L3_EPS_DIVIDER_MODE = 0001 - // EPS_CNT_USE_L3_DIVIDER_EN = 0 - epsilonValBuf.setBit<33>(); - epsilonValBuf.extract<0, 64>(l_epsilonScomVal); + // p9.l3.scom.initfile: + // L3_EPS_STEP_MODE = 0000 + // L3_EPS_DIVIDER_MODE = 0001 + // EPS_CNT_USE_L3_DIVIDER_EN = 0 + epsilonValBuf.setBit<33>(); - //----------------------- Updating SCOM Registers using STOP API -------------------- + epsilonValBuf.extract<0, 64>(l_epsilonScomVal); - for( eqCnt = 0; eqCnt < MAX_CACHE_CHIPLET; eqCnt++ ) - { - scomAddr = (EX_L3_L3_WR_EPSILON_CFG_REG | (eqCnt << QUAD_BIT_POS)); - - FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", - scomAddr, l_epsilonScomVal); - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + //----------------------- Updating SCOM Registers using STOP API -------------------- - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } + for( eqCnt = 0; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ ) + { + scomAddr = (EX_L3_L3_WR_EPSILON_CFG_REG | (eqCnt << QUAD_BIT_POS)); - scomAddr |= ODD_EVEN_EX_POS; + FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", + scomAddr, l_epsilonScomVal); + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", - scomAddr, l_epsilonScomVal); + if( rc ) + { + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; + } - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + scomAddr |= ODD_EVEN_EX_POS; - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } - } + FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", + scomAddr, l_epsilonScomVal); - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ), - fapi2::EPSILON_SCOM_UPDATE_FAIL() - .set_STOP_API_SCOM_ERR( rc ) - .set_EPSILON_REG_ADDR( scomAddr ) - .set_EPSILON_REG_DATA( l_epsilonScomVal ), - "Failed to create restore entry for L3 Epsilon register" ); + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + if( rc ) + { + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; + } } - while(0); - FAPI_DBG("< populateEpsilonL3ScomReg"); - fapi_try_exit: - return fapi2::current_err; + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ), + fapi2::EPSILON_SCOM_UPDATE_FAIL() + .set_STOP_API_SCOM_ERR( rc ) + .set_EPSILON_REG_ADDR( scomAddr ) + .set_EPSILON_REG_DATA( l_epsilonScomVal ), + "Failed to create restore entry for L3 Epsilon register" ); + } + while(0); + + FAPI_DBG("< populateEpsilonL3ScomReg"); +fapi_try_exit: + return fapi2::current_err; +} //--------------------------------------------------------------------------- - fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, - void* const i_pImageIn, - void* i_pHomerImage, - void* const i_pRingOverride, - SysPhase_t i_phase, - ImageType_t i_imgType, - void* const i_pBuf1, - const uint32_t i_sizeBuf1, - void* const i_pBuf2, - const uint32_t i_sizeBuf2, - void* const i_pBuf3, - const uint32_t i_sizeBuf3 ) +fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, + void* const i_pImageIn, + void* i_pHomerImage, + void* const i_pRingOverride, + SysPhase_t i_phase, + ImageType_t i_imgType, + void* const i_pBuf1, + const uint32_t i_sizeBuf1, + void* const i_pBuf2, + const uint32_t i_sizeBuf2, + void* const i_pBuf3, + const uint32_t i_sizeBuf3 ) - { - FAPI_IMP("Entering p9_hcode_image_build "); - fapi2::ReturnCode retCode; +{ + FAPI_IMP("Entering p9_hcode_image_build "); + fapi2::ReturnCode retCode; - do + do + { + FAPI_DBG("validating argument .."); + + retCode = validateInputArguments( i_pImageIn, i_pHomerImage, i_phase, + i_imgType, + i_pBuf1, + i_sizeBuf1, + i_pBuf2, + i_sizeBuf2, + i_pBuf3, + i_sizeBuf3 ); + + if( retCode ) { - FAPI_DBG("validating argument .."); + FAPI_ERR("Invalid arguments, escaping hcode image build"); + break; + } - retCode = validateInputArguments( i_pImageIn, i_pHomerImage, i_phase, - i_imgType, - i_pBuf1, - i_sizeBuf1, - i_pBuf2, - i_sizeBuf2, - i_pBuf3, - i_sizeBuf3 ); + uint8_t ecLevel = 0; + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, + i_procTgt, + ecLevel), + "Error from for attribute ATTR_EC"); - if( retCode ) - { - FAPI_ERR("Invalid arguments, escaping hcode image build"); - break; - } + FAPI_INF("Creating chip functional model"); - uint8_t ecLevel = 0; - FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, - i_procTgt, - ecLevel), - "Error from for attribute ATTR_EC"); - - FAPI_INF("Creating chip functional model"); - - P9FuncModel l_chipFuncModel( i_procTgt, ecLevel ); - Homerlayout_t* pChipHomer = ( Homerlayout_t*) i_pHomerImage; - const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; - uint32_t ppeImgRc = IMG_BUILD_SUCCESS; - QpmrHeaderLayout_t l_qpmrHdr; - // HW Image is a nested XIP Image. Let us read global TOC of hardware image - // and find out if XIP header of PPE image is contained therein. - // Let us start with SGPE - FAPI_INF("SGPE building"); - ppeImgRc = buildSgpeImage( i_pImageIn, pChipHomer, i_imgType, l_qpmrHdr ); - - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), - fapi2::SGPE_BUILD_FAIL() - .set_SGPE_FAIL_SECTN( ppeImgRc ), - "Failed to copy SGPE section in HOMER" ); - FAPI_INF("SGPE built"); - - // copy sections pertaining to self restore - // Note: this creates the CPMR header portion - - //let us determine if system is configured in fuse mode. This needs to - //be updated in a CPMR region. - uint8_t fuseModeState = 0; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FUSED_CORE_MODE, - FAPI_SYSTEM, - fuseModeState), - "Error from FAPI_ATTR_GET for attribute ATTR_FUSED_CORE_MODE"); - - FAPI_INF("CPMR / Self Restore building"); - ppeImgRc = buildCoreRestoreImage( i_pImageIn, pChipHomer, i_imgType, fuseModeState ); - - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), - fapi2::SELF_RESTORE_BUILD_FAIL() - .set_SELF_RESTORE_FAIL_SECTN( ppeImgRc ), - "Failed to copy core self restore section in HOMER" ); - FAPI_INF("Self Restore built "); - - // copy sections pertaining to CME - FAPI_INF("CPMR / CME building"); - uint64_t cpmrPhyAdd = 0; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HOMER_PHYS_ADDR, i_procTgt, cpmrPhyAdd ), - "Error from FAPI_ATTR_GET for ATTR_HOMER_PHYS_ADDR"); - FAPI_DBG("HOMER base address 0x%016lX", cpmrPhyAdd ); - ppeImgRc = buildCmeImage( i_pImageIn, pChipHomer, i_imgType, cpmrPhyAdd ); - - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), - fapi2::CME_BUILD_FAIL() - .set_CME_FAIL_SECTN( ppeImgRc ), - "Failed to copy CME section in HOMER" ); - FAPI_INF("CME built"); - - FAPI_INF("PGPE building"); - PpmrHeader_t l_ppmrHdr; - ppeImgRc = buildPgpeImage( i_pImageIn, pChipHomer, l_ppmrHdr, i_imgType ); - - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), - fapi2::PGPE_BUILD_FAIL() - .set_PGPE_FAIL_SECTN( ppeImgRc ), - "Failed to copy PGPE section in HOMER" ); - - //Update P State parameter block info in HOMER - retCode = buildParameterBlock( pChipHomer, i_procTgt, l_ppmrHdr, i_imgType ); - - if( retCode ) - { - FAPI_ERR("Failed to add parameter block"); - break; - } + P9FuncModel l_chipFuncModel( i_procTgt, ecLevel ); + Homerlayout_t* pChipHomer = ( Homerlayout_t*) i_pHomerImage; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + uint32_t ppeImgRc = IMG_BUILD_SUCCESS; + QpmrHeaderLayout_t l_qpmrHdr; + // HW Image is a nested XIP Image. Let us read global TOC of hardware image + // and find out if XIP header of PPE image is contained therein. + // Let us start with SGPE + FAPI_INF("SGPE building"); + ppeImgRc = buildSgpeImage( i_pImageIn, pChipHomer, i_imgType, l_qpmrHdr ); + + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), + fapi2::SGPE_BUILD_FAIL() + .set_SGPE_FAIL_SECTN( ppeImgRc ), + "Failed to copy SGPE section in HOMER" ); + FAPI_INF("SGPE built"); + + // copy sections pertaining to self restore + // Note: this creates the CPMR header portion + + //let us determine if system is configured in fuse mode. This needs to + //be updated in a CPMR region. + uint8_t fuseModeState = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FUSED_CORE_MODE, + FAPI_SYSTEM, + fuseModeState), + "Error from FAPI_ATTR_GET for attribute ATTR_FUSED_CORE_MODE"); + + FAPI_INF("CPMR / Self Restore building"); + ppeImgRc = buildCoreRestoreImage( i_pImageIn, pChipHomer, i_imgType, fuseModeState ); + + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), + fapi2::SELF_RESTORE_BUILD_FAIL() + .set_SELF_RESTORE_FAIL_SECTN( ppeImgRc ), + "Failed to copy core self restore section in HOMER" ); + FAPI_INF("Self Restore built "); + + // copy sections pertaining to CME + FAPI_INF("CPMR / CME building"); + uint64_t cpmrPhyAdd = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HOMER_PHYS_ADDR, i_procTgt, cpmrPhyAdd ), + "Error from FAPI_ATTR_GET for ATTR_HOMER_PHYS_ADDR"); + FAPI_DBG("HOMER base address 0x%016lX", cpmrPhyAdd ); + ppeImgRc = buildCmeImage( i_pImageIn, pChipHomer, i_imgType, cpmrPhyAdd ); + + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), + fapi2::CME_BUILD_FAIL() + .set_CME_FAIL_SECTN( ppeImgRc ), + "Failed to copy CME section in HOMER" ); + FAPI_INF("CME built"); + + FAPI_INF("PGPE building"); + PpmrHeader_t l_ppmrHdr; + ppeImgRc = buildPgpeImage( i_pImageIn, pChipHomer, l_ppmrHdr, i_imgType ); + + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), + fapi2::PGPE_BUILD_FAIL() + .set_PGPE_FAIL_SECTN( ppeImgRc ), + "Failed to copy PGPE section in HOMER" ); + + //Update P State parameter block info in HOMER + retCode = buildParameterBlock( pChipHomer, i_procTgt, l_ppmrHdr, i_imgType ); + + if( retCode ) + { + FAPI_ERR("Failed to add parameter block"); + break; + } - FAPI_INF("PGPE built"); - //Let us add Scan Rings to the image. - uint8_t l_ringDebug = 0; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_RING_DBG_MODE, - FAPI_SYSTEM, - l_ringDebug), - "Error from FAPI_ATTR_GET for attribute ATTR_SYSTEM_RING_DBG_MODE"); - - RingBufData l_ringData( i_pBuf1, - i_sizeBuf1, - i_pBuf2, - i_sizeBuf2, - i_pBuf3, - i_sizeBuf3 ); - - //Extract all the rings for CME platform from HW Image and VPD - ppeImgRc = getPpeScanRings( i_pImageIn, - PLAT_CME, - i_procTgt, - l_ringData, - i_imgType ); + FAPI_INF("PGPE built"); + //Let us add Scan Rings to the image. + uint8_t l_ringDebug = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_RING_DBG_MODE, + FAPI_SYSTEM, + l_ringDebug), + "Error from FAPI_ATTR_GET for attribute ATTR_SYSTEM_RING_DBG_MODE"); + + RingBufData l_ringData( i_pBuf1, + i_sizeBuf1, + i_pBuf2, + i_sizeBuf2, + i_pBuf3, + i_sizeBuf3 ); + + //Extract all the rings for CME platform from HW Image and VPD + ppeImgRc = getPpeScanRings( i_pImageIn, + PLAT_CME, + i_procTgt, + l_ringData, + i_imgType ); - if( ppeImgRc ) - { - FAPI_ERR( "failed to extract core scan rings rc = 0x%08X", ppeImgRc ); - break; - } + if( ppeImgRc ) + { + FAPI_ERR( "failed to extract core scan rings rc = 0x%08X", ppeImgRc ); + break; + } - uint8_t l_iplPhase = 0 ; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, - FAPI_SYSTEM, - l_iplPhase), - "Error from FAPI_ATTR_GET for ATTR_RISK_LEVEL"); - // create a layout of rings in HOMER for consumption of CME - ppeImgRc = layoutRingsForCME( pChipHomer, - l_chipFuncModel, - l_ringData, - (RingDebugMode_t)l_ringDebug, - l_iplPhase, - i_imgType, - i_pRingOverride ); - - if( ppeImgRc ) - { - FAPI_ERR("Failed to copy core Scan rings in HOMER rc 0x%08X", ppeImgRc ); - break; - } + uint8_t l_iplPhase = 0 ; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, + FAPI_SYSTEM, + l_iplPhase), + "Error from FAPI_ATTR_GET for ATTR_RISK_LEVEL"); + // create a layout of rings in HOMER for consumption of CME + ppeImgRc = layoutRingsForCME( pChipHomer, + l_chipFuncModel, + l_ringData, + (RingDebugMode_t)l_ringDebug, + l_iplPhase, + i_imgType, + i_pRingOverride ); + + if( ppeImgRc ) + { + FAPI_ERR("Failed to copy core Scan rings in HOMER rc 0x%08X", ppeImgRc ); + break; + } + + l_ringData.iv_ringBufSize = i_sizeBuf1; + ppeImgRc = getPpeScanRings( i_pImageIn, + PLAT_SGPE, + i_procTgt, + l_ringData, + i_imgType ); - l_ringData.iv_ringBufSize = i_sizeBuf1; - ppeImgRc = getPpeScanRings( i_pImageIn, - PLAT_SGPE, - i_procTgt, + if( ppeImgRc ) + { + FAPI_ERR( "failed to extract quad/ex scan rings" ); + break; + } + + // create a layout of rings in HOMER for consumption of SGPE + ppeImgRc = layoutRingsForSGPE( pChipHomer, + i_pRingOverride, + l_chipFuncModel, l_ringData, + (RingDebugMode_t)l_ringDebug, + l_iplPhase, + l_qpmrHdr, i_imgType ); - if( ppeImgRc ) - { - FAPI_ERR( "failed to extract quad/ex scan rings" ); - break; - } - - // create a layout of rings in HOMER for consumption of SGPE - ppeImgRc = layoutRingsForSGPE( pChipHomer, - i_pRingOverride, - l_chipFuncModel, - l_ringData, - (RingDebugMode_t)l_ringDebug, - l_iplPhase, - l_qpmrHdr, - i_imgType ); - - if( ppeImgRc ) - { - FAPI_ERR("Failed to copy quad/ex Scan rings in HOMER rc 0x%08X", ppeImgRc ); - break; - } + if( ppeImgRc ) + { + FAPI_ERR("Failed to copy quad/ex Scan rings in HOMER rc 0x%08X", ppeImgRc ); + break; + } - //Update CPMR Header with Scan Ring details - updateCpmrCmeRegion( pChipHomer ); + //Update CPMR Header with Scan Ring details + updateCpmrCmeRegion( pChipHomer ); - //Update QPMR Header area in HOMER - updateQpmrHeader( pChipHomer, l_qpmrHdr ); + //Update QPMR Header area in HOMER + updateQpmrHeader( pChipHomer, l_qpmrHdr ); - //update PPMR Header area in HOMER - updatePpmrHeader( pChipHomer, l_ppmrHdr ); + //update PPMR Header area in HOMER + updatePpmrHeader( pChipHomer, l_ppmrHdr ); - //Update L2 Epsilon SCOM Registers - retCode = populateEpsilonL2ScomReg( pChipHomer ); + //Update L2 Epsilon SCOM Registers + retCode = populateEpsilonL2ScomReg( pChipHomer ); - if( retCode ) - { - FAPI_ERR("populateEpsilonL2ScomReg failed" ); - break; - } + if( retCode ) + { + FAPI_ERR("populateEpsilonL2ScomReg failed" ); + break; + } - //Update L3 Epsilon SCOM Registers - retCode = populateEpsilonL3ScomReg( pChipHomer ); + //Update L3 Epsilon SCOM Registers + retCode = populateEpsilonL3ScomReg( pChipHomer ); - if( retCode ) - { - FAPI_ERR("populateEpsilonL3ScomReg failed" ); - break; - } + if( retCode ) + { + FAPI_ERR("populateEpsilonL3ScomReg failed" ); + break; + } - //populate HOMER with SCOM restore value of NCU RNG BAR SCOM Register - retCode = populateNcuRingBarScomReg( pChipHomer, i_procTgt ); + //populate HOMER with SCOM restore value of NCU RNG BAR SCOM Register + retCode = populateNcuRingBarScomReg( pChipHomer, i_procTgt ); - if( retCode ) - { - FAPI_ERR("populateNcuRingBarScomReg failed" ); - break; - } + if( retCode ) + { + FAPI_ERR("populateNcuRingBarScomReg failed" ); + break; + } - //validate SRAM Image Sizes of PPE's - uint32_t sramImgSize = 0; - ppeImgRc = validateSramImageSize( pChipHomer, sramImgSize ); - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), - fapi2::IMG_EXCEED_SRAM_SIZE( ) - .set_BAD_IMG_SIZE( sramImgSize ), - "SRAM Image Size Exceeded Max Allowed Size" ); + //validate SRAM Image Sizes of PPE's + uint32_t sramImgSize = 0; + ppeImgRc = validateSramImageSize( pChipHomer, sramImgSize ); + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), + fapi2::IMG_EXCEED_SRAM_SIZE( ) + .set_BAD_IMG_SIZE( sramImgSize ), + "SRAM Image Size Exceeded Max Allowed Size" ); - //Update CME/SGPE Flags in respective image header. - updateImageFlags( pChipHomer ); + //Update CME/SGPE Flags in respective image header. + updateImageFlags( pChipHomer ); - //Set the Fabric IDs - FAPI_TRY(setFabricIds( pChipHomer, i_procTgt ), - "Failed to set Fabric IDs"); + //Set the Fabric IDs + FAPI_TRY(setFabricIds( pChipHomer, i_procTgt ), + "Failed to set Fabric IDs"); - //Update the attributes storing PGPE and SGPE's boot copier offset. - retCode = updateGpeAttributes( pChipHomer, i_procTgt ); + //Update the attributes storing PGPE and SGPE's boot copier offset. + retCode = updateGpeAttributes( pChipHomer, i_procTgt ); - if( retCode ) - { - FAPI_ERR("Failed to update SGPE/PGPE IVPR attributes"); - break; - } + if( retCode ) + { + FAPI_ERR("Failed to update SGPE/PGPE IVPR attributes"); + break; } - while(0); + } + while(0); - FAPI_IMP("Exit p9_hcode_image_build" ); + FAPI_IMP("Exit p9_hcode_image_build" ); - fapi_try_exit: - return retCode; - } +fapi_try_exit: + return retCode; +} - } //namespace p9_hcodeImageBuild ends +} //namespace p9_hcodeImageBuild ends }// extern "C" diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C index f1d656a8b..433ae1ad2 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C @@ -188,7 +188,7 @@ RingBucket::RingBucket( PlatId i_plat, uint8_t* i_pRingStart, RingDebugMode_t i_ { ex_l3_fure_1, 0, 0 }, }; - RingProfile l_quadSpecRings[TEMP_MAX_QUAD_SPEC_RINGS * MAX_CACHE_CHIPLET] = + RingProfile l_quadSpecRings[TEMP_MAX_QUAD_SPEC_RINGS * MAX_QUADS_PER_CHIP] = { { eq_repr, 0x10 }, { ex_l3_repr, 0x10 }, @@ -257,7 +257,7 @@ RingBucket::RingBucket( PlatId i_plat, uint8_t* i_pRingStart, RingDebugMode_t i_ iv_cmnRingMap[ringIndex] = l_quadCmnRings[ringIndex]; } - for( ringIndex = 0; ringIndex < ( EQ::g_eqData.iv_num_instance_rings_scan_addrs * MAX_CACHE_CHIPLET ); + for( ringIndex = 0; ringIndex < ( EQ::g_eqData.iv_num_instance_rings_scan_addrs * MAX_QUADS_PER_CHIP ); ringIndex++ ) { iv_instRingMap[ringIndex] = l_quadSpecRings[ringIndex]; diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C index ebf7da61b..cdebc2723 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C @@ -325,7 +325,8 @@ StopReturnCode_t lookUpSprInImage( uint32_t* i_pThreadSectLoc, void** io_pSprEntryLoc ) { StopReturnCode_t l_rc = STOP_SAVE_FAIL; - uint32_t temp = i_isCoreReg ? CORE_SPR_SECTN_SIZE : THREAD_SECTN_SIZE; + uint32_t temp = i_isCoreReg ? uint32_t(CORE_RESTORE_CORE_AREA_SIZE) : + uint32_t(CORE_RESTORE_THREAD_AREA_SIZE); uint32_t* i_threadSectEnd = i_pThreadSectLoc + temp; uint32_t bctr_inst = SWIZZLE_4_BYTE(BLR_INST); *io_pSprEntryLoc = NULL; @@ -967,7 +968,7 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, if( P9_STOP_SECTION_CORE_SCOM == i_section ) { - memset( pScomEntry, 0x00, SCOM_SIZE_PER_CORE ); + memset( pScomEntry, 0x00, CORE_SCOM_RESTORE_SIZE_PER_CORE ); } break; diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H index e9cfa29a7..8a5c2b4ed 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H @@ -39,7 +39,7 @@ #include <endian.h> #endif -#include "p9_stop_section_defines.H" +#include "p9_hcd_memmap_base.H" #ifdef __FAPI_2_ #include <fapi2.H> @@ -52,6 +52,12 @@ namespace stopImageSection { #endif +enum +{ + MAX_SPR_RESTORE_INST = 0x08, + SIZE_PER_SPR_RESTORE_INST = ((4 * sizeof(uint8_t)) / sizeof(uint32_t)), +}; + typedef struct { uint32_t scomEntryHeader; @@ -64,8 +70,8 @@ typedef struct */ typedef struct { - uint8_t threadArea[THREAD_AREA_SIZE]; - uint8_t coreArea[CORE_SPR_SECTN_SIZE]; + uint8_t threadArea[CORE_RESTORE_THREAD_AREA_SIZE]; + uint8_t coreArea[CORE_RESTORE_CORE_AREA_SIZE]; } SprRestoreArea_t; /** @@ -76,10 +82,10 @@ typedef struct typedef struct { uint8_t occ_host_sgpe_area[ TWO_MB ]; // CPU restore area starts at an offset of 2MB from chip HOMER - uint8_t interrruptHandler[INTERRUPT_HANDLER_SIZE]; + uint8_t interrruptHandler[SELF_RESTORE_INT_SIZE]; uint8_t threadLauncher[THREAD_LAUNCHER_SIZE]; - SprRestoreArea_t coreThreadRestore[MAX_CORE_ID_SUPPORTED + 1][MAX_THREAD_ID_SUPPORTED + 1]; - uint8_t reserve[(ONE_KB * ONE_KB) - SPR_RESTORE_PER_CHIP]; + SprRestoreArea_t coreThreadRestore[MAX_CORES_PER_CHIP][MAX_THREADS_PER_CORE]; + uint8_t reserve[(ONE_KB * ONE_KB) - SELF_RESTORE_SIZE_TOTAL]; } HomerSection_t; /** @@ -121,15 +127,15 @@ enum #define CORE_ID_SCOM_START(io_image,\ i_chipletId) \ -((ScomEntry_t*)(((uint8_t*)(io_image))+ CORE_SCOM_SECTN_START +\ +((ScomEntry_t*)(((uint8_t*)(io_image)) + CORE_SCOM_RESTORE_HOMER_OFFSET +\ ((i_chipletId - CORE_CHIPLET_ID_MIN) * \ - SCOM_SIZE_PER_CORE))); + CORE_SCOM_RESTORE_SIZE_PER_CORE))); #define CACHE_SECTN_START(io_image,\ i_chipletId) \ -((StopCacheSection_t *)(((uint8_t *)(io_image))+CACHE_SCOM_SECTN_START \ - + ( i_chipletId - CACHE_CHIPLET_ID_MIN ) * \ - SCOM_SIZE_PER_CACHE_CHIPLET )); +((StopCacheSection_t *)(((uint8_t *)(io_image)) + QUAD_SCOM_RESTORE_HOMER_OFFSET +\ + ((i_chipletId - CACHE_CHIPLET_ID_MIN) * \ + QUAD_SCOM_RESTORE_SIZE_PER_QUAD))); #ifdef __cplusplus } // extern "C" diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H deleted file mode 100755 index d660e5fb7..000000000 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H +++ /dev/null @@ -1,106 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file p9_stop_section_defines.H -/// @brief defines all constants associated with STOP image layout. -/// -// *HWP HW Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> -// *HWP Team : PM -// *HWP Level : 2 -// *HWP Consumed by : HB:HYP - -#ifndef _STOP_SECTION_DEFINES_H -#define _STOP_SECTION_DEFINES_H - -#ifdef __cplusplus -namespace stopImageSection -{ -#endif - -//basic constants -enum -{ -ONE_KB = 1024, -ONE_MB = ONE_KB * ONE_KB, -TWO_MB = 2 * ONE_MB, -MAX_CORE_SCOM_ENTRIES = 15, -MAX_EQ_SCOM_ENTRIES = 15, -MAX_L2_SCOM_ENTRIES = 16, -MAX_L3_SCOM_ENTRIES = 16, -MAX_CORE_ID_SUPPORTED = 23, -MAX_THREAD_ID_SUPPORTED = 3, -MAX_CACHE_SECTN_SIZE_PER_CHIPLET = - MAX_EQ_SCOM_ENTRIES + MAX_L2_SCOM_ENTRIES + MAX_L3_SCOM_ENTRIES, - -// start offset for SPR register restore, core scom or cache scom register -// restore regions in homer image. -CORE_SCOM_SECTN_START = ( TWO_MB + ( 256 * ONE_KB )), //offset from start of chip HOMER -CACHE_SCOM_SECTN_START = ( ONE_MB + ( 128 * ONE_KB )), // start of cache section - -//constants in HOMER's header area. -FUSED_MODE = 0xBB, -NONFUSED_MODE = 0xAA, -CPMR_MAGIC_WORD = 0x43504d525f312e30, -CACHE_CHIPLET_ID_MIN = 0x10, -CACHE_CHIPLET_ID_MAX = 0x15, -CORE_CHIPLET_ID_MIN = 0x20, -CORE_CHIPLET_ID_MAX = 0x37, -MAX_SPR_RESTORE_INST = 0x08, -SIZE_PER_SPR_RESTORE_INST = ((4 * sizeof(uint8_t)) / sizeof(uint32_t)), -}; - -// all section sizes below are in bytes -enum -{ -SCOM_ENTRY_SIZE = 16, -INTERRUPT_HANDLER_SIZE = 8 * ONE_KB, -THREAD_LAUNCHER_SIZE = 256, -THREAD_RESTORE_SECTN = 192, -THREAD_COMPLETION = 64, -THREAD_AREA_SIZE = ONE_KB, -THREAD_SECTN_SIZE = THREAD_RESTORE_SECTN + THREAD_COMPLETION, -CORE_SPR_SECTN_SIZE = ONE_KB, -L2_AREA = (SCOM_ENTRY_SIZE * MAX_L2_SCOM_ENTRIES), -L3_AREA = (SCOM_ENTRY_SIZE * MAX_L2_SCOM_ENTRIES ), -EQ_AREA = SCOM_ENTRY_SIZE * MAX_EQ_SCOM_ENTRIES, -MAX_SIZE_PER_CORE = 8 * ONE_KB, -SPR_RESTORE_PER_CHIP = ( MAX_SIZE_PER_CORE * - ( MAX_CORE_ID_SUPPORTED + 1)) + - ( INTERRUPT_HANDLER_SIZE + THREAD_LAUNCHER_SIZE), -SCOM_SIZE_PER_CORE = ( MAX_CORE_SCOM_ENTRIES + 1 ) * SCOM_ENTRY_SIZE, -SCOM_SIZE_PER_CHIP = SCOM_SIZE_PER_CORE * ( MAX_CORE_ID_SUPPORTED + 1), -SCOM_SIZE_PER_CACHE_CHIPLET = L2_AREA + L3_AREA + EQ_AREA - + SCOM_ENTRY_SIZE, -//size in byte ends -}; - -#ifdef __cplusplus -}//stopImageSection ends -#endif //__cplusplus - -#endif - diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C index 7fdc1deee..9e9874ad9 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C @@ -65,7 +65,7 @@ StopReturnCode_t isFusedMode( void* const i_pImage, bool* o_fusedMode ) HomerSection_t* pHomerDesc = ( HomerSection_t* ) i_pImage; HomerImgDesc_t* pHomer = (HomerImgDesc_t*)( pHomerDesc->interrruptHandler ); - if( SWIZZLE_8_BYTE(CPMR_MAGIC_WORD) != pHomer->cpmrMagicWord ) + if( SWIZZLE_8_BYTE(CPMR_MAGIC_NUMBER) != pHomer->cpmrMagicWord ) { MY_ERR("corrupt or invalid HOMER image location 0x%016llx", SWIZZLE_8_BYTE(pHomer->cpmrMagicWord) ); @@ -73,13 +73,13 @@ StopReturnCode_t isFusedMode( void* const i_pImage, bool* o_fusedMode ) break; } - if( (uint8_t) FUSED_MODE == pHomer->fusedModeStatus ) + if( (uint8_t) FUSED_CORE_MODE == pHomer->fusedModeStatus ) { *o_fusedMode = true; break; } - if( (uint8_t) NONFUSED_MODE == pHomer->fusedModeStatus ) + if( (uint8_t) NONFUSED_CORE_MODE == pHomer->fusedModeStatus ) { break; } diff --git a/src/usr/isteps/pm/pm_common.C b/src/usr/isteps/pm/pm_common.C index b82f6faae..ea829193d 100644 --- a/src/usr/isteps/pm/pm_common.C +++ b/src/usr/isteps/pm/pm_common.C @@ -409,7 +409,7 @@ namespace HBPM pQpmrHeader->bootLoaderLength); sgpeHeader_t* pSgpeImageHeader = (sgpeHeader_t*) - & pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT]; + & pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "SGPE header -- Date:0x%08X, Version:0x%08X, " "Image offset:0x%08X, Image length:0x%08X", @@ -446,7 +446,7 @@ namespace HBPM PpmrHeader_t* pPpmrHeader = (PpmrHeader_t *)pChipHomer->ppmrRegion.ppmrHeader; PgpeHeader_t* pPgpeHeader = (PgpeHeader_t*) - (&(pChipHomer->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR])); + (&(pChipHomer->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR_SIZE])); TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "PGPE header -- Date:0x%08X, Version:0x%08X, " "Hcode offset:0x%08X, Hcode length:0x%08X", |
