Change SEQ timings, SEQ ODT, WC config and DQS polarity

  SEQ timings make use of new timing functions
  SEQ ODT changes VBU VPD, makes sure ZZ VPD is correct
  WC Config makes cal big step 8/128th
  Add Monza DQS polarity workarounds

Change-Id: I1b2059188616674f885253492cba7350d268214f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29219
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29221
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

10 files changed, 661 insertions, 100 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H
index 3939e7dc8..82a481c0b 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H
@@ -39,6 +39,7 @@
 #include <fapi2.H>
 #include <lib/utils/find.H>
 #include <lib/utils/conversions.H>
+
 namespace mss
 {
 
@@ -168,7 +169,7 @@ fapi2::ReturnCode calc_trfc_dlr( const uint8_t i_refresh_mode,
                                  uint64_t& o_trfc_in_ps );
 
 ///
-/// @brief DLL locking time
+/// @brief DLL locking time *in clocks*
 /// @tparam T the fapi2::TargetType of i_target
 /// @tparam OT the type of the output location
 /// @param[in] i_target a target for attributes
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
index d54ba3a28..b9d39b945 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
@@ -45,6 +45,8 @@
 #include <lib/phy/apb.H>
 #include <lib/phy/adr32s.H>
 #include <lib/phy/adr.H>
+#include <lib/phy/seq.H>
+#include <lib/workarounds/dp16_workarounds.H>
 
 #include <lib/utils/bit_count.H>
 #include <lib/utils/find.H>
@@ -616,6 +618,9 @@ fapi2::ReturnCode phy_scominit(const fapi2::Target<TARGET_TYPE_MCBIST>& i_target
         // Read Control reset
         FAPI_TRY( mss::rc::reset(p) );
 
+        // Reset the SEQ block
+        FAPI_TRY( mss::seq::reset(p) );
+
         // Reset the AC Boost controls from the values in VPD
         FAPI_TRY( mss::dp16::reset_ac_boost_cntl(p) );
 
@@ -629,8 +634,13 @@ fapi2::ReturnCode phy_scominit(const fapi2::Target<TARGET_TYPE_MCBIST>& i_target
         FAPI_TRY( mss::adr32s::reset_tsys_adr(p) );
         FAPI_TRY( mss::dp16::reset_tsys_data(p) );
 
-        //resets all of the IO impedances
+        // Resets all of the IO impedances
         FAPI_TRY( mss::reset_io_impedances(p) );
+
+        //
+        // Workarounds
+        //
+        FAPI_TRY( mss::workarounds::dp16::dqs_polarity(p) );
     }
 
 fapi_try_exit:
@@ -773,25 +783,6 @@ fapi2::ReturnCode setup_cal_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA>&
 }
 
 ///
-/// @brief Setup seq_config0
-/// @param[in] i_target the MCA target associated with this cal setup
-/// @return FAPI2_RC_SUCCESS iff setup was successful
-///
-template<>
-fapi2::ReturnCode reset_seq_config0( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target )
-{
-    fapi2::buffer<uint64_t> l_data;
-
-    // ATTR_VPD_DRAM_2N_MODE_ENABLED  49, 0b1, (def_2N_mode);       # enable 2 cycle addr mode BRS
-
-    FAPI_INF("seq_config0 0x%llx", l_data);
-    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_CONFIG0_P0, l_data) );
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-///
 /// @brief Setup odt_wr/rd_config
 /// @param[in] i_target the MCA target associated with this cal setup
 /// @return FAPI2_RC_SUCCESS iff setup was successful
@@ -931,29 +922,6 @@ fapi_try_exit:
 }
 
 ///
-/// @brief Setup seq_rd_wr_data
-/// @param[in] i_target the MCA target associated with this cal setup
-/// @return FAPI2_RC_SUCCESS iff setup was successful
-///
-template<>
-fapi2::ReturnCode reset_seq_rd_wr_data( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target )
-{
-    // MPR_PATTERN_BIT of 0F0F0F0F pattern
-    static const uint64_t MPR_PATTERN = 0x5555;
-    fapi2::buffer<uint64_t> l_data;
-
-    l_data.insertFromRight<MCA_DDRPHY_SEQ_RD_WR_DATA0_P0_DATA_REG0,
-                           MCA_DDRPHY_SEQ_RD_WR_DATA0_P0_DATA_REG0_LEN>(MPR_PATTERN);
-
-    FAPI_INF("seq_rd_wr 0x%llx", l_data);
-    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_RD_WR_DATA0_P0, l_data) );
-    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_RD_WR_DATA1_P0, l_data) );
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-///
 /// @brief Start the DLL calibration, monitor for fails.
 /// @param[in] i_target the target associated with this DLL cal
 /// @return FAPI2_RC_SUCCESS iff setup was successful
@@ -1061,6 +1029,10 @@ fapi2::ReturnCode flush_output_drivers( const fapi2::Target<fapi2::TARGET_TYPE_M
     const auto& l_force_atest_reg = adr32sTraits<TARGET_TYPE_MCA>::OUTPUT_DRIVER_REG;
     const auto& l_data_dir_reg = dp16Traits<TARGET_TYPE_MCA>::DATA_BIT_DIR1;
 
+    // Per PHY review 8/16, setup the DATA_BIT_DIR1 with advance_ping_pong and delay_ping_pong_half
+    mss::dp16::set_adv_pp(l_dp16_data, mss::HIGH);
+    mss::dp16::set_delay_pp_half(l_dp16_data, mss::HIGH);
+
     // 8. Set FLUSH=1 and INIT_IO=1 in the DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL and DDRPHY_DP16_DATA_BIT_DIR1 register
     {
         mss::adr32s::set_output_flush( l_adr_data, mss::HIGH );
@@ -1069,7 +1041,7 @@ fapi2::ReturnCode flush_output_drivers( const fapi2::Target<fapi2::TARGET_TYPE_M
 
         mss::dp16::set_output_flush( l_dp16_data, mss::HIGH );
         mss::dp16::set_init_io( l_dp16_data, mss::HIGH);
-        FAPI_TRY( mss::scom_blastah(l_ports, l_data_dir_reg, l_adr_data) );
+        FAPI_TRY( mss::scom_blastah(l_ports, l_data_dir_reg, l_dp16_data) );
     }
 
     // 9. Wait at least 32 dphy_gckn clock cycles.
@@ -1084,7 +1056,7 @@ fapi2::ReturnCode flush_output_drivers( const fapi2::Target<fapi2::TARGET_TYPE_M
 
         mss::dp16::set_output_flush( l_dp16_data, mss::LOW );
         mss::dp16::set_init_io( l_dp16_data, mss::LOW);
-        FAPI_TRY( mss::scom_blastah(l_ports, l_data_dir_reg, l_adr_data) );
+        FAPI_TRY( mss::scom_blastah(l_ports, l_data_dir_reg, l_dp16_data) );
     }
 
 fapi_try_exit:
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
index 4ff039e1b..075db9781 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
@@ -149,25 +149,6 @@ fapi2::ReturnCode setup_cal_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA>&
                                     const uint64_t i_rank,
                                     const fapi2::buffer<uint16_t> i_cal_steps_enabled);
 
-
-///
-/// @brief Setup seq_config0
-/// @tparam T the target type of the MCA/MBA
-/// @param[in] i_target the target associated with this cal setup
-/// @return FAPI2_RC_SUCCESS iff setup was successful
-///
-template< fapi2::TargetType T >
-fapi2::ReturnCode reset_seq_config0( const fapi2::Target<T>& i_target );
-
-///
-/// @brief Setup seq_config0
-/// @param[in] i_target the MCA target associated with this cal setup
-/// @return FAPI2_RC_SUCCESS iff setup was successful
-///
-template<>
-fapi2::ReturnCode reset_seq_config0( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
-
-
 ///
 /// @brief Setup odt_wr/rd_config
 /// @tparam T the target type of the MCA/MBA
@@ -186,23 +167,6 @@ template<>
 fapi2::ReturnCode reset_odt_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
 
 ///
-/// @brief Setup seq_rd_wr_data
-/// @tparam T the target type of the MCA/MBA
-/// @param[in] i_target the target associated with this cal setup
-/// @return FAPI2_RC_SUCCESS iff setup was successful
-///
-template< fapi2::TargetType T >
-fapi2::ReturnCode reset_seq_rd_wr_data( const fapi2::Target<T>& i_target );
-
-///
-/// @brief Setup seq_rd_wr_data
-/// @param[in] i_target the MCA target associated with this cal setup
-/// @return FAPI2_RC_SUCCESS iff setup was successful
-///
-template<>
-fapi2::ReturnCode reset_seq_rd_wr_data( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
-
-///
 /// @brief Perform the DLL calibration
 /// @tparam T the target type of the MCBIST
 /// @param[in] i_target the target associated with this DLL cal
@@ -238,6 +202,15 @@ fapi2::ReturnCode flush_output_drivers( const fapi2::Target<fapi2::TARGET_TYPE_M
 
 ///
 /// @brief Setup seq_rd_wr_data
+/// @tparam T the target type of the MCA/MBA
+/// @param[in] i_target the target associated with this cal setup
+/// @return FAPI2_RC_SUCCESS iff setup was successful
+///
+template< fapi2::TargetType T >
+fapi2::ReturnCode reset_seq_rd_wr_data( const fapi2::Target<T>& i_target );
+
+///
+/// @brief Setup seq_rd_wr_data
 /// @param[in] i_target the MCA target associated with this cal setup
 /// @return FAPI2_RC_SUCCESS iff setup was successful
 ///
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
index 79050b6d6..f6f2ea3b4 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
@@ -158,6 +158,8 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA>
             DLL_CNTL_INIT_RXDLL_CAL_RESET = MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_RESET,
             FLUSH = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_FLUSH,
             INIT_IO = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_INIT_IO,
+            ADV_PP = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_ADVANCE_PING_PONG,
+            DELAY_PP_HALF = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_DELAY_PING_PONG_HALF,
 
             TSYS_DATA = MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS,
             TSYS_DATA_LEN = MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS_LEN,
@@ -546,7 +548,7 @@ fapi2::ReturnCode reset_ctle_cntl( const fapi2::Target<T>& i_target );
 /// @brief Set the DLL cal reset (begins DLL cal operations)
 /// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
 /// @tparam TT traits type defaults to dp16Traits<T>
-/// @param[in] o_data the value of the register
+/// @param[out] o_data the value of the register
 /// @param[in] i_state mss::LOW or mss::HIGH representing the state of the bit
 /// @note Default state is 'low' as writing a 0 forces the cal to begin.
 ///
@@ -606,9 +608,8 @@ fapi_try_exit:
 /// @brief Set the output flush
 /// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
 /// @tparam TT traits type defaults to dp16Traits<T>
-/// @param[in] o_data the value of the register
+/// @param[out] o_data the value of the register
 /// @param[in] i_state mss::LOW or mss::HIGH representing the state of the bit
-/// @note Default state is 'low' as writing a 0 forces the cal to begin.
 ///
 template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = dp16Traits<T> >
 inline void set_output_flush( fapi2::buffer<uint64_t>& o_data, const states i_state )
@@ -621,9 +622,8 @@ inline void set_output_flush( fapi2::buffer<uint64_t>& o_data, const states i_st
 /// @brief Set the init io state
 /// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
 /// @tparam TT traits type defaults to dp16Traits<T>
-/// @param[in] o_data the value of the register
+/// @param[out] o_data the value of the register
 /// @param[in] i_state mss::LOW or mss::HIGH representing the state of the bit
-/// @note Default state is 'low' as writing a 0 forces the cal to begin.
 ///
 template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = dp16Traits<T> >
 inline void set_init_io( fapi2::buffer<uint64_t>& o_data, const states i_state )
@@ -632,6 +632,34 @@ inline void set_init_io( fapi2::buffer<uint64_t>& o_data, const states i_state )
     o_data.writeBit<TT::INIT_IO>(i_state);
 }
 
+///
+/// @brief Set advance_ping_pong
+/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[out] o_data the value of the register
+/// @param[in] i_state mss::LOW or mss::HIGH representing the state of the bit
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = dp16Traits<T> >
+inline void set_adv_pp( fapi2::buffer<uint64_t>& o_data, const states i_state )
+{
+    FAPI_INF("set_adv_pp %s", (i_state == mss::LOW ? "low" : "high"));
+    o_data.writeBit<TT::ADV_PP>(i_state);
+}
+
+///
+/// @brief Set delay ping pong half
+/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[out] o_data the value of the register
+/// @param[in] i_state mss::LOW or mss::HIGH representing the state of the bit
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = dp16Traits<T> >
+inline void set_delay_pp_half( fapi2::buffer<uint64_t>& o_data, const states i_state )
+{
+    FAPI_INF("set_delay_pp_half %s", (i_state == mss::LOW ? "low" : "high"));
+    o_data.writeBit<TT::DELAY_PP_HALF>(i_state);
+}
+
 
 
 ///
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C
index 1fb3214c1..415a54cef 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C
@@ -22,3 +22,158 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file seq.C
+/// @brief Subroutines for the PHY SEQ registers
+///
+// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 2
+// *HWP Consumed by: FSP:HB
+
+#include <fapi2.H>
+#include <lib/phy/seq.H>
+#include <lib/utils/scom.H>
+#include <lib/utils/c_str.H>
+#include <lib/utils/bit_count.H>
+#include <lib/eff_config/timing.H>
+
+using fapi2::TARGET_TYPE_MCA;
+using fapi2::TARGET_TYPE_DIMM;
+
+namespace mss
+{
+
+namespace seq
+{
+
+///
+/// @brief PHY SEQ register exponent helper
+/// PHY SEQ fields is used as exponent of 2, to calculate the number of MEMINTCLKO clock cycles.
+/// For example, if TMOD_CYCLES[0:3] = 5, the internal timers use the value 2^5 = 32 MEMINTCLKO
+/// clock cycles. The maximum value per nibble is ‘A’h. This helper takes a calculated value and returns
+/// the 'best' exponent.
+/// @param[in] i_value a value for which to make an exponent
+/// @return uint64_t right-aligned value to stick in the field
+///
+uint64_t exp_helper( const uint64_t i_value )
+{
+    // PHY exponents don't make much sense above this value so we short circuit if possible.
+    constexpr uint64_t MAX_EXP = 0xA;
+
+    if (i_value >= (1 << MAX_EXP))
+    {
+        return 0xA;
+    }
+
+    // If the user passes in 0, let it past.
+    if (i_value == 0)
+    {
+        return 0;
+    }
+
+    // Find the first bit set. The subtraction from 63 switches from a left-count to a right-count (e.g., 0 (left most
+    // bit) is really bit 63 if you start on the right.)
+    const uint64_t l_first_bit = 63 - first_bit_set(i_value);
+
+    // If the input is greater than 2^first bit, add one to the first_bit so 2^first_bit >= input
+    // (round up)
+    return l_first_bit + (uint64_t(1 << l_first_bit) < i_value ? 1 : 0);
+}
+
+
+///
+/// @brief reset SEQ_TIMING0
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template<>
+fapi2::ReturnCode reset_timing0( const fapi2::Target<TARGET_TYPE_MCA>& i_target )
+{
+    typedef seqTraits<TARGET_TYPE_MCA> TT;
+    fapi2::buffer<uint64_t> l_data;
+
+    // Table 5-324. SEQ Memory Timing Parameter 0 Register Bit Definition
+    // TMOD_CYCLES max(tMRD, tMOD)
+    // TRCD_CYCLES tRCD
+    // TRP_CYCLES  tRP
+    // TRFC_CYCLES tRFC
+
+    uint64_t l_tmod_cycles = 0;
+    uint8_t l_trcd = 0;
+    uint8_t l_trp = 0;
+    uint16_t l_trfc_max = 0;
+
+    l_tmod_cycles = exp_helper( std::max(mss::tmrd(), mss::tmod(i_target)) );
+    l_data.insertFromRight<TT::TMOD_CYCLES, TT::TMOD_CYCLES_LEN>(l_tmod_cycles);
+
+    FAPI_TRY( mss::eff_dram_trcd(i_target, l_trcd) );
+    l_data.insertFromRight<TT::TRCD_CYCLES, TT::TRCD_CYCLES_LEN>( exp_helper(l_trcd) );
+
+    FAPI_TRY( mss::eff_dram_trp(i_target, l_trp) );
+    l_data.insertFromRight<TT::TRP_CYCLES, TT::TRP_CYCLES_LEN>( exp_helper(l_trp) );
+
+    // It's not really clear what to put here. We can have DIMM with different tRFC as they
+    // don't have to be the same (3DS v. SPD for example.) So we'll take the maximum trfc we
+    // find on the DIMM connected to this port.
+    for (const auto& d : mss::find_targets<TARGET_TYPE_DIMM>(i_target))
+    {
+        uint16_t l_trfc = 0;
+        FAPI_TRY( mss::trfc(d, l_trfc) );
+        l_trfc_max = std::max(l_trfc_max, l_trfc);
+    }
+
+    l_data.insertFromRight<TT::TRFC_CYCLES, TT::TRFC_CYCLES_LEN>( exp_helper(l_trfc_max) );
+
+    FAPI_TRY( mss::putScom(i_target, TT::SEQ_TIMING0_REG, l_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+
+///
+/// @brief reset SEQ_TIMING1
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template<>
+fapi2::ReturnCode reset_timing1( const fapi2::Target<TARGET_TYPE_MCA>& i_target )
+{
+    typedef seqTraits<TARGET_TYPE_MCA> TT;
+    fapi2::buffer<uint64_t> l_data;
+
+    // Table 5-325. SEQ Memory Timing Parameter 1 Register
+    // TZQINIT_CYCLES  max(tZQINIT,tZQOPER)
+    // TZQCS_CYCLES  tZQCS
+    // TWLDQSEN_CYCLES tWLDQSEN
+    // TWRMRD_CYCLES tWLMRD
+
+    uint64_t l_tzqint = std::max( mss::tzqinit(), mss::tzqoper() );
+    l_data.insertFromRight<TT::TZQINIT_CYCLES, TT::TZQINIT_CYCLES_LEN>( exp_helper(l_tzqint) );
+    l_data.insertFromRight<TT::TZQCS_CYCLES, TT::TZQCS_CYCLES_LEN>( exp_helper(mss::tzqcs()) );
+    l_data.insertFromRight<TT::TWLDQSEN_CYCLES, TT::TWLDQSEN_CYCLES_LEN>( exp_helper(mss::twldqsen()) );
+    l_data.insertFromRight<TT::TWRMRD_CYCLES, TT::TWRMRD_CYCLES_LEN>( exp_helper(mss::twlmrd()) );
+
+    return mss::putScom(i_target, TT::SEQ_TIMING1_REG, l_data);
+}
+
+
+///
+/// @brief reset SEQ_TIMING2
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template<>
+fapi2::ReturnCode reset_timing2( const fapi2::Target<TARGET_TYPE_MCA>& i_target )
+{
+    // NO-OP right now.
+    return fapi2::FAPI2_RC_SUCCESS;
+}
+
+
+} // close namespace seq
+} // close namespace mss
+
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H
index 1ab83efe9..4985c6557 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H
@@ -22,3 +22,332 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file seq.H
+/// @brief Subroutines for the PHY sequencer registers
+///
+// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 2
+// *HWP Consumed by: FSP:HB
+
+#ifndef _MSS_SEQ_H_
+#define _MSS_SEQ_H_
+
+#include <fapi2.H>
+#include <p9_mc_scom_addresses.H>
+#include <p9_mc_scom_addresses_fld.H>
+#include <lib/utils/scom.H>
+
+namespace mss
+{
+
+// I have a dream that the PHY code can be shared among controllers. So, I drive the
+// engine from a set of traits. This might be folly. Allow me to dream. BRS
+
+///
+/// @class seqTraits
+/// @brief a collection of traits associated with the PHY SEQ interface
+/// @tparam T fapi2::TargetType representing the PHY
+///
+template< fapi2::TargetType T >
+class seqTraits;
+
+///
+/// @class seqTraits
+/// @brief a collection of traits associated with the Centaur PHY SEQ interface
+///
+template<>
+class seqTraits<fapi2::TARGET_TYPE_MBA>
+{
+};
+
+///
+/// @class seqTraits
+/// @brief a collection of traits associated with the Nimbus PHY SEQ
+///
+template<>
+class seqTraits<fapi2::TARGET_TYPE_MCA>
+{
+    public:
+        // MCA SEQ control registers - must be 64 bits.
+        static const uint64_t SEQ_CONFIG0_REG = MCA_DDRPHY_SEQ_CONFIG0_P0;
+        static const uint64_t SEQ_ERROR0_REG = MCA_DDRPHY_SEQ_ERROR_STATUS0_P0;
+        static const uint64_t SEQ_TIMING0_REG = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0;
+        static const uint64_t SEQ_TIMING1_REG = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0;
+        static const uint64_t SEQ_TIMING2_REG = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0;
+        static const uint64_t SEQ_RDWR_DATA0 = MCA_DDRPHY_SEQ_RD_WR_DATA0_P0;
+        static const uint64_t SEQ_RDWR_DATA1 = MCA_DDRPHY_SEQ_RD_WR_DATA1_P0;
+
+        // Fields, can be any size.
+        enum
+        {
+            MPR_PATTERN = MCA_DDRPHY_SEQ_RD_WR_DATA0_P0_DATA_REG0,
+            MPR_PATTERN_LEN = MCA_DDRPHY_SEQ_RD_WR_DATA0_P0_DATA_REG0_LEN,
+
+            TMOD_CYCLES = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TMOD_CYCLES,
+            TMOD_CYCLES_LEN = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TMOD_CYCLES_LEN,
+            TRCD_CYCLES = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRCD_CYCLES,
+            TRCD_CYCLES_LEN = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRCD_CYCLES_LEN,
+            TRP_CYCLES = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRP_CYCLES,
+            TRP_CYCLES_LEN = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRP_CYCLES_LEN,
+            TRFC_CYCLES = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRFC_CYCLES,
+            TRFC_CYCLES_LEN = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRFC_CYCLES_LEN,
+            TZQINIT_CYCLES = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQINIT_CYCLES,
+            TZQINIT_CYCLES_LEN = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQINIT_CYCLES_LEN,
+            TZQCS_CYCLES = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQCS_CYCLES,
+            TZQCS_CYCLES_LEN = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQCS_CYCLES_LEN,
+            TWLDQSEN_CYCLES = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWLDQSEN_CYCLES,
+            TWLDQSEN_CYCLES_LEN = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWLDQSEN_CYCLES_LEN,
+            TWRMRD_CYCLES = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWRMRD_CYCLES,
+            TWRMRD_CYCLES_LEN = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWRMRD_CYCLES_LEN,
+            TODTLON_OFF_CYCLES = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TODTLON_OFF_CYCLES,
+            TODTLON_OFF_CYCLES_LEN = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TODTLON_OFF_CYCLES_LEN,
+            TRC_CYCLES = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TRC_CYCLES,
+            TRC_CYCLES_LEN = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TRC_CYCLES_LEN,
+            TMRSC_CYCLES = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TMRSC_CYCLES,
+            TMRSC_CYCLES_LEN = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TMRSC_CYCLES_LEN,
+        };
+
+};
+
+namespace seq
+{
+
+///
+/// @brief PHY SEQ register exponent helper
+/// PHY SEQ fields is used as exponent of 2, to calculate the number of MEMINTCLKO clock cycles.
+/// For example, if TMOD_CYCLES[0:3] = 5, the internal timers use the value 2^5 = 32 MEMINTCLKO
+/// clock cycles. The maximum value per nibble is ‘A’h. This helper takes a calculated value and returns
+/// the 'best' exponent.
+/// @param[in] i_value a value for which to make an exponent
+/// @return uint64_t right-aligned value to stick in te field
+///
+uint64_t exp_helper( const uint64_t i_value );
+
+///
+/// @brief Read SEQ_CONFIG0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+inline fapi2::ReturnCode read_config0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
+{
+    FAPI_TRY( mss::getScom(i_target, TT::SEQ_CONFIG0_REG, o_data) );
+    FAPI_DBG("seq_config0: 0x%016lx", o_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Write SEQ_CONFIG0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+inline fapi2::ReturnCode write_config0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
+{
+    FAPI_DBG("seq_config0: 0x%016lx", i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::SEQ_CONFIG0_REG, i_data) );
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Read SEQ_ERROR_STATUS0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+inline fapi2::ReturnCode read_error_status0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
+{
+    FAPI_TRY( mss::getScom(i_target, TT::SEQ_ERROR0_REG, o_data) );
+    FAPI_DBG("seq_error_status0: 0x%016lx", o_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+// SEQ_ERROR_STATUS0 is read-only
+
+///
+/// @brief Read SEQ_MEM_TIMING_PARAM0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+inline fapi2::ReturnCode read_timing0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
+{
+    FAPI_TRY( mss::getScom(i_target, TT::SEQ_TIMING0_REG, o_data) );
+    FAPI_DBG("seq_timing0: 0x%016lx", o_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Write SEQ_MEM_TIMING_PARAM0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+inline fapi2::ReturnCode write_timing0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
+{
+    FAPI_DBG("seq_timing0: 0x%016lx", i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::SEQ_TIMING0_REG, i_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Read SEQ_MEM_TIMING_PARAM1
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+inline fapi2::ReturnCode read_timing1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
+{
+    FAPI_TRY( mss::getScom(i_target, TT::SEQ_TIMING1_REG, o_data) );
+    FAPI_DBG("seq_timing1: 0x%016lx", o_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Write SEQ_MEM_TIMING_PARAM1
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+inline fapi2::ReturnCode write_timing1( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
+{
+    FAPI_DBG("seq_timing1: 0x%016lx", i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::SEQ_TIMING1_REG, i_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+// TK read, write RD_WR_DATA
+
+///
+/// @brief Setup odt_wr/rd_config
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target the target associated with this cal setup
+/// @return FAPI2_RC_SUCCESS iff setup was successful
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+fapi2::ReturnCode reset_rd_wr_data( const fapi2::Target<T>& i_target )
+{
+    // MPR_PATTERN_BIT of 0F0F0F0F pattern
+    static const uint64_t MPR_PATTERN = 0x5555;
+    fapi2::buffer<uint64_t> l_data;
+
+    l_data.insertFromRight<TT::MPR_PATTERN, TT::MPR_PATTERN_LEN>(MPR_PATTERN);
+
+    FAPI_INF("seq_rd_wr 0x%llx", l_data);
+    FAPI_TRY( mss::putScom(i_target, TT::SEQ_RDWR_DATA0, l_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::SEQ_RDWR_DATA1, l_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief reset SEQ_CONFIG0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+inline fapi2::ReturnCode reset_config0( const fapi2::Target<T>& i_target )
+{
+    // TK ATTR_VPD_DRAM_2N_MODE_ENABLED  49, 0b1, (def_2N_mode);       # enable 2 cycle addr mode BRS
+    FAPI_TRY( write_config0(i_target, 0) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief reset SEQ_TIMING0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+fapi2::ReturnCode reset_timing0( const fapi2::Target<T>& i_target );
+
+
+///
+/// @brief reset SEQ_TIMING1
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+fapi2::ReturnCode reset_timing1( const fapi2::Target<T>& i_target );
+
+
+///
+/// @brief reset SEQ_TIMING2
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+fapi2::ReturnCode reset_timing2( const fapi2::Target<T>& i_target );
+
+///
+/// @brief reset seq
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+inline fapi2::ReturnCode reset( const fapi2::Target<T>& i_target )
+{
+    FAPI_TRY( reset_config0(i_target) );
+    FAPI_TRY( reset_timing0(i_target) );
+    FAPI_TRY( reset_timing1(i_target) );
+    FAPI_TRY( reset_timing2(i_target) );
+    FAPI_TRY( reset_rd_wr_data(i_target) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+} // close namespace seq
+
+} // close namespace mss
+
+#endif
+
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
index bd76b42da..9d7e98c38 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
@@ -61,14 +61,8 @@ enum sizes
     BYTES_PER_GB = 1000000000,      ///< Multiplier to go from GB to B
     T_PER_MT     = 1000000,          ///< Multiplier to go from MT/s to T/s
 
-    // All need to be attributes - BRS
-    // 48:51, 0b1100, (def_is_sim);       # BIG_STEP = 12 (changed from default for SIM)
-    // 48:51, 0b0000, any;       # BIG_STEP = 0  SWyatt
-    // #48:51, 0b0010, any;       # BIG_STEP = 2  (default)
-    // 52:54,  0b000,  any;       # SMALL_STEP = 0 (default)      SWyatt
-    //#52:54,  0b001,  any;       # SMALL_STEP = 1        (!! recommend setting to 0)
-    // 55:60,  0b101010, any;     # WR_PRE_DLY = 42
-    WR_LVL_BIG_STEP = 0b1100,
+    // All need to be attributes? - BRS
+    WR_LVL_BIG_STEP = 0b0111,
     WR_LVL_SMALL_STEP = 0b000,
     WR_LVL_PRE_DLY = 0b101010,
     WR_LVL_NUM_VALID_SAMPLES = 0x5,
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C
index 9f69233be..f6c4eb1f5 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C
@@ -22,3 +22,73 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file workarounds/dp16.C
+/// @brief Workarounds for the DP16 logic blocks
+/// Workarounds are very deivce specific, so there is no attempt to generalize
+/// this code in any way.
+///
+// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Steven Glancy <sglancy@usi.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 2
+// *HWP Consumed by: FSP:HB
+
+#include <fapi2.H>
+#include <p9_mc_scom_addresses.H>
+#include <p9_mc_scom_addresses_fld.H>
+
+#include <lib/utils/scom.H>
+#include <lib/utils/pos.H>
+#include <lib/workarounds/dp16_workarounds.H>
+
+namespace mss
+{
+
+namespace workarounds
+{
+
+namespace dp16
+{
+
+///
+/// @brief DQS polarity workaround
+/// For Monza DDR port 2, one pair of DQS P/N is swapped polarity.  Not in DDR port 6
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+/// @note This function is called during the phy scom init procedure, after the initfile is
+/// processed. It is specific to the Monza module, but can be called for all modules as it
+/// will enforce its requirements internally
+///
+fapi2::ReturnCode dqs_polarity( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target )
+{
+    // Receiver config provided by S. Wyatt 8/16
+    constexpr uint64_t rx_config = 0x4000;
+
+    // For Monza DDR port 2, one pair of DQS P/N is swapped polarity.  Not in DDR port 6
+    // For Monza DDR port 3, one pair of DQS P/N is swapped polarity.  Not in DDR port 7
+    const auto l_pos = mss::pos(i_target);
+
+    // TODO RTC:160353 Need module/chip rev EC support for workarounds
+    // Need to check this for Monza only when attribute support for EC levels is in place
+
+    // So we need to make sure our position is 2 or 3 and skip for the other ports.
+    if (l_pos == 2)
+    {
+        FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4, rx_config) );
+    }
+
+    if (l_pos == 3)
+    {
+        FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0, rx_config) );
+    }
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+} // close namespace dp16
+} // close namespace workarounds
+} // close namespace mss
+
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H
index 51f44f804..fd20617f3 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H
@@ -22,3 +22,47 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file workarounds/dp16.H
+/// @brief Workarounds for the DP16 logic blocks
+/// Workarounds are very deivce specific, so there is no attempt to generalize
+/// this code in any way.
+///
+// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Steven Glancy <sglancy@usi.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 2
+// *HWP Consumed by: FSP:HB
+
+#ifndef _MSS_WORKAROUNDS_DP16_H_
+#define _MSS_WORKAROUNDS_DP16_H_
+
+#include <fapi2.H>
+
+namespace mss
+{
+
+namespace workarounds
+{
+
+namespace dp16
+{
+
+///
+/// @brief DQS polarity workaround
+/// For Monza DDR port 2, one pair of DQS P/N is swapped polarity.  Not in DDR port 6
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+/// @note This function is called during the phy scom init procedure, after the initfile is
+/// processed. It is specific to the Monza module, but can be called for all modules as it
+/// will enforce its requirements internally
+///
+fapi2::ReturnCode dqs_polarity( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
+
+} // close namespace dp16
+} // close namespace workarounds
+} // close namespace mss
+
+#endif
+
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
index e1c67caf6..23546af61 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
@@ -124,12 +124,7 @@ extern "C"
 
             // The following registers must be configured to the correct operating environment:
 
-            // Unclear, can probably be 0's for sim BRS
             // • Section 5.2.5.10 SEQ ODT Write Configuration {0-3} on page 422
-
-            FAPI_TRY( mss::reset_seq_config0(p) );
-            FAPI_TRY( mss::reset_seq_rd_wr_data(p) );
-
             FAPI_TRY( mss::reset_odt_config(p) );
 
             // These are reset in phy_scominit