Move FSP-only attributes to common targeting for Open Power

- Added default lane masks to Hostboot system XML files
- Added PCIE config related module IDs and reason codes
- Added new packing function to combine 4x uint8 into 1x uint32
- Added dynamic PCIE config for SP-less environments
- Moved PCIE attributes into common attribute definition
- Attached new PCIE attributes to common target definition
- Defaulted PCIE lanes per proc appropriately for all proc chips
- Added CDM_DOMAIN attribute into common attribute definition
- Attached + defaulted CDM domain in common target definition
- Updated common MRW parser to customize the new PCIE attributes

Change-Id: I3779ca6e6a4803d7e78e21e47a92e0b1a09e657d
RTC: 113488
CMVC-coreq: 942076
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13997
Tested-by: Jenkins Server
Reviewed-by: STEPHEN M. CPREK <smcprek@us.ibm.com>
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

15 files changed, 1902 insertions, 18 deletions

diff --git a/src/build/citest/etc/patches/attribute_types.patch b/src/build/citest/etc/patches/attribute_types.patch
index d2cd19443..a97e53b86 100644
--- a/src/build/citest/etc/patches/attribute_types.patch
+++ b/src/build/citest/etc/patches/attribute_types.patch
@@ -1,4 +1,192 @@
-966,984d965
+778,1003c778
+<     <attribute>
+<         <id>IOP_LANES_PER_PROC</id>
+<         <description>Number of PCIE lanes per PROC
+<             creator: MRW
+<             consumer: hwsv
+<             firmware notes:
+<             PCIE Lanes per PROC
+<         </description>
+<         <simpleType>
+<             <uint8_t>
+<             </uint8_t>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_LANE_MASK</id>
+<         <description>PCIE Lane Mask
+<             creator: MRW
+<             consumer: 
+<             firmware notes:
+<             PCIE Lane mask
+<             Array index: IOP number (0:1)
+<                          lane set (0:1)
+<         </description>
+<         <simpleType>
+<             <uint16_t>
+<             </uint16_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>semi-non-volatile</persistency>
+<         <readable/>
+<         <writeable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_DSMP_CAPABLE</id>
+<         <description>DSMP capability
+<             creator: platform
+<             consumer:
+<             firmware notes:
+<             DSMP capability
+<             Array index: IOP number (0:1)
+<                          Lane Set (0:1)
+<         </description>
+<         <simpleType>
+<             <uint8_t>
+<             </uint8_t>
+<             <array>2,2</array>
+<             </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_REVERSAL</id>
+<         <description>PCIE IOP reversal configuration
+<             creator: HWSV
+<             consumer:
+<             firmware notes:
+<             PCIE IOP reversal configuration
+<             Array index: IOP number (0:1)
+<                          Lane Index (0:1)
+<         </description>
+<         <simpleType>
+<             <uint8_t>
+<             </uint8_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>semi-non-volatile</persistency>
+<         <readable/>
+<         <writeable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id>
+<         <description>PCIE IOP reversal base configuration
+<             creator: MRW
+<             consumer: 
+<             firmware notes:
+<             PCIE IOP reversal base configuration
+<             Array index: IOP number (0:1)
+<                          Lane Index (0:1)
+<         </description>
+<         <simpleType>
+<             <uint8_t>
+<             </uint8_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_SWAP_NON_BIFURCATED</id>
+<         <description>PCIE IOP swap base configuration
+<             creator: platform
+<             consumer:
+<             firmware notes:
+<             Encoded PCIE IOP swap configuration
+<             Array index: IOP number (0:1)
+<                          Lane Index (0:1)
+<         </description>
+<         <simpleType>
+<             <uint8_t></uint8_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+<         <description>PCIE Lane Mask base configuration
+<             creator: HWSV
+<             consumer: 
+<             firmware notes:
+<             PCIE Lane mask
+<             Array index: IOP number (0:1)
+<                          Lane Index (0:1)
+<         </description>
+<         <simpleType>
+<             <uint16_t>
+<             </uint16_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<         <attribute>
+<         <id>PROC_PCIE_IOP_REVERSAL_BIFURCATED</id>
+<         <description>PCIE IOP Reversal bifurcated configuration
+<             creator: MRW
+<             consumer: 
+<             firmware notes:
+<             PCIE IOP Reversal bifurcated configuration
+<             Array index: IOP number (0:1)
+<                          Lane Set   (0:1)
+<         </description>
+<         <simpleType>
+<             <uint8_t>
+<             </uint8_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_SWAP_BIFURCATED</id>
+<         <description>PCIE IOP swap bifurcated configuration
+<             creator: MRW
+<             consumer:
+<             firmware notes:
+<             Encoded PCIE IOP swap bifurcated configuration
+<             Array index: IOP number (0:1)
+<                          Lane Set   (0:1)
+<         </description>
+<         <simpleType>
+<             <uint8_t></uint8_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_LANE_MASK_BIFURCATED</id>
+<         <description>PCIE Lane mask bifurcated configuration
+<             creator: MRW
+<             consumer: 
+<             firmware notes:
+<             PCIE Lane mask bifurcated configuration
+<             Array index: IOP number (0:1)
+<                          Lane Set   (0:1)
+<         </description>
+<         <simpleType>
+<             <uint16_t>
+<             </uint16_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
 <         <id>PROC_PCIE_LANE_EQUALIZATION</id>
 <         <description>PCIE Lane Equalization values for each PHB
 <             creator: MRW
@@ -18,7 +206,28 @@
 <         <fspOnly/>
 <     </attribute>
 <     <attribute>
-1413,1427d1412
+<         <id>PROC_PCIE_IS_SLOT</id>
+<         <description>Whether the end point is a slot or not
+<             creator:MRW
+<             consumer: 
+<             firmware notes:
+<             Whether the end point is a slot or not
+<             1 - Slot, 0 - not a slot
+<             Array index: Iop Number (0:1)
+<                          lane Set   (0:1)
+<         </description>
+<         <simpleType>
+<             <uint8_t>
+<             </uint8_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+---
+> 
+1413,1427d1187
 <     <attribute>
 <         <id>OCC_MASTER_CAPABLE</id>
 <         <description>
@@ -34,3 +243,69 @@
 <         <readable/>
 <         <fspOnly/>
 <     </attribute>
+1774,1838d1533
+<     <enumerationType>
+<         <id>CDM_DOMAIN</id>
+<         <description>Enumeration indicating CDM Domain of a target</description>
+<         <enumerator>
+<             <name>NONE</name>
+<             <value>0</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>CPU</name>
+<             <value>1</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>DIMM</name>
+<             <value>2</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>FABRIC</name>
+<             <value>3</value>
+<         </enumerator> 
+<         <enumerator>
+<             <name>MEM</name>
+<             <value>4</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>IO</name>
+<             <value>5</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>NODE</name>
+<             <value>6</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>CLOCK</name>
+<             <value>7</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>PSI</name>
+<             <value>8</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>FSP</name>
+<             <value>9</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>ALL</name>
+<             <value>10</value>
+<         </enumerator>
+<         <default>NONE</default>
+<    </enumerationType>
+< 
+<     <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <description>Indicates the CDM Domain of an applicable target
+<         </description>
+<         <simpleType>
+<             <enumeration>
+<                 <id>CDM_DOMAIN</id>
+<             </enumeration>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <hasStringConversion/>
+<         <fspOnly/>
+<     </attribute>
+<     
diff --git a/src/build/citest/etc/patches/target_types.patch b/src/build/citest/etc/patches/target_types.patch
index 2e53ed871..497d730d8 100644
--- a/src/build/citest/etc/patches/target_types.patch
+++ b/src/build/citest/etc/patches/target_types.patch
@@ -20,7 +20,159 @@
 < </targetType>
 < 
 < <targetType>
-627,629d626
+165,168d143
+<         <id>CDM_DOMAIN</id>
+<         <default>CPU</default>
+<     </attribute>
+<     <attribute>
+356,359d330
+<     <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>MEM</default>
+<     </attribute>
+371,374d341
+<         <id>CDM_DOMAIN</id>
+<         <default>NODE</default>
+<     </attribute>
+<     <attribute>
+596a564
+> 
+600,632d567
+<         <id>PROC_PCIE_LANE_MASK</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_LANE_MASK_BIFURCATED</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_SWAP_NON_BIFURCATED</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_SWAP_BIFURCATED</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_REVERSAL_BIFURCATED</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_REVERSAL</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_DSMP_CAPABLE</id>        
+<     </attribute>
+<     <attribute>
 <         <id>PROC_PCIE_LANE_EQUALIZATION</id>
 <     </attribute>
 <     <attribute>
+<         <id>PROC_PCIE_IS_SLOT</id>
+<     </attribute>
+<     <attribute>
+635,637d569
+<    <attribute>
+<         <id>IOP_LANES_PER_PROC</id>
+<    </attribute>
+643,646d574
+<         <id>IOP_LANES_PER_PROC</id>
+<         <default>24</default>
+<    </attribute>
+<    <attribute>
+659,662d586
+<         <id>IOP_LANES_PER_PROC</id>
+<         <default>32</default>
+<    </attribute>
+<    <attribute>
+702d625
+<  
+734a658
+> 
+881,912d804
+<  
+< <targetTypeExtension>
+<     <id>lcard-dimm</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>DIMM</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>chip-processor-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>FABRIC</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>unit-abus-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>FABRIC</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>unit-xbus-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>FABRIC</default>
+<     </attribute>
+< </targetTypeExtension>
+917,920d808
+<         <id>CDM_DOMAIN</id>
+<         <default>FABRIC</default>
+<     </attribute>
+<     <attribute>
+925,972d812
+< <targetTypeExtension>
+<     <id>unit-pore-power8</id>
+<     <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>FABRIC</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>unit-mbs-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>MEM</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>unit-l4-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>MEM</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>unit-mcs-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>MEM</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>unit-mba-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>MEM</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>unit-pci-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>IO</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
diff --git a/src/include/usr/errl/hberrltypes.H b/src/include/usr/errl/hberrltypes.H
index 94e3722a8..e948e4df0 100644
--- a/src/include/usr/errl/hberrltypes.H
+++ b/src/include/usr/errl/hberrltypes.H
@@ -79,6 +79,11 @@ namespace ERRORLOG { class ErrlEntry; };
         ( (TO_UINT64(TWO_UINT16_TO_UINT32(mostleft_16, left_16)) << 32) | \
           (TO_UINT64(TWO_UINT16_TO_UINT32(right_16, mostright_16))) )
 
+// uint32_t val = 8bit:8bit:8bit:8bit
+#define FOUR_UINT8_TO_UINT32(mostleft_8, left_8, right_8, mostright_8) \
+        ( (TO_UINT32(TWO_UINT8_TO_UINT16(mostleft_8, left_8)) << 16) | \
+          (TO_UINT32(TWO_UINT8_TO_UINT16(right_8, mostright_8))) )
+
 namespace ERRORLOG
 {
 
diff --git a/src/include/usr/hwpf/istepreasoncodes.H b/src/include/usr/hwpf/istepreasoncodes.H
index 1a8314e25..b433701cb 100644
--- a/src/include/usr/hwpf/istepreasoncodes.H
+++ b/src/include/usr/hwpf/istepreasoncodes.H
@@ -56,6 +56,8 @@ enum istepModuleId
     ISTEP_HOST_ACTIVATE_MASTER                          = 0x06,
     ISTEP_SBE_CENTAUR_INIT                              = 0x07,
     ISTEP_ENABLE_CORE_CHECKSTOPS                        = 0x08,
+    ISTEP_DECONFIG_PHBS_BASED_ON_PCI_STATE              = 0x09,
+    ISTEP_COMPUTE_PCIE_CONFIG_ATTRS                     = 0x0A,
 };
 
 /**
@@ -76,6 +78,9 @@ enum istepReasonCode
     ISTEP_REPAIR_LOADER_RETRY_OCCURED           = ISTEP_COMP_ID | 0x07,
     ISTEP_MM_MAP_ERR                            = ISTEP_COMP_ID | 0x08,
     ISTEP_INCORRECT_TARGET_COUNT                = ISTEP_COMP_ID | 0x09,
+    ISTEP_INVALID_TARGET_TYPE                   = ISTEP_COMP_ID | 0x0A,
+    ISTEP_INVALID_ATTR_VALUE                    = ISTEP_COMP_ID | 0x0B,
+    ISTEP_INVALID_CONFIGURATION                 = ISTEP_COMP_ID | 0x0C,
 };  // end ISTEP
 
 }
diff --git a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
index bd6dc5775..f94bf8fb5 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
@@ -45,6 +45,7 @@
 #include    <errl/errludtarget.H>
 
 #include    <initservice/isteps_trace.H>
+#include    <initservice/initserviceif.H>
 
 //  targeting support
 #include    <targeting/common/commontargeting.H>
@@ -782,6 +783,787 @@ void* call_proc_abus_scominit( void    *io_pArgs )
     return l_StepError.getErrorHandle();
 }
 
+//******************************************************************************
+// _queryIopsToBifurcateAndPhbsToDisable
+//******************************************************************************
+
+#ifdef DYNAMIC_BIFURCATION
+// Normally a x16 PCIE adapter is driven by one PHB in the processor.
+// Some x16 adapters have two logically different devices integrated
+// onto the same adapter, each acting as a x8 PCIE endpoint driven by
+// its own PHB.  The ability to detect which type of PCIE adapter is
+// present and dynamically reconfigure the PCIE langes / PHBs to support
+// whatever is present is called 'dynamic bifurcation'.  This feature is
+// not officially supported however hooks remain in place to add that
+// support easily.  To enable it, define the DYNAMIC_BIFURCATION flag
+// and implement the guts of the
+// _queryIopsToBifurcateAndPhbsToDisable function.
+
+errlHndl_t _queryIopsToBifurcateAndPhbsToDisable(
+    TARGETING::ConstTargetHandle_t const       i_pProcChipTarget,
+    BifurcatedIopsContainer&                   o_iopList,
+    TARGETING::ATTR_PROC_PCIE_PHB_ACTIVE_type& o_disabledPhbsMask)
+{
+    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+        ENTER_MRK "_queryIopsToBifurcateAndPhbsToDisable: Proc chip target "
+        "HUID = 0x%08X.",
+        i_pProcChipTarget ?
+            i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>() : 0);
+
+    errlHndl_t pError = NULL;
+    o_iopList.clear();
+    o_disabledPhbsMask = 0;
+
+    do {
+
+    // Extension point to return bifurcated IOPs and PHBs to disable.
+    // Assuming no extensions are added, the function returns no IOPs to
+    // bifurcate and no PHBs to disable
+
+    // If implemented, this function should only return error on software code
+    // bug.  Any other condition should result in IOPs not being bifurcated and
+    // host taking care of that condition.
+
+    } while(0);
+
+    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+        EXIT_MRK "_queryIopsToBifurcateAndPhbsToDisable: EID = 0x%08X, "
+        "PLID = 0x%08X, RC = 0x%08X.",
+        ERRL_GETEID_SAFE(pError),ERRL_GETPLID_SAFE(pError),
+        ERRL_GETRC_SAFE(pError));
+
+    return pError;
+}
+
+#endif
+
+//******************************************************************************
+// _deconfigPhbsBasedOnPciState
+//******************************************************************************
+
+void _deconfigPhbsBasedOnPciState(
+    TARGETING::ConstTargetHandle_t const       i_pProcChipTarget,
+    TARGETING::ATTR_PROC_PCIE_PHB_ACTIVE_type& io_phbActiveMask)
+{
+    errlHndl_t pError = NULL;
+
+    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+        ENTER_MRK "_deconfigPhbsBasedOnPciState: Proc chip target HUID = "
+        "0x%08X, PHB active mask = 0x%02X.",
+        i_pProcChipTarget ?
+            i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>() : 0,
+        io_phbActiveMask);
+
+    // Get proc chip's functional PCI units
+    TARGETING::TargetHandleList funcPciList;
+    (void)TARGETING::getChildChiplets(
+        funcPciList,i_pProcChipTarget,TARGETING::TYPE_PCI);
+
+    // Activate PHB mask bits based on functional PCI units
+    TARGETING::ATTR_PROC_PCIE_PHB_ACTIVE_type activePciMask = 0;
+    for (TARGETING::TargetHandleList::const_iterator pciItr
+            = funcPciList.begin();
+         pciItr != funcPciList.end();
+         ++pciItr)
+    {
+        // PCI chip unit to PHB mapping is as follows:
+        //
+        // PCI-0 => PHB0
+        // PCI-1 => PHB1
+        // PCI-2 => PHB2
+        //
+        // Further, io_phbActiveMask and activePciMask are bitmasks whose
+        // leftmost bit corresponds to PHB0, followed by bits for PHB1 and PHB2.
+        // The remaining bits are ignored.
+
+        // Compensate for the fact that PHB mask bits start on left side of the
+        // mask
+        const size_t bitsToLeftShift
+            = ((sizeof(activePciMask)*BITS_PER_BYTE) - 1);
+
+        // Committing an error here because this would mean a read only
+        // attribute was set to a value which should be impossible, the
+        // side effect will be that whatever PHB this should really correspond
+        // to will not be enabled
+        if((*pciItr)->getAttr<TARGETING::ATTR_CHIP_UNIT>() > bitsToLeftShift)
+        {
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                ERR_MRK "_deconfigPhbsBasedOnPciState> "
+                "Code Bug! CHIP_UNIT attribute (%d) for PCI unit with HUID of "
+                "0x%08X was larger than max value of %d in "
+                "_deconfigPhbsBasedOnPciState().",
+                (*pciItr)->getAttr<TARGETING::ATTR_CHIP_UNIT>(),
+                (*pciItr)->getAttr<TARGETING::ATTR_HUID>(),
+                bitsToLeftShift );
+            /*@
+             * @errortype
+             * @moduleid         ISTEP_DECONFIG_PHBS_BASED_ON_PCI_STATE
+             * @reasoncode       ISTEP_TARGET_NULL
+             * @userdata1[0:31]  HUID of PCI target with bad ATTR_CHIP_UNIT
+             * @userdata1[32:39] ATTR_CHIP_UNIT value
+             * @userdata2[40:47] # bits to shift
+             * @devdesc          Attribute model inconsistency detected; Cannot
+             *                   represent PHB bitmask given the value of the
+             *                   PCI target's chip unit attribute.  Continuing
+             *                   without PHB enabled
+             * @custdesc         A problem isolated to firmware occurred during
+             *                   the IPL of the system.
+             */
+            pError = new ERRORLOG::ErrlEntry(
+                ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+                ISTEP_DECONFIG_PHBS_BASED_ON_PCI_STATE,
+                ISTEP_TARGET_NULL,
+                TWO_UINT32_TO_UINT64(
+                    (*pciItr)->getAttr<TARGETING::ATTR_HUID>(),
+                    TWO_UINT16_TO_UINT32(
+                        TWO_UINT8_TO_UINT16(
+                            (*pciItr)->getAttr<TARGETING::ATTR_CHIP_UNIT>(),
+                            bitsToLeftShift),
+                        0)),
+                0,
+                true);
+
+            ERRORLOG::ErrlUserDetailsTarget(*pciItr).addToLog(pError);
+            pError->collectTrace(ISTEP_COMP_NAME);
+            errlCommit(pError, ISTEP_COMP_ID);
+
+            continue;
+        }
+
+        activePciMask |=
+            (1 << (  bitsToLeftShift
+                   - (*pciItr)->getAttr<TARGETING::ATTR_CHIP_UNIT>()));
+    }
+
+    // Can never enable more PHBs than were supplied as input.  It's conceivable
+    // that due to code bug in the chip unit attribute, the unit value
+    // corresponds to a non supported PHB.  This masking will also prevent the
+    // error from propagating.  There is no way to trap for valid PHBs that are
+    // cross-wired vis a vis the chip unit attribute.
+    io_phbActiveMask &= activePciMask;
+
+    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+        EXIT_MRK "_deconfigPhbsBasedOnPciState: io_phbActiveMask = 0x%02X",
+        io_phbActiveMask);
+
+    return;
+}
+
+//******************************************************************************
+// Local logical equality operator for matching lane configuration rows
+//******************************************************************************
+
+inline bool operator==(
+    const laneConfigRow& i_lhs,
+    const laneConfigRow& i_rhs)
+{
+    return ( memcmp(i_lhs.laneSet,i_rhs.laneSet,sizeof(i_lhs.laneSet)) == 0);
+}
+
+//******************************************************************************
+// _laneMaskToLaneWidth
+//******************************************************************************
+
+LaneWidth _laneMaskToLaneWidth(const uint16_t i_laneMask)
+{
+    LaneWidth laneWidth = LANE_WIDTH_NC;
+    if(i_laneMask == LANE_MASK_X16)
+    {
+        laneWidth = LANE_WIDTH_16X;
+    }
+    else if(   (i_laneMask == LANE_MASK_X8_GRP0)
+            || (i_laneMask == LANE_MASK_X8_GRP1))
+    {
+        laneWidth = LANE_WIDTH_8X;
+    }
+
+    return laneWidth;
+}
+
+//******************************************************************************
+// computeProcPcieConfigAttrs
+//******************************************************************************
+
+errlHndl_t computeProcPcieConfigAttrs(
+    TARGETING::TargetHandle_t const i_pProcChipTarget)
+{
+    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+        ENTER_MRK "computeProcPcieConfigAttrs: Proc chip target HUID = "
+        "0x%08X.",
+        i_pProcChipTarget ?
+            i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>() : 0);
+
+    // Currently there are two IOP config tables, one for procs with 24 usable
+    // PCIE lanes and one for proces with 32 usable PCIE lanes.  In general, the
+    // code accumulates the current configuration of the IOPs from the MRW and
+    // other dynamic information (such as bifurcation, etc.), then matches that
+    // config to one of the rows in the table.  Once a match is discovered, the
+    // IOP config value is pulled from the matching row and set in the
+    // attributes.
+    const laneConfigRow x24_laneConfigTable[] =
+        {{{{{LANE_WIDTH_16X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}},
+           {{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x0,PHB0_MASK|PHB1_MASK},
+
+         {{{{LANE_WIDTH_16X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}},
+           {{LANE_WIDTH_NC,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x0,PHB0_MASK},
+
+         {{{{LANE_WIDTH_16X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}},
+           {{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x1,PHB0_MASK|PHB1_MASK},
+
+         {{{{LANE_WIDTH_16X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}},
+           {{LANE_WIDTH_NC,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x1,PHB0_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}},
+           {{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x2,PHB0_MASK|PHB1_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_8X,DSMP_DISABLE}},
+           {{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x3,PHB0_MASK|PHB1_MASK|PHB2_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_8X,DSMP_DISABLE}},
+           {{LANE_WIDTH_NC,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x3,PHB0_MASK|PHB2_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_8X,DSMP_ENABLE}},
+           {{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x4,PHB0_MASK|PHB1_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_8X,DSMP_ENABLE}},
+           {{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x5,PHB0_MASK|PHB1_MASK},
+
+         {{{{LANE_WIDTH_16X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}},
+           {{LANE_WIDTH_8X,DSMP_ENABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x6,PHB1_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_8X,DSMP_DISABLE}},
+           {{LANE_WIDTH_8X,DSMP_ENABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x7,PHB1_MASK|PHB2_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_ENABLE},
+            {LANE_WIDTH_8X,DSMP_ENABLE}},
+           {{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x8,PHB1_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_ENABLE},
+            {LANE_WIDTH_8X,DSMP_ENABLE}},
+           {{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x9,PHB1_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_ENABLE},
+            {LANE_WIDTH_8X,DSMP_DISABLE}},
+           {{LANE_WIDTH_8X,DSMP_ENABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0xA,PHB2_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_8X,DSMP_ENABLE}},
+           {{LANE_WIDTH_8X,DSMP_ENABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0xB,PHB1_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_ENABLE},
+            {LANE_WIDTH_8X,DSMP_DISABLE}},
+           {{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0xC,PHB1_MASK|PHB2_MASK},
+        };
+
+    const laneConfigRow* x24_end = x24_laneConfigTable +
+        (  sizeof(x24_laneConfigTable)
+         / sizeof(x24_laneConfigTable[0]));
+
+    const laneConfigRow x32_laneConfigTable[] =
+        {{{{{LANE_WIDTH_16X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}},
+           {{LANE_WIDTH_16X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x0,PHB0_MASK|PHB1_MASK},
+
+         {{{{LANE_WIDTH_16X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}},
+           {{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_8X,DSMP_DISABLE}}},
+             0x1,PHB0_MASK|PHB1_MASK|PHB2_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}},
+           {{LANE_WIDTH_16X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x2,PHB0_MASK|PHB1_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}},
+           {{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_8X,DSMP_DISABLE}}},
+             0x3,PHB0_MASK|PHB1_MASK|PHB2_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_8X,DSMP_ENABLE}},
+           {{LANE_WIDTH_16X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x4,PHB0_MASK|PHB1_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_8X,DSMP_ENABLE}},
+           {{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_8X,DSMP_DISABLE}}},
+             0x5,PHB0_MASK|PHB1_MASK|PHB2_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_ENABLE},
+            {LANE_WIDTH_8X,DSMP_DISABLE}},
+           {{LANE_WIDTH_16X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x6,PHB0_MASK|PHB1_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_ENABLE},
+            {LANE_WIDTH_8X,DSMP_DISABLE}},
+           {{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_8X,DSMP_DISABLE}}},
+             0x7,PHB0_MASK|PHB1_MASK|PHB2_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_ENABLE},
+            {LANE_WIDTH_8X,DSMP_ENABLE}},
+           {{LANE_WIDTH_16X,DSMP_DISABLE},
+            {LANE_WIDTH_NC,DSMP_DISABLE}}},
+             0x8,PHB1_MASK},
+
+         {{{{LANE_WIDTH_8X,DSMP_ENABLE},
+            {LANE_WIDTH_8X,DSMP_ENABLE}},
+           {{LANE_WIDTH_8X,DSMP_DISABLE},
+            {LANE_WIDTH_8X,DSMP_DISABLE}}},
+             0x9,PHB1_MASK|PHB2_MASK},
+        };
+
+    const laneConfigRow* x32_end = x32_laneConfigTable +
+        (  sizeof(x32_laneConfigTable)
+         / sizeof(x32_laneConfigTable[0]));
+
+    errlHndl_t pError = NULL;
+    const laneConfigRow* pLaneConfigTableBegin = NULL;
+    const laneConfigRow* pLaneConfigTableEnd = NULL;
+
+    do
+    {
+        if(i_pProcChipTarget == NULL)
+        {
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                ERR_MRK "computeProcPcieConfigAttrs> "
+                "Code bug! Input processor target is NULL");
+
+            /*@
+             * @errortype
+             * @moduleid    ISTEP_COMPUTE_PCIE_CONFIG_ATTRS
+             * @reasoncode  ISTEP_TARGET_NULL
+             * @devdesc     Caller passed a NULL processor target
+             * @custdesc    A problem isolated to firmware occurred during the
+             *              IPL of the system.
+             */
+            pError = new ERRORLOG::ErrlEntry(
+                ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+                ISTEP_COMPUTE_PCIE_CONFIG_ATTRS,
+                ISTEP_TARGET_NULL,
+                0,
+                0,
+                true);
+            pError->collectTrace(ISTEP_COMP_NAME);
+            break;
+        }
+
+        const TARGETING::ATTR_CLASS_type targetClass
+            = i_pProcChipTarget->getAttr<TARGETING::ATTR_CLASS>();
+        const TARGETING::ATTR_TYPE_type targetType
+            = i_pProcChipTarget->getAttr<TARGETING::ATTR_TYPE>();
+        const bool targetPresent =
+            i_pProcChipTarget->getAttr<TARGETING::ATTR_HWAS_STATE>()
+                .present;
+
+        if(   (targetClass != TARGETING::CLASS_CHIP)
+           || (targetType != TARGETING::TYPE_PROC)
+           || (!targetPresent))
+        {
+            const TARGETING::ATTR_HUID_type targetHuid
+                = i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>();
+
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                ERR_MRK "computeProcPcieConfigAttrs> Code bug!"
+                "Input target is not a processor chip or is not present.  "
+                "Class = 0x%08X, "
+                "Type = 0x%08X, HUID = 0x%08X, Present? = %d",
+                targetClass,targetType,
+                targetHuid,
+                targetPresent);
+
+            /*@
+             * @errortype
+             * @moduleid         ISTEP_COMPUTE_PCIE_CONFIG_ATTRS
+             * @reasoncode       ISTEP_INVALID_TARGET_TYPE
+             * @userdata1[0:31]  Illegal target's class
+             * @userdata1[32:63] Illegal target's type
+             * @userdata2[0:31]  Illegal target's HUID
+             * @userdata2[32:63] Illegal target's presence (0=no, 1=yes)
+             * @devdesc          Caller passed a non-processor chip target or
+             *                   passed a processor chip target that was not
+             *                   present
+             * @custdesc         A problem isolated to firmware occurred during
+             *                   the IPL of the system.
+             */
+            pError = new ERRORLOG::ErrlEntry(
+                ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+                ISTEP_COMPUTE_PCIE_CONFIG_ATTRS,
+                ISTEP_INVALID_TARGET_TYPE,
+                TWO_UINT32_TO_UINT64(
+                    targetClass,targetType),
+                TWO_UINT32_TO_UINT64(
+                    targetHuid,targetPresent),
+                true);
+            ERRORLOG::ErrlUserDetailsTarget(i_pProcChipTarget).addToLog(pError);
+            pError->collectTrace(ISTEP_COMP_NAME);
+            break;
+        }
+
+        // Pick the appropriate IOP configuration table
+        if(   i_pProcChipTarget->getAttr<TARGETING::ATTR_IOP_LANES_PER_PROC>()
+           == IOP_LANES_PER_PROC_32X)
+        {
+            pLaneConfigTableBegin = x32_laneConfigTable;
+            pLaneConfigTableEnd = x32_end;
+        }
+        else if(   i_pProcChipTarget->getAttr<
+                       TARGETING::ATTR_IOP_LANES_PER_PROC>()
+                == IOP_LANES_PER_PROC_24X)
+        {
+            pLaneConfigTableBegin = x24_laneConfigTable;
+            pLaneConfigTableEnd = x24_end;
+        }
+        else
+        {
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                ERR_MRK "computeProcPcieConfigAttrs> "
+                "Code bug! Unsupported ATTR_IOP_LANES_PER_PROC attribute for "
+                "processor with HUID of 0x%08X.  Expected 24 or 32, but read "
+                "value of %d.",
+                i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>(),
+                i_pProcChipTarget->getAttr<
+                    TARGETING::ATTR_IOP_LANES_PER_PROC>());
+
+            /*@
+             * @errortype
+             * @moduleid         ISTEP_COMPUTE_PCIE_CONFIG_ATTRS
+             * @reasoncode       ISTEP_INVALID_ATTR_VALUE
+             * @userdata1[0:31]  Target's HUID
+             * @userdata2[32:63] ATTR_IOP_LANES_PER_PROC attribute value
+             * @devdesc          Illegal ATTR_IOP_LANES_PER_PROC attribute read
+             *                   from a processor chip target.
+             * @custdesc         A problem isolated to firmware or firmware
+             *                   customization occurred during the IPL of the
+             *                   system.
+             */
+            pError = new ERRORLOG::ErrlEntry(
+                ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+                ISTEP_COMPUTE_PCIE_CONFIG_ATTRS,
+                ISTEP_INVALID_ATTR_VALUE,
+                TWO_UINT32_TO_UINT64(
+                    i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>(),
+                    i_pProcChipTarget->getAttr<
+                        TARGETING::ATTR_IOP_LANES_PER_PROC>()),
+                0,
+                true);
+            ERRORLOG::ErrlUserDetailsTarget(i_pProcChipTarget).addToLog(pError);
+            pError->collectTrace(ISTEP_COMP_NAME);
+            break;
+        }
+
+        TARGETING::ATTR_PROC_PCIE_PHB_ACTIVE_type disabledPhbs = 0;
+
+#ifdef DYNAMIC_BIFURCATION
+
+        // Figure out which IOPs need bifurcation, and as a result, which PHBs
+        // to disable
+        BifurcatedIopsContainer iopList;
+        pError = _queryIopsToBifurcateAndPhbsToDisable(
+            i_pProcChipTarget,
+            iopList,
+            disabledPhbs);
+        if(pError!=NULL)
+        {
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                ERR_MRK "computeProcPcieConfigAttrs> "
+                "Failed in call to _queryIopsToBifurcateAndPhbsToDisable; "
+                "Proc HUID = 0x%08X.",
+                i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>());
+            break;
+        }
+#endif
+
+        // Arrays require all try[Get|Set]Attr API calls in order to be able to
+        // read them properly.  All attributes should exist, so assert if they
+        // do not.
+        TARGETING::ATTR_PROC_PCIE_LANE_MASK_NON_BIFURCATED_type
+            laneMaskNonBifurcated = {{0}};
+        assert(i_pProcChipTarget->tryGetAttr<
+            TARGETING::ATTR_PROC_PCIE_LANE_MASK_NON_BIFURCATED>(
+                laneMaskNonBifurcated));
+
+        TARGETING::ATTR_PROC_PCIE_IOP_REVERSAL_NON_BIFURCATED_type
+            laneReversalNonBifrucated = {{0}};
+        assert(i_pProcChipTarget->tryGetAttr<
+            TARGETING::ATTR_PROC_PCIE_IOP_REVERSAL_NON_BIFURCATED>(
+                laneReversalNonBifrucated));
+
+        TARGETING::ATTR_PROC_PCIE_IOP_SWAP_NON_BIFURCATED_type
+            laneSwapNonBifurcated = {{0}};
+        assert(i_pProcChipTarget->tryGetAttr<
+            TARGETING::ATTR_PROC_PCIE_IOP_SWAP_NON_BIFURCATED>(
+                laneSwapNonBifurcated));
+
+        TARGETING::ATTR_PROC_PCIE_LANE_MASK_type
+            effectiveLaneMask = {{0}};
+        memcpy(effectiveLaneMask,laneMaskNonBifurcated,
+            sizeof(effectiveLaneMask));
+
+        TARGETING::ATTR_PROC_PCIE_IOP_REVERSAL_type
+            effectiveLaneReversal = {{0}};
+        memcpy(effectiveLaneReversal,laneReversalNonBifrucated,
+            sizeof(effectiveLaneReversal));
+
+        TARGETING::ATTR_PROC_PCIE_IOP_SWAP_type
+            effectiveLaneSwap = {0};
+
+        // Apply the non-bifurcated lane swap
+        for(size_t iop = 0; iop<MAX_IOPS_PER_PROC; ++iop)
+        {
+            uint8_t laneSwap = 0;
+            for(size_t laneGroup = 0;
+                laneGroup <
+                    (sizeof(laneSwapNonBifurcated)/sizeof(effectiveLaneSwap));
+                ++laneGroup)
+            {
+                // If lanes are used and swap not yet set, then set it
+                if(   (effectiveLaneMask[iop][laneGroup])
+                   && (!laneSwap))
+                {
+                    laneSwap =
+                        laneSwapNonBifurcated[iop][laneGroup];
+                }
+            }
+            effectiveLaneSwap[iop] = laneSwap;
+        }
+
+#ifdef DYNAMIC_BIFURCATION
+
+        TARGETING::ATTR_PROC_PCIE_LANE_MASK_BIFURCATED_type
+            laneMaskBifurcated = {{0}};
+        assert(i_pProcChipTarget->tryGetAttr<
+            TARGETING::ATTR_PROC_PCIE_LANE_MASK_BIFURCATED>(
+                laneMaskBifurcated));
+
+        TARGETING::ATTR_PROC_PCIE_IOP_REVERSAL_BIFURCATED_type
+            laneReversalBifurcated = {{0}};
+        assert(i_pProcChipTarget->tryGetAttr<
+            TARGETING::ATTR_PROC_PCIE_IOP_REVERSAL_BIFURCATED>(
+                laneReversalBifurcated));
+
+        TARGETING::ATTR_PROC_PCIE_IOP_SWAP_BIFURCATED_type
+            bifurcatedSwap = {{0}};
+        assert(i_pProcChipTarget->tryGetAttr<
+            TARGETING::ATTR_PROC_PCIE_IOP_SWAP_BIFURCATED>(
+                bifurcatedSwap));
+
+        // Apply any IOP bifurcation settings
+        for(BifurcatedIopsContainer::const_iterator iopItr = iopList.begin();
+            iopItr != iopList.end();
+            ++iopItr)
+        {
+            BifurcatedIopsContainer::const_reference iop = *iopItr;
+            memcpy(
+                &effectiveLaneReversal[iop][0],
+                &laneReversalBifurcated[iop][0],
+                sizeof(effectiveLaneReversal)/MAX_IOPS_PER_PROC);
+
+            memcpy(
+                &effectiveLaneMask[iop][0],
+                &laneMaskBifurcated[iop][0],
+                sizeof(effectiveLaneMask)/MAX_IOPS_PER_PROC);
+
+            uint8_t laneSwap = 0;
+            for(size_t laneGroup=0;
+                laneGroup <
+                    (sizeof(bifurcatedSwap)/sizeof(effectiveLaneSwap));
+                ++laneGroup)
+            {
+                // If lanes are used and swap not yet set, then set it
+                if(   (effectiveLaneMask[iop][laneGroup])
+                   && (!laneSwap))
+                {
+                    laneSwap =
+                        bifurcatedSwap[iop][laneGroup];
+                }
+            }
+            effectiveLaneSwap[iop] = laneSwap;
+        }
+#endif
+
+        i_pProcChipTarget->setAttr<
+            TARGETING::ATTR_PROC_PCIE_LANE_MASK>(effectiveLaneMask);
+
+        i_pProcChipTarget->setAttr<
+            TARGETING::ATTR_PROC_PCIE_IOP_REVERSAL>(effectiveLaneReversal);
+
+        i_pProcChipTarget->setAttr<
+            TARGETING::ATTR_PROC_PCIE_IOP_SWAP>(effectiveLaneSwap);
+
+        TARGETING::ATTR_PROC_PCIE_DSMP_CAPABLE_type
+            dsmpCapable = {{0}};
+        assert(i_pProcChipTarget->tryGetAttr<
+            TARGETING::ATTR_PROC_PCIE_DSMP_CAPABLE>(dsmpCapable));
+
+        TARGETING::ATTR_PROC_PCIE_PHB_ACTIVE_type phbActiveMask = 0;
+        TARGETING::ATTR_PROC_PCIE_IOP_CONFIG_type iopConfig = 0;
+
+        laneConfigRow effectiveConfig =
+            {{{{LANE_WIDTH_NC,DSMP_DISABLE},
+                {LANE_WIDTH_NC,DSMP_DISABLE}},
+               {{LANE_WIDTH_NC,DSMP_DISABLE},
+                {LANE_WIDTH_NC,DSMP_DISABLE}}},
+               0x0,PHB_MASK_NA};
+
+        // Transform effective config to match lane config table format
+        for(size_t iop = 0;
+            iop < MAX_IOPS_PER_PROC;
+            ++iop)
+        {
+            for(size_t laneGroup = 0;
+                laneGroup < MAX_LANE_GROUPS_PER_IOP;
+                ++laneGroup)
+            {
+                effectiveConfig.laneSet[iop][laneGroup].width
+                    = _laneMaskToLaneWidth(effectiveLaneMask[iop][laneGroup]);
+                effectiveConfig.laneSet[iop][laneGroup].dsmp
+                    = dsmpCapable[iop][laneGroup];
+            }
+        }
+
+        const laneConfigRow* laneConfigItr =
+            std::find(
+                pLaneConfigTableBegin,
+                pLaneConfigTableEnd,
+                effectiveConfig);
+
+        if(laneConfigItr != pLaneConfigTableEnd)
+        {
+            iopConfig = laneConfigItr->laneConfig;
+            phbActiveMask = laneConfigItr->phbActive;
+
+            // Disable applicable PHBs
+            phbActiveMask &= (~disabledPhbs);
+            (void)_deconfigPhbsBasedOnPciState(
+                i_pProcChipTarget,
+                phbActiveMask);
+        }
+        else
+        {
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                ERR_MRK "computeProcPcieConfigAttrs> "
+                "Code bug! Proc PCIE IOP configuration not found.  Continuing "
+                "with no PHBs active.  "
+                "IOP0 Lane set 0: Lane mask = 0x%04X, DSMP enable = 0x%02X.  "
+                "IOP0 Lane set 1: Lane mask = 0x%04X, DSMP enable = 0x%02X.  ",
+                effectiveLaneMask[0][0],dsmpCapable[0][0],
+                effectiveLaneMask[0][1],dsmpCapable[0][1]);
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                "IOP1 Lane set 0: Lane mask = 0x%04X, DSMP enable = 0x%02X.  "
+                "IOP1 Lane set 1: Lane mask = 0x%04X, DSMP enable = 0x%02X.  ",
+                effectiveLaneMask[1][0],dsmpCapable[1][0],
+                effectiveLaneMask[1][1],dsmpCapable[1][1]);
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                "Proc chip target HUID = 0x%08X.",
+                i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>());
+            /*@
+             * @errortype
+             * @moduleid         ISTEP_COMPUTE_PCIE_CONFIG_ATTRS
+             * @reasoncode       ISTEP_INVALID_CONFIGURATION
+             * @userdata1[0:31]  Target processor chip's HUID
+             * @userdata1[32:39] IOP 0 lane set 0 DSMP enable
+             * @userdata1[40:47] IOP 0 lane set 1 DSMP enable
+             * @userdata1[48:55] IOP 1 lane set 0 DSMP enable
+             * @userdata1[56:63] IOP 1 lane set 1 DSMP enable
+             * @userdata2[0:15]  IOP 0 lane set 0 lane mask
+             * @userdata2[16:31] IOP 0 lane set 1 lane mask
+             * @userdata2[32:47] IOP 1 lane set 0 lane mask
+             * @userdata2[48:63] IOP 1 lane set 1 lane mask
+             * @devdesc          No valid PCIE IOP configuration found.  All
+             *                   PHBs on the processor will be disabled.
+             * @custdesc         A problem isolated to firmware or firmware
+             *                   customization occurred during the IPL of the
+             *                   system.
+             */
+            pError = new ERRORLOG::ErrlEntry(
+                ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+                ISTEP_COMPUTE_PCIE_CONFIG_ATTRS,
+                ISTEP_INVALID_CONFIGURATION,
+                TWO_UINT32_TO_UINT64(
+                    i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>(),
+                    FOUR_UINT8_TO_UINT32(
+                        dsmpCapable[0][0],
+                        dsmpCapable[0][1],
+                        dsmpCapable[1][0],
+                        dsmpCapable[1][1])),
+                FOUR_UINT16_TO_UINT64(
+                    effectiveLaneMask[0][0],
+                    effectiveLaneMask[0][1],
+                    effectiveLaneMask[1][0],
+                    effectiveLaneMask[1][1]),
+                true);
+            ERRORLOG::ErrlUserDetailsTarget(i_pProcChipTarget).addToLog(pError);
+            pError->collectTrace(ISTEP_COMP_NAME);
+            errlCommit(pError, ISTEP_COMP_ID);
+        }
+
+        i_pProcChipTarget->setAttr<
+            TARGETING::ATTR_PROC_PCIE_PHB_ACTIVE>(phbActiveMask);
+        i_pProcChipTarget->setAttr<
+            TARGETING::ATTR_PROC_PCIE_IOP_CONFIG>(iopConfig);
+
+    } while(0);
+
+    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+        EXIT_MRK "computeProcPcieConfigAttrs: EID = 0x%08X, PLID = 0x%08X, "
+        "RC = 0x%08X.",
+        ERRL_GETEID_SAFE(pError),ERRL_GETPLID_SAFE(pError),
+        ERRL_GETRC_SAFE(pError));
+
+    return pError;
+}
 
 //*****************************************************************************
 // wrapper function to call proc_pcie_scominit
@@ -791,8 +1573,7 @@ void*    call_proc_pcie_scominit( void    *io_pArgs )
     errlHndl_t          l_errl      =   NULL;
     IStepError          l_StepError;
 
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-        "call_proc_pcie_scominit entry" );
+    bool spBaseServicesEnabled = INITSERVICE::spBaseServicesEnabled();
 
     TARGETING::TargetHandleList l_procTargetList;
     getAllChips(l_procTargetList, TYPE_PROC);
@@ -802,7 +1583,30 @@ void*    call_proc_pcie_scominit( void    *io_pArgs )
           l_iter != l_procTargetList.end();
           ++l_iter )
     {
-        const TARGETING::Target*  l_proc_target = *l_iter;
+        TARGETING::Target* const l_proc_target = *l_iter;
+
+        // Compute the PCIE attribute config on all non-SP systems, since SP
+        // won't be there to do it.
+        if(!spBaseServicesEnabled)
+        {
+            // Unlike SP which operates on all present procs, the SP-less
+            // algorithm only needs to operate on functional ones
+            l_errl = computeProcPcieConfigAttrs(l_proc_target);
+            if(l_errl != NULL)
+            {
+                // Any failure to configure PCIE that makes it to this handler
+                // implies a firmware bug that should be fixed, everything else
+                // is tolerated internally (usually as disabled PHBs)
+                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                    ERR_MRK "call_proc_pcie_scominit> Failed in call to "
+                    "computeProcPcieConfigAttrs for target with HUID = "
+                    "0x%08X",
+                    l_proc_target->getAttr<TARGETING::ATTR_HUID>());
+                l_StepError.addErrorDetails(l_errl);
+                errlCommit( l_errl, ISTEP_COMP_ID );
+            }
+        }
+
         const fapi::Target l_fapi_proc_target( TARGET_TYPE_PROC_CHIP,
                 ( const_cast<TARGETING::Target*>(l_proc_target) ));
 
diff --git a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.H b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.H
index 92b28dc69..7907ae321 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.H
+++ b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.H
@@ -5,7 +5,9 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
+/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
@@ -104,6 +106,105 @@
 
 namespace   NEST_CHIPLETS
 {
+
+/**
+ *  @brief # of bits in a byte for computation purposes
+ */
+static const size_t BITS_PER_BYTE = 8;
+
+/**
+ *  @brief Container for holding IOPs to bifurcate
+ */
+typedef std::list<uint32_t> BifurcatedIopsContainer;
+
+/**
+ *  @brief Enum indicating number of usable IOP lanes for a proc
+ */
+enum IopLanesPerProc
+{
+    IOP_LANES_PER_PROC_24X = 24,// 24 Lanes per proc
+    IOP_LANES_PER_PROC_32X = 32 // 32 Lanes per proc
+};
+
+/**
+ *  @brief Struct for PCIE lane properties within IOP configuration table
+ */
+struct LaneSet
+{
+    uint8_t width; // Width of each PCIE lane set (0, 8, or 16)
+    uint8_t dsmp;  // Whether dSMP is enabled (0=disabled, 1=enabled)
+};
+
+/**
+ *  @brief Max possible IOPs per processor; invarient across all POWER8
+ *      processors
+ */
+static const size_t MAX_IOPS_PER_PROC = 2;
+
+/**
+ *  @brief Lane groups per IOP; invarient across all POWER8 processors
+ */
+static const size_t MAX_LANE_GROUPS_PER_IOP = 2;
+
+/**
+ *  @brief Struct for each row in PCIE IOP configuration table.
+ *      Used by code to compute the IOP config and PHBs active mask.
+ */
+struct laneConfigRow
+{
+    // Grouping of lanes under one IOP
+    LaneSet laneSet[MAX_IOPS_PER_PROC][MAX_LANE_GROUPS_PER_IOP];
+
+    // IOP config value from PCIE IOP configuration table
+    uint8_t laneConfig;
+
+    // PHB active mask (see PhbActiveMask enum)
+    // PHB0 = 0x80
+    // PHB1 = 0x40
+    // PHB1 = 0x20
+    uint8_t phbActive;
+};
+
+/**
+ *  @brief Enum indicating lane width (units = "number of lanes")
+ */
+enum LaneWidth
+{
+    LANE_WIDTH_NC  = 0,
+    LANE_WIDTH_8X  = 8,
+    LANE_WIDTH_16X = 16
+};
+
+/**
+ *  @brief Enum indicating whether lane set has DSMP Capability
+ */
+enum DsmpCapability
+{
+    DSMP_DISABLE = 0,
+    DSMP_ENABLE  = 1
+};
+
+/**
+ *  @brief Enumeration of lane mask values
+ */
+enum LaneMask
+{
+    LANE_MASK_X16     = 0xFFFF,
+    LANE_MASK_X8_GRP0 = 0xFF00,
+    LANE_MASK_X8_GRP1 = 0x00FF,
+};
+
+/**
+ *  @brief Enum giving bitmask values for enabled PHBs
+ */
+enum PhbActiveMask
+{
+    PHB_MASK_NA = 0x00, ///< Sentinel mask (loop terminations)
+    PHB0_MASK   = 0x80, ///< PHB0 enabled
+    PHB1_MASK   = 0x40, ///< PHB1 enabled
+    PHB2_MASK   = 0x20, ///< PHB2 enabled
+};
+
 /**
  *  @brief  call_proc_attr_update
  *
diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl
index 221f0d742..a13b4d204 100755
--- a/src/usr/targeting/common/genHwsvMrwXml.pl
+++ b/src/usr/targeting/common/genHwsvMrwXml.pl
@@ -2595,6 +2595,97 @@ sub generate_proc
                  $pcie_list{$ipath}{1}{0}{'lane-swap'}
         </default>
     </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_REVERSAL</id>
+        <default>
+            $pcie_list{$ipath}{0}{0}{'lane-reversal'},
+            $pcie_list{$ipath}{0}{1}{'lane-reversal'},
+            $pcie_list{$ipath}{1}{0}{'lane-reversal'},
+            $pcie_list{$ipath}{1}{1}{'lane-reversal'}
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK</id>
+        <default>
+            $pcie_list{$ipath}{0}{0}{'lane-mask'},
+            $pcie_list{$ipath}{0}{1}{'lane-mask'},
+            $pcie_list{$ipath}{1}{0}{'lane-mask'},
+            $pcie_list{$ipath}{1}{1}{'lane-mask'}
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_SWAP_NON_BIFURCATED</id>
+        <default>
+            $pcie_list{$ipath}{0}{0}{'lane-swap'},
+            $pcie_list{$ipath}{0}{1}{'lane-swap'},
+            $pcie_list{$ipath}{1}{0}{'lane-swap'},
+            $pcie_list{$ipath}{1}{1}{'lane-swap'}
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id>
+        <default>
+            $pcie_list{$ipath}{0}{0}{'lane-reversal'},
+            $pcie_list{$ipath}{0}{1}{'lane-reversal'},
+            $pcie_list{$ipath}{1}{0}{'lane-reversal'},
+            $pcie_list{$ipath}{1}{1}{'lane-reversal'}
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>
+            $pcie_list{$ipath}{0}{0}{'lane-mask'},
+            $pcie_list{$ipath}{0}{1}{'lane-mask'},
+            $pcie_list{$ipath}{1}{0}{'lane-mask'},
+            $pcie_list{$ipath}{1}{1}{'lane-mask'}
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_SWAP_BIFURCATED</id>
+        <default>
+            $bifurcation_list{$ipath}{0}{0}{'lane-swap'},
+            $bifurcation_list{$ipath}{0}{1}{'lane-swap'},
+            $bifurcation_list{$ipath}{1}{0}{'lane-swap'},
+            $bifurcation_list{$ipath}{1}{1}{'lane-swap'}
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_BIFURCATED</id>
+        <default>
+            $bifurcation_list{$ipath}{0}{0}{'lane-mask'},
+            $bifurcation_list{$ipath}{0}{1}{'lane-mask'},
+            $bifurcation_list{$ipath}{1}{0}{'lane-mask'},
+            $bifurcation_list{$ipath}{1}{1}{'lane-mask'}
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_REVERSAL_BIFURCATED</id>
+        <default>
+            $bifurcation_list{$ipath}{0}{0}{'lane-reversal'},
+            $bifurcation_list{$ipath}{0}{1}{'lane-reversal'},
+            $bifurcation_list{$ipath}{1}{0}{'lane-reversal'},
+            $bifurcation_list{$ipath}{1}{1}{'lane-reversal'}
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_DSMP_CAPABLE</id>
+        <default>
+            $pcie_list{$ipath}{0}{0}{'dsmp-capable'},
+            $pcie_list{$ipath}{0}{1}{'dsmp-capable'},
+            $pcie_list{$ipath}{1}{0}{'dsmp-capable'},
+            $pcie_list{$ipath}{1}{1}{'dsmp-capable'}
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IS_SLOT</id>
+        <default>
+            $pcie_list{$ipath}{0}{0}{'is-slot'},
+            $pcie_list{$ipath}{0}{1}{'is-slot'},
+            $pcie_list{$ipath}{1}{0}{'is-slot'},
+            $pcie_list{$ipath}{1}{1}{'is-slot'}
+        </default>
+    </attribute>
+
     <!-- End PROC_PCIE_ attributes -->\n";
 
     if ((scalar @SortedPmChipAttr) == 0)
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 72fa433d0..1a59b859d 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -14386,14 +14386,236 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
 </attribute>
 
 <attribute>
+    <id>IOP_LANES_PER_PROC</id>
+    <description>Number of PCIE lanes per processor
+        Creator: Targeting definition
+        Purpose: Determines which IOP configuration table is used to build the
+            PE lane config value and PHB active masks for the HWPs
+        Data format: value of 24 or 32 (lanes per processor)
+    </description>
+    <simpleType>
+        <uint8_t>
+        </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>PROC_PCIE_LANE_MASK</id>
+    <description>Effective PCIE Lane Mask
+        Creator: Firmware
+        Purpose: Holds the effective PCIE lane mask after taking into account
+            any IOP bifurcations.  If no IOP bifurcations present, this is just
+            the value of the PROC_PCIE_LANE_MASK_NON_BIFURCATED attribute
+        Data Format: 2x2 array of uint16_t values.  The first two uint16_t
+            values are lane set 0/1 masks for IOP0, the remaining two uint16_t
+            values are lane set 0/1 masks for IOP1.  A lane set mask indicates
+            which groups of lanes are assigned to an IOP.  For instance, lane
+            set 0 value of 0xFFFF and lane set 1 value of 0x0000 for IOP0 means
+            IOP0 is a x16. Lane set 0 value of 0xFF00 and lane set 1 value of
+            0x00FF for IOP0, means the IOP is bifurcated into two x8s.
+            Each index in the array that is non-0 will require a dedicated PHB.
+    </description>
+    <simpleType>
+        <uint16_t>
+        </uint16_t>
+        <array>2,2</array>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>PROC_PCIE_DSMP_CAPABLE</id>
+    <description>Whether DSMP is enabled for a lane set or not
+        Creator: MRW
+        Purpose: Indicates whether a given IOP / lane set is dedicated to dSMP
+            traffic or not
+        Data Format: 2x2 array of uint8_t values.  The first two uint8_t
+            values are for lane sets 0/1 of IOP0, the remaining two uint8_t
+            values are fpr lane sets 0/1 of IOP1.  If the value at a given
+            array index is 1, that IOP/lane set routes dSMP traffic.
+    </description>
+    <simpleType>
+        <uint8_t>
+        </uint8_t>
+        <array>2,2</array>
+        </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>PROC_PCIE_IOP_REVERSAL</id>
+    <description>Effective PCIE IOP reversal configuration
+        Creator: Firmware
+        Purpose: Holds the effective PCIE IOP reversal value after taking into
+            account any IOP bifurcations.  If no IOP bifurcations present, this
+            is just the value of the PROC_PCIE_IOP_REVERSAL_NON_BIFURCATED
+            attribute.
+        Data Format: 2x2 array of uint8_t values.  The first two uint8_t
+            values are for lane sets 0/1 of IOP0, the remaining two uint8_t
+            values are for lane sets 0/1 of IOP1.  The given index in the array
+            is a mask which specifies which bit to invert in the lane swap
+            settings for the given IOP/lane set.
+    </description>
+    <simpleType>
+        <uint8_t>
+        </uint8_t>
+        <array>2,2</array>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>PROC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id>
+    <description>Base PCIE IOP reversal configuration
+        Creator: Firmware
+        Purpose: Holds the base PCIE IOP reversal value without considering IOP
+            bifurcation.
+        Data Format: 2x2 array of uint8_t values.  The first two uint8_t
+            values are for lane sets 0/1 of IOP0, the remaining two uint8_t
+            values are for lane sets 0/1 of IOP1.  The given index in the array
+            is a mask which specifies which bit to invert in the lane swap
+            settings for the given IOP/lane set
+    </description>
+    <simpleType>
+        <uint8_t>
+        </uint8_t>
+        <array>2,2</array>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>PROC_PCIE_IOP_SWAP_NON_BIFURCATED</id>
+    <description>Base PCIE IOP swap configuration value
+        Creator: MRW
+        Purpose: Holds the base IOP swap configuration value without considering
+            IOP bifurcation.  The swap value controls how PCIE lanes are
+            recordered when the leave the IOP, to provide lane routing
+            flexibility.
+        Data Format: 2x2 array of uint8_t values.  The first two uint8_t
+            values are for lane sets 0/1 of IOP0, the remaining two uint8_t
+            values are for lane sets 0/1 of IOP1.  The given index in the array
+            is a value for the hardware which specifies how to swap the PCIE
+            lanes for the given IOP/lane set.
+    </description>
+    <simpleType>
+        <uint8_t></uint8_t>
+        <array>2,2</array>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+    <description>PCIE Lane Mask base configuration
+        Creator: MRW
+        Purpose: Holds the base PCIE lane mask assuming no dynamic IOP
+            bifurcations.
+        Data Format: 2x2 array of uint16_t values.  The first two uint16_t
+            values are for lane set 0/1 masks of IOP0, the remaining two
+            values are for lane set 0/1 masks of IOP1.  A lane set mask
+            indicates which groups of lanes are assigned to an IOP.  For
+            instance, lane set 0 value of 0xFFFF and lane set 1 value of 0x0000
+            for IOP0 means IOP0 is a x16. Lane set 0 value of 0xFF00 and lane
+            set 1 value of 0x00FF for IOP0, means the IOP is split into two x8s.
+            Each array index with non-0 value implies a dedicated PHB.
+    </description>
+    <simpleType>
+        <uint16_t>
+        </uint16_t>
+        <array>2,2</array>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>PROC_PCIE_IOP_REVERSAL_BIFURCATED</id>
+    <description>Base PCIE IOP reversal configuration
+        Creator: Firmware
+        Purpose: Holds the PCIE IOP reversal value for cases where the IOP
+            is bifurcated
+        Data Format: 2x2 array of uint8_t values.  The first two uint8_t
+            values are for lane sets 0/1 of IOP0, the remaining two uint8_t
+            values are for lane sets 0/1 of IOP1.  The given index in the array
+            is a mask which specifies which bit to invert in the lane swap
+            settings for the given IOP / lane set
+    </description>
+    <simpleType>
+        <uint8_t>
+        </uint8_t>
+        <array>2,2</array>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>PROC_PCIE_IOP_SWAP_BIFURCATED</id>
+    <description>Bifurcated PCIE IOP swap configuration value
+        Creator: MRW
+        Purpose: Holds the base IOP swap configuration value for the IOPs in the
+            case where they are bifurcated.  The swap value controls how PCIE
+            lanes are recordered when the leave the IOP, to provide lane routing
+            flexibility.
+        Data Format: 2x2 array of uint8_t values.  The first two uint8_t
+            values are for lane sets 0/1 of IOP0, the remaining two uint8_t
+            values are for lane sets 0/1 pf IOP1.  The given index in the array
+            is a value for the hardware which specifies how to swap the PCIE
+            lanes for the given IOP/lane set.
+    </description>
+    <simpleType>
+        <uint8_t></uint8_t>
+        <array>2,2</array>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
+    <id>PROC_PCIE_LANE_MASK_BIFURCATED</id>
+    <description>PCIE Lane Mask bifurcated configuration
+        Creator: MRW
+        Purpose: Holds the PCIE lane mask assuming IOPs are bifurcated.
+        Data Format: 2x2 array of uint16_t values.  The first two uint16_t
+            values are for lane set 0/1 masks of IOP0, the remaining two
+            values are for lane set 0/1 masks of IOP1.  A lane set mask
+            indicates which groups of lanes are assigned to an IOP.  For
+            instance, lane set 0 value of 0xFF00 and lane set 1 value of 0x00FF
+            for IOP0, means the IOP is bifurcated into two x8s.
+            Each non-0 array value implies a dedicated PHB.
+    </description>
+    <simpleType>
+        <uint16_t>
+        </uint16_t>
+        <array>2,2</array>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<attribute>
     <id>PROC_PCIE_LANE_EQUALIZATION</id>
     <description>PCIE Lane Equalization values for each PHB
-        creator: MRW
-        consumer: HDAT
-        firmware notes:
-        PCIE Lane Equalization values for each PHB
-        Array index: PHBs (0:3)
-                     Lane Settings (0:31)
+        Creator: MRW
+        Purpose: Holds settings which are loaded into the HW to optimize the
+            PCIE lane signal eye between the chips + PCIE endpoints
+        Data Format: 4 PHBs x 32 bytes of EQ data per PHB.  Each PHB has an EQ
+            value for each of its 16 lanes.  Each value is a uint16 formatted as
+            follows:
+                Bit 0:3   - up_rx_hint (bit 0 reserved)
+                Bit 4:7   - up_tx_preset
+                Bit 8:11  - dn_rx_hint (bit 0 reserved)
+                Bit 12:15 - dn_tx_preset
     </description>
     <simpleType>
         <uint8_t>
@@ -14404,5 +14626,96 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     <readable/>
 </attribute>
 
+<attribute>
+    <id>PROC_PCIE_IS_SLOT</id>
+    <description>Indicates whether PCIE lanes terminate at a pluggable slot
+        Creator: MRW
+        Purpose: Used by FW to know whether the given PCIE lanes terminate at a
+            pluggable slot or not.  If this is the case, and the platform
+            supports bifurcation, the card's VPD should be interrogated to
+            determine whether to bifurcate the IOP or not.
+        Data Format: 2x2 array of uint8_t values.  The first two values indicate
+            whether lane set 0/1 of IOP0 terminates at a pluggable slot.  The
+            next two values indicate the same for IOP1.  A value of 1 at a given
+            array index indicates the lanes terminate at a pluggable slot, 0
+            otherwise.
+    </description>
+    <simpleType>
+        <uint8_t>
+        </uint8_t>
+        <array>2,2</array>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
+<enumerationType>
+    <id>CDM_DOMAIN</id>
+    <description>
+        Enumeration specifying a target's CEC degraded mode domain
+    </description>
+    <enumerator>
+        <name>NONE</name>
+        <value>0</value>
+    </enumerator>
+    <enumerator>
+        <name>CPU</name>
+        <value>1</value>
+    </enumerator>
+    <enumerator>
+        <name>DIMM</name>
+        <value>2</value>
+    </enumerator>
+    <enumerator>
+        <name>FABRIC</name>
+        <value>3</value>
+    </enumerator>
+    <enumerator>
+        <name>MEM</name>
+        <value>4</value>
+    </enumerator>
+    <enumerator>
+        <name>IO</name>
+        <value>5</value>
+    </enumerator>
+    <enumerator>
+        <name>NODE</name>
+        <value>6</value>
+    </enumerator>
+    <enumerator>
+        <name>CLOCK</name>
+        <value>7</value>
+    </enumerator>
+    <enumerator>
+        <name>PSI</name>
+        <value>8</value>
+    </enumerator>
+    <enumerator>
+        <name>FSP</name>
+        <value>9</value>
+    </enumerator>
+    <enumerator>
+        <name>ALL</name>
+        <value>10</value>
+    </enumerator>
+    <default>NONE</default>
+</enumerationType>
+
+<attribute>
+    <id>CDM_DOMAIN</id>
+    <description>
+        Specifies a target's CEC degraded mode domain.  For example, all
+        DIMMs are part of the DIMM CEC degraded mode domain.
+    </description>
+    <simpleType>
+        <enumeration>
+            <id>CDM_DOMAIN</id>
+        </enumeration>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hasStringConversion/>
+</attribute>
+
 </attributes>
 
diff --git a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
index f006262e8..7e88f2ea2 100644
--- a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
@@ -709,6 +709,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFF00,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n0p0 EX units -->
@@ -1588,6 +1592,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFF00,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n0p1 EX units -->
@@ -2459,6 +2467,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFF00,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n0p2 EX units -->
@@ -3330,6 +3342,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFF00,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n0p3 EX units -->
diff --git a/src/usr/targeting/common/xmltohb/simics_NAPLES.system.xml b/src/usr/targeting/common/xmltohb/simics_NAPLES.system.xml
index 7c5da001c..6b1b2bf93 100644
--- a/src/usr/targeting/common/xmltohb/simics_NAPLES.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_NAPLES.system.xml
@@ -682,6 +682,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Naples n0p0 EX units -->
@@ -1541,6 +1545,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Naples n0p1 EX units -->
@@ -2391,6 +2399,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Naples n0p2 EX units -->
@@ -3241,6 +3253,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Naples n0p3 EX units -->
diff --git a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
index 84e5e6dd8..d20e6db99 100644
--- a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
@@ -676,6 +676,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p0 EX units -->
@@ -1907,6 +1911,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p1 EX units -->
@@ -3137,6 +3145,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p2 EX units -->
@@ -4367,6 +4379,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p3 EX units -->
@@ -5597,6 +5613,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p4 EX units -->
@@ -6796,6 +6816,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p5 EX units -->
@@ -7993,6 +8017,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p6 EX units -->
@@ -9190,6 +9218,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p7 EX units -->
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 993afb586..c9c84968e 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -501,6 +501,7 @@
         </default>
     </attribute>
     <attribute><id>PROC_PCIE_LANE_EQUALIZATION</id></attribute>
+    <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute>
 </targetType>
 
 <targetType>
@@ -536,6 +537,20 @@
     <attribute><id>PROC_PCIE_IOP_CONFIG</id></attribute>
     <attribute><id>PROC_PCIE_IOP_SWAP</id></attribute>
     <attribute><id>PROC_PCIE_PHB_ACTIVE</id></attribute>
+
+    <attribute><id>IOP_LANES_PER_PROC</id></attribute>
+    <attribute><id>PROC_PCIE_LANE_MASK</id></attribute>
+    <attribute><id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id></attribute>
+    <attribute><id>PROC_PCIE_LANE_MASK_BIFURCATED</id></attribute>
+    <attribute><id>PROC_PCIE_IOP_SWAP_NON_BIFURCATED</id></attribute>
+    <attribute><id>PROC_PCIE_IOP_SWAP_BIFURCATED</id></attribute>
+    <attribute><id>PROC_PCIE_IOP_REVERSAL</id></attribute>
+    <attribute><id>PROC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id></attribute>
+    <attribute><id>PROC_PCIE_IOP_REVERSAL_BIFURCATED</id></attribute>
+    <attribute><id>PROC_PCIE_DSMP_CAPABLE</id></attribute>
+    <attribute><id>PROC_PCIE_LANE_EQUALIZATION</id></attribute>
+    <attribute><id>PROC_PCIE_IS_SLOT</id></attribute>
+
     <attribute><id>PROC_PCIE_IOP_G3_PLL_CONTROL0</id></attribute>
     <attribute><id>PROC_PCIE_IOP_G2_PLL_CONTROL0</id></attribute>
     <attribute><id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0</id></attribute>
@@ -581,8 +596,6 @@
 
     <attribute><id>PROC_PCIE_IOP_TX_FFE_GEN1</id></attribute>
     <attribute><id>PROC_PCIE_IOP_TX_FFE_GEN2</id></attribute>
-
-
 </targetType>
 
 <targetType>
@@ -594,6 +607,10 @@
     </attribute>
     <attribute><id>DUMMY_RW</id></attribute>
     <attribute><id>DUMMY_HEAP_ZERO_DEFAULT</id></attribute>
+    <attribute>
+        <id>IOP_LANES_PER_PROC</id>
+        <default>32</default>
+    </attribute>
 </targetType>
 
 <targetType>
@@ -603,6 +620,10 @@
         <id>MODEL</id>
         <default>MURANO</default>
     </attribute>
+   <attribute>
+        <id>IOP_LANES_PER_PROC</id>
+        <default>24</default>
+   </attribute>
 </targetType>
 
 <targetType>
@@ -612,6 +633,10 @@
         <id>MODEL</id>
         <default>NAPLES</default>
     </attribute>
+   <attribute>
+        <id>IOP_LANES_PER_PROC</id>
+        <default>32</default>
+   </attribute>
 </targetType>
 
 <targetType>
@@ -682,6 +707,7 @@
     <attribute><id>OVERRIDE_MVPD_I_CS_LAB_CURRENT</id></attribute>
     <attribute><id>PM_SPWUP_IGNORE_XSTOP_FLAG</id></attribute>
     <attribute><id>FREQ_CORE</id></attribute>
+    <attribute><id>CDM_DOMAIN</id><default>CPU</default></attribute>
 </targetType>
 
 <targetType>
@@ -711,7 +737,6 @@
     </attribute>
 </targetType>
 
-
 <targetType>
     <id>unit-core-power8</id>
     <parent>unit</parent>
@@ -752,7 +777,6 @@
     </attribute>
 </targetType>
 
-
 <targetType>
     <id>unit-pci-power8</id>
     <parent>unit</parent>
@@ -764,6 +788,7 @@
     <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id>
         <default>0x00000001</default> <!--GARD -->
     </attribute>
+    <attribute><id>CDM_DOMAIN</id><default>IO</default></attribute>
 </targetType>
 
 <targetType>
@@ -793,7 +818,6 @@
     </attribute>
 </targetType>
 
-
 <targetType>
     <id>enc-node-power8</id>
     <parent>base</parent>
@@ -814,6 +838,7 @@
     <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id>
         <default>0x00000009</default> <!-- HOSTSVC_HBEL and GARD -->
     </attribute>
+    <attribute><id>CDM_DOMAIN</id><default>NODE</default></attribute>
 </targetType>
 
 <targetType>
@@ -833,6 +858,7 @@
     <attribute><id>EI_BUS_TX_MSBSWAP</id></attribute>
     <attribute><id>IS_INTER_ENCLOSURE_BUS</id></attribute>
     <attribute><id>PEER_PATH</id></attribute>
+    <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute>
 </targetType>
 
 <targetType>
@@ -875,6 +901,7 @@
     </attribute>
     <attribute><id>CHIP_UNIT</id></attribute>
     <attribute><id>PEER_TARGET</id></attribute>
+    <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute>
 </targetType>
 
 <targetType>
@@ -917,6 +944,7 @@
     <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id>
         <default>0x00000001</default> <!--GARD -->
     </attribute>
+    <attribute><id>CDM_DOMAIN</id><default>MEM</default></attribute>
 </targetType>
 
 <targetType>
@@ -1200,6 +1228,7 @@
     <attribute><id>MSS_DATABUS_UTIL_PER_MBA</id></attribute>
     <attribute><id>MSS_UTIL_N_PER_MBA</id></attribute>
     <attribute><id>MSS_EFF_VPD_VERSION</id></attribute>
+    <attribute><id>CDM_DOMAIN</id><default>MEM</default></attribute>
 </targetType>
 
 <targetType>
@@ -1218,6 +1247,7 @@
     <attribute><id>DMI_REFCLOCK_SWIZZLE</id></attribute>
     <attribute><id>EI_BUS_TX_MSBSWAP</id></attribute>
     <attribute><id>DMI_DFE_OVERRIDE</id></attribute>
+    <attribute><id>CDM_DOMAIN</id><default>MEM</default></attribute>
 </targetType>
 
 <targetType>
@@ -1374,6 +1404,7 @@
     <attribute><id>VPD_ISDIMMTOC4DQ</id></attribute>
     <attribute><id>VPD_ISDIMMTOC4DQS</id></attribute>
     <attribute><id>MSS_POWER_CONTROL_REQUESTED</id></attribute>
+    <attribute><id>CDM_DOMAIN</id><default>MEM</default></attribute>
 </targetType>
 
 <!-- Centaur L4 -->
@@ -1446,6 +1477,7 @@
 
     <attribute><id>VPD_REC_NUM</id></attribute>
     <attribute><id>MSS_EFF_VPD_VERSION</id></attribute>
+    <attribute><id>CDM_DOMAIN</id><default>DIMM</default></attribute>
 </targetType>
 
 <targetType>
@@ -1482,6 +1514,7 @@
             <field><id>reserved</id><value>0</value></field>
         </default>
     </attribute>
+    <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute>
 </targetType>
 
 <targetType>
@@ -1531,6 +1564,7 @@
             <field><id>reserved</id><value>0</value></field>
         </default>
     </attribute>
+    <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute>
 </targetType>
 
 <targetType>
diff --git a/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml b/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml
index 51a1bec8d..c42d97233 100644
--- a/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml
+++ b/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml
@@ -520,6 +520,10 @@
         <id>PROC_PCIE_PHB_ACTIVE</id>
         <default>0xE0</default>
     </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFF00,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n0p0 EX units
@@ -960,6 +964,10 @@
     <attribute><id>RNG_BASE_ADDR</id>
         <default>0x0003FFFF40001000</default>
     </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFF00,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n0p1 EX units
@@ -1384,6 +1392,10 @@
     <attribute><id>RNG_BASE_ADDR</id>
         <default>0x0003FFFF40002000</default>
     </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFF00,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n2p0 EX units
@@ -1809,6 +1821,10 @@
     <attribute><id>RNG_BASE_ADDR</id>
         <default>0x0003FFFF40003000</default>
     </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFF00,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n2p1 EX units
diff --git a/src/usr/targeting/common/xmltohb/vbu_NAPLES.system.xml b/src/usr/targeting/common/xmltohb/vbu_NAPLES.system.xml
index bf10d5860..732d0e7ef 100644
--- a/src/usr/targeting/common/xmltohb/vbu_NAPLES.system.xml
+++ b/src/usr/targeting/common/xmltohb/vbu_NAPLES.system.xml
@@ -516,6 +516,10 @@
         <id>PROC_PCIE_PHB_ACTIVE</id>
         <default>0xE0</default>
     </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Naples n0p0 EX units
@@ -962,6 +966,10 @@
     <attribute><id>RNG_BASE_ADDR</id>
         <default>0x0003FFFF40001000</default>
     </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Naples n0p1 EX units
@@ -1386,6 +1394,10 @@
     <attribute><id>RNG_BASE_ADDR</id>
         <default>0x0003FFFF40002000</default>
     </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Naples n2p0 EX units
@@ -1811,6 +1823,10 @@
     <attribute><id>RNG_BASE_ADDR</id>
         <default>0x0003FFFF40003000</default>
     </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Naples n2p1 EX units
diff --git a/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml b/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml
index 9d1f507c2..4b9703a2c 100644
--- a/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml
+++ b/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml
@@ -579,6 +579,10 @@
         <default>0</default>
     </attribute>
     <!-- End PM_ attributes -->
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p0 EX units -->
@@ -1680,6 +1684,10 @@
         <default>0</default>
     </attribute>
     <!-- End PM_ attributes -->
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p1 EX units -->