Change PHY WC register block to functional API

Change-Id: I808ecfdfb573658d1fff126b1d52fca353b2297b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23034
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23036
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 316 insertions, 283 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H
index e56dd36ca..248a8cbcb 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H
@@ -115,325 +115,358 @@ class wcTraits<fapi2::TARGET_TYPE_MCA>
 
 };
 
+namespace wc
+{
 ///
-/// @class mss::wc
-/// @brief Write Control Class, encapsulates the WC registers
-/// @tparam T fapi2 Target Type
+/// @brief Read WC_CONFIG0
+/// @tparam T fapi2 Target Type - derived
 /// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
 ///
 template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
-class wc_class
+inline fapi2::ReturnCode read_config0( const fapi2::Target<T>& i_target,
+                                       fapi2::buffer<uint64_t>& o_data )
 {
-    public:
+    FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG0_REG, o_data) );
+    FAPI_DBG("wc_config0: 0x%016llx", o_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
 
-        ///
-        /// @brief Read WC_CONFIG0
-        /// @param[in] i_target the fapi2 target of the port
-        /// @param[out] o_data the value of the register
-        /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode read_config0( const fapi2::Target<T>& i_target,
-                fapi2::buffer<uint64_t>& o_data )
-        {
-            FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG0_REG, o_data) );
-            FAPI_DBG("wc_config0: 0x%016llx", o_data);
-        fapi_try_exit:
-            return fapi2::current_err;
-        }
-
-        ///
-        /// @brief Write WC_CONFIG0
-        /// @param[in] i_target the fapi2 target of the port
-        /// @param[in] i_data the value of the register
-        /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode write_config0( const fapi2::Target<T>& i_target,
-                const fapi2::buffer<uint64_t>& i_data )
-        {
-            FAPI_DBG("wc_config0: 0x%016llx", i_data);
-            FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG0_REG, i_data) );
-        fapi_try_exit:
-            return fapi2::current_err;
-        }
-
-
-        ///
-        /// @brief Read WC_CONFIG1
-        /// @param[in] i_target the fapi2 target of the port
-        /// @param[out] o_data the value of the register
-        /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode read_config1( const fapi2::Target<T>& i_target,
-                fapi2::buffer<uint64_t>& o_data )
-        {
-            FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG1_REG, o_data) );
-            FAPI_DBG("wc_config1: 0x%016llx", o_data);
-        fapi_try_exit:
-            return fapi2::current_err;
-        }
-
-        ///
-        /// @brief Write WC_CONFIG1
-        /// @param[in] i_target the fapi2 target of the port
-        /// @param[in] i_data the value of the register
-        /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode write_config1( const fapi2::Target<T>& i_target,
-                const fapi2::buffer<uint64_t>& i_data )
-        {
-            FAPI_DBG("wc_config1: 0x%016llx", i_data);
-            FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG1_REG, i_data) );
-        fapi_try_exit:
-            return fapi2::current_err;
-        }
-
-        ///
-        /// @brief Read WC_CONFIG2
-        /// @param[in] i_target the fapi2 target of the port
-        /// @param[out] o_data the value of the register
-        /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode read_config2( const fapi2::Target<T>& i_target,
-                fapi2::buffer<uint64_t>& o_data )
-        {
-            FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG2_REG, o_data) );
-            FAPI_DBG("wc_config2: 0x%016llx", o_data);
-        fapi_try_exit:
-            return fapi2::current_err;
-        }
-
-        ///
-        /// @brief Write WC_CONFIG2
-        /// @param[in] i_target the fapi2 target of the port
-        /// @param[in] i_data the value of the register
-        /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode write_config2( const fapi2::Target<T>& i_target,
-                const fapi2::buffer<uint64_t>& i_data )
-        {
-            FAPI_DBG("wc_config2: 0x%016llx", i_data);
-            FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG2_REG, i_data) );
-        fapi_try_exit:
-            return fapi2::current_err;
-        }
-
-
-        ///
-        /// @brief Read WC_CONFIG3
-        /// @param[in] i_target the fapi2 target of the port
-        /// @param[out] o_data the value of the register
-        /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode read_config3( const fapi2::Target<T>& i_target,
-                fapi2::buffer<uint64_t>& o_data )
-        {
-            FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG3_REG, o_data) );
-            FAPI_DBG("wc_config3: 0x%016llx", o_data);
-        fapi_try_exit:
-            return fapi2::current_err;
-        }
-
-        ///
-        /// @brief Write WC_CONFIG3
-        /// @param[in] i_target the fapi2 target of the port
-        /// @param[in] i_data the value of the register
-        /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode write_config3( const fapi2::Target<T>& i_target,
-                const fapi2::buffer<uint64_t>& i_data )
-        {
-            FAPI_DBG("wc_config3: 0x%016llx", i_data);
-            FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG3_REG, i_data) );
-        fapi_try_exit:
-            return fapi2::current_err;
-        }
-
-
-        ///
-        /// @brief Read WC_RTT_WR_SWAP_ENABLE
-        /// @param[in] i_target the fapi2 target of the port
-        /// @param[out] o_data the value of the register
-        /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode read_rtt_wr_swap_enable( const fapi2::Target<T>& i_target,
-                fapi2::buffer<uint64_t>& o_data )
-        {
-            FAPI_TRY( mss::getScom(i_target, TT::WC_RTT_WR_SWAP_ENABLE_REG, o_data) );
-            FAPI_DBG("wc_rtt_wr_swap_enable: 0x%016llx", o_data);
-        fapi_try_exit:
-            return fapi2::current_err;
-        }
-
-        ///
-        /// @brief Write WC_RTT_WR_SWAP_ENABLE
-        /// @param[in] i_target the fapi2 target of the port
-        /// @param[in] i_data the value of the register
-        /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode write_rtt_wr_swap_enable( const fapi2::Target<T>& i_target,
-                const fapi2::buffer<uint64_t>& i_data )
-        {
-            FAPI_DBG("wc_rtt_wr_swap_enable: 0x%016llx", i_data);
-            FAPI_TRY( mss::putScom(i_target, TT::WC_RTT_WR_SWAP_ENABLE_REG, i_data) );
-        fapi_try_exit:
-            return fapi2::current_err;
-        }
-
-        ///
-        /// @brief reset wc_config0
-        /// @param[in] i_target, fapi2 target of the port
-        /// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode reset_config0( const fapi2::Target<T>& i_target )
-        {
-            fapi2::buffer<uint64_t> l_data;
-            uint8_t l_is_sim = 0;
-            FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_is_sim) );
+///
+/// @brief Write WC_CONFIG0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode write_config0( const fapi2::Target<T>& i_target,
+                                        const fapi2::buffer<uint64_t>& i_data )
+{
+    FAPI_DBG("wc_config0: 0x%016llx", i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG0_REG, i_data) );
+fapi_try_exit:
+    return fapi2::current_err;
+}
 
-            // This is a simplification - in sim we don't have DQS wire delays so we don't acccount for them BRS
-            l_data.insertFromRight<TT::TWLO_TWLOE, TT::TWLO_TWLOE_LEN>(mss::twlo_twloe(i_target));
 
-            // WL_ONE_DQS_PULSE = enable (one pulse)
-            l_data.setBit<TT::WL_ONE_DQS_PULSE>();
+///
+/// @brief Read WC_CONFIG1
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode read_config1( const fapi2::Target<T>& i_target,
+                                       fapi2::buffer<uint64_t>& o_data )
+{
+    FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG1_REG, o_data) );
+    FAPI_DBG("wc_config1: 0x%016llx", o_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
 
-            // FW_WR_RD [same formula as RD_WR? max(tWTR+11,AL+tRTP+3), ATTR_EFF_DRAM_AL(0,1,2)]
-            // 57:62, 0b000000, (def_is_sim);   # is this max?
-            // 57:62, 0b100000, any;   # dd0 = 17 clocks, now 32 from SWyatt
-            {
-                const uint64_t FW_WR_RD = l_is_sim ? 0b000000 : 0b100000;
-                l_data.insertFromRight<TT::FW_WR_RD, TT::FW_WR_RD_LEN>(FW_WR_RD);
-            }
+///
+/// @brief Write WC_CONFIG1
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode write_config1( const fapi2::Target<T>& i_target,
+                                        const fapi2::buffer<uint64_t>& i_data )
+{
+    FAPI_DBG("wc_config1: 0x%016llx", i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG1_REG, i_data) );
+fapi_try_exit:
+    return fapi2::current_err;
+}
 
-            // 63, 0b0, any;       # CUSTOM_INIT_WRITE
-            l_data.clearBit<TT::CUSTOM_INIT_WRITE>();
+///
+/// @brief Read WC_CONFIG2
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode read_config2( const fapi2::Target<T>& i_target,
+                                       fapi2::buffer<uint64_t>& o_data )
+{
+    FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG2_REG, o_data) );
+    FAPI_DBG("wc_config2: 0x%016llx", o_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
 
-            FAPI_DBG("wc_config0 reset 0x%llx (tWLO_tWLOE: %d)", l_data, mss::twlo_twloe(i_target));
-            FAPI_TRY( write_config0(i_target, l_data) );
+///
+/// @brief Write WC_CONFIG2
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode write_config2( const fapi2::Target<T>& i_target,
+                                        const fapi2::buffer<uint64_t>& i_data )
+{
+    FAPI_DBG("wc_config2: 0x%016llx", i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG2_REG, i_data) );
+fapi_try_exit:
+    return fapi2::current_err;
+}
 
-        fapi_try_exit:
-            return fapi2::current_err;
 
-        }
+///
+/// @brief Read WC_CONFIG3
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode read_config3( const fapi2::Target<T>& i_target,
+                                       fapi2::buffer<uint64_t>& o_data )
+{
+    FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG3_REG, o_data) );
+    FAPI_DBG("wc_config3: 0x%016llx", o_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
 
-        ///
-        /// @brief reset wc_config1
-        /// @param[in] i_target, fapi2 target of the port
-        /// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode reset_config1( const fapi2::Target<T>& i_target )
-        {
-            // Reset WC_CONFIG1 with the values directly from the PHY databook
-            fapi2::buffer<uint64_t> l_data;
-
-            l_data.insertFromRight<TT::BIG_STEP, TT::BIG_STEP_LEN>(WR_LVL_BIG_STEP);
-            l_data.insertFromRight<TT::SMALL_STEP, TT::SMALL_STEP_LEN>(WR_LVL_SMALL_STEP);
-            l_data.insertFromRight<TT::WR_PRE_DLY, TT::WR_PRE_DLY_LEN>(WR_LVL_PRE_DLY);
-
-            FAPI_DBG("wc_config1 reset 0x%llx (big 0x%x small 0x%x wr_pre_dly 0x%x)",
-                     l_data, WR_LVL_BIG_STEP, WR_LVL_SMALL_STEP, WR_LVL_PRE_DLY);
-            FAPI_TRY( write_config1(i_target, l_data) );
-
-        fapi_try_exit:
-            return fapi2::current_err;
-        }
-
-        ///
-        /// @brief reset wc_config2
-        /// @param[in] i_target, fapi2 target of the port
-        /// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode reset_config2( const fapi2::Target<T>& i_target )
-        {
-            fapi2::buffer<uint64_t> l_data;
+///
+/// @brief Write WC_CONFIG3
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode write_config3( const fapi2::Target<T>& i_target,
+                                        const fapi2::buffer<uint64_t>& i_data )
+{
+    FAPI_DBG("wc_config3: 0x%016llx", i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG3_REG, i_data) );
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+
+///
+/// @brief Read WC_RTT_WR_SWAP_ENABLE
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode read_rtt_wr_swap_enable( const fapi2::Target<T>& i_target,
+        fapi2::buffer<uint64_t>& o_data )
+{
+    FAPI_TRY( mss::getScom(i_target, TT::WC_RTT_WR_SWAP_ENABLE_REG, o_data) );
+    FAPI_DBG("wc_rtt_wr_swap_enable: 0x%016llx", o_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
 
-            l_data.insertFromRight<TT::NUM_VALID_SAMPLES, TT::NUM_VALID_SAMPLES_LEN>(WR_LVL_NUM_VALID_SAMPLES);
-            l_data.insertFromRight<TT::FW_RD_WR, TT::FW_RD_WR_LEN>(WR_CNTR_FW_RD_WR);
+///
+/// @brief Write WC_RTT_WR_SWAP_ENABLE
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode write_rtt_wr_swap_enable( const fapi2::Target<T>& i_target,
+        const fapi2::buffer<uint64_t>& i_data )
+{
+    FAPI_DBG("wc_rtt_wr_swap_enable: 0x%016llx", i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::WC_RTT_WR_SWAP_ENABLE_REG, i_data) );
+fapi_try_exit:
+    return fapi2::current_err;
+}
 
-            FAPI_DBG("wc_config2 reset 0x%llx", l_data);
-            FAPI_TRY( write_config2(i_target, l_data) );
+///
+/// @brief reset wc_config0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode reset_config0( const fapi2::Target<T>& i_target )
+{
+    fapi2::buffer<uint64_t> l_data;
+    uint8_t l_is_sim = 0;
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_is_sim) );
 
-        fapi_try_exit:
-            return fapi2::current_err;
-        }
+    // This is a simplification - in sim we don't have DQS wire delays so we don't acccount for them BRS
+    l_data.insertFromRight<TT::TWLO_TWLOE, TT::TWLO_TWLOE_LEN>(mss::twlo_twloe(i_target));
 
-        ///
-        /// @brief reset wc_config3
-        /// @param[in] i_target, fapi2 target of the port
-        /// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode reset_config3( const fapi2::Target<T>& i_target )
-        {
-            fapi2::buffer<uint64_t> l_data;
-            uint8_t l_is_sim = 0;
-            FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_is_sim) );
+    // WL_ONE_DQS_PULSE = enable (one pulse)
+    l_data.setBit<TT::WL_ONE_DQS_PULSE>();
 
-            // MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON is 0's
+    // FW_WR_RD [same formula as RD_WR? max(tWTR+11,AL+tRTP+3), ATTR_EFF_DRAM_AL(0,1,2)]
+    // 57:62, 0b000000, (def_is_sim);   # is this max?
+    // 57:62, 0b100000, any;   # dd0 = 17 clocks, now 32 from SWyatt
+    {
+        const uint64_t FW_WR_RD = l_is_sim ? 0b000000 : 0b100000;
+        l_data.insertFromRight<TT::FW_WR_RD, TT::FW_WR_RD_LEN>(FW_WR_RD);
+    }
 
-            // 55:60, 0b000000, (def_is_sim); # MRS_CMD_DQ_OFF        !!
-            // 55:60, 0b111111, any   ;       # MRS_CMD_DQ_OFF        !!
-            {
-                const uint64_t CMD_DQ_OFF = l_is_sim ? 0b000000 : 0b111111;
-                l_data.insertFromRight<TT::MRS_CMD_DQ_OFF, TT::MRS_CMD_DQ_OFF_LEN>(CMD_DQ_OFF);
-            }
+    // 63, 0b0, any;       # CUSTOM_INIT_WRITE
+    l_data.clearBit<TT::CUSTOM_INIT_WRITE>();
 
-            FAPI_DBG("wc_config3 reset 0x%llx", l_data);
-            FAPI_TRY( write_config3(i_target, l_data) );
+    FAPI_DBG("wc_config0 reset 0x%llx (tWLO_tWLOE: %d)", l_data, mss::twlo_twloe(i_target));
+    FAPI_TRY( write_config0(i_target, l_data) );
 
-        fapi_try_exit:
-            return fapi2::current_err;
+fapi_try_exit:
+    return fapi2::current_err;
 
-        }
+}
 
+///
+/// @brief reset wc_config1
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode reset_config1( const fapi2::Target<T>& i_target )
+{
+    // Reset WC_CONFIG1 with the values directly from the PHY databook
+    fapi2::buffer<uint64_t> l_data;
 
-        ///
-        /// @brief reset wc_rtt_wr_swap_enable
-        /// @param[in] i_target, fapi2 target of the port
-        /// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode reset_rtt_wr_swap_enable( const fapi2::Target<T>& i_target )
-        {
-            fapi2::buffer<uint64_t> l_data;
+    l_data.insertFromRight<TT::BIG_STEP, TT::BIG_STEP_LEN>(WR_LVL_BIG_STEP);
+    l_data.insertFromRight<TT::SMALL_STEP, TT::SMALL_STEP_LEN>(WR_LVL_SMALL_STEP);
+    l_data.insertFromRight<TT::WR_PRE_DLY, TT::WR_PRE_DLY_LEN>(WR_LVL_PRE_DLY);
 
-            FAPI_TRY( read_rtt_wr_swap_enable(i_target, l_data) );
+    FAPI_DBG("wc_config1 reset 0x%llx (big 0x%x small 0x%x wr_pre_dly 0x%x)",
+             l_data, WR_LVL_BIG_STEP, WR_LVL_SMALL_STEP, WR_LVL_PRE_DLY);
+    FAPI_TRY( write_config1(i_target, l_data) );
 
-            // Per John Bialas 1/16: The enable RTT_SWAP bit is causing problems.
-            l_data.clearBit<TT::RTT_WR_SWAP_ENABLE_P0_WL>();
-            l_data.setBit<TT::RTT_WR_SWAP_ENABLE_P0_CTR>();
+fapi_try_exit:
+    return fapi2::current_err;
+}
 
-            FAPI_DBG("wc_rtt_wr_swap_enable reset 0x%llx", l_data);
-            FAPI_TRY( write_rtt_wr_swap_enable(i_target, l_data) );
+///
+/// @brief reset wc_config2
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode reset_config2( const fapi2::Target<T>& i_target )
+{
+    fapi2::buffer<uint64_t> l_data;
 
-        fapi_try_exit:
-            return fapi2::current_err;
+    l_data.insertFromRight<TT::NUM_VALID_SAMPLES, TT::NUM_VALID_SAMPLES_LEN>(WR_LVL_NUM_VALID_SAMPLES);
+    l_data.insertFromRight<TT::FW_RD_WR, TT::FW_RD_WR_LEN>(WR_CNTR_FW_RD_WR);
 
-        }
+    FAPI_DBG("wc_config2 reset 0x%llx", l_data);
+    FAPI_TRY( write_config2(i_target, l_data) );
 
-        ///
-        /// @brief reset wc
-        /// @param[in] i_target, fapi2 target of the port
-        /// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
-        ///
-        static inline fapi2::ReturnCode reset( const fapi2::Target<T>& i_target )
-        {
-            FAPI_TRY( reset_config0(i_target) );
-            FAPI_TRY( reset_config1(i_target) );
-            FAPI_TRY( reset_config2(i_target) );
-            FAPI_TRY( reset_config3(i_target) );
+fapi_try_exit:
+    return fapi2::current_err;
+}
 
-            FAPI_TRY( reset_rtt_wr_swap_enable(i_target) );
+///
+/// @brief reset wc_config3
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode reset_config3( const fapi2::Target<T>& i_target )
+{
+    fapi2::buffer<uint64_t> l_data;
+    uint8_t l_is_sim = 0;
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_is_sim) );
 
-        fapi_try_exit:
-            return fapi2::current_err;
-        }
+    // MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON is 0's
 
+    // 55:60, 0b000000, (def_is_sim); # MRS_CMD_DQ_OFF        !!
+    // 55:60, 0b111111, any   ;       # MRS_CMD_DQ_OFF        !!
+    {
+        const uint64_t CMD_DQ_OFF = l_is_sim ? 0b000000 : 0b111111;
+        l_data.insertFromRight<TT::MRS_CMD_DQ_OFF, TT::MRS_CMD_DQ_OFF_LEN>(CMD_DQ_OFF);
+    }
 
-};
+    FAPI_DBG("wc_config3 reset 0x%llx", l_data);
+    FAPI_TRY( write_config3(i_target, l_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+
+///
+/// @brief reset wc_rtt_wr_swap_enable
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode reset_rtt_wr_swap_enable( const fapi2::Target<T>& i_target )
+{
+    fapi2::buffer<uint64_t> l_data;
+
+    FAPI_TRY( read_rtt_wr_swap_enable(i_target, l_data) );
+
+    // Per John Bialas 1/16: The enable RTT_SWAP bit is causing problems.
+    l_data.clearBit<TT::RTT_WR_SWAP_ENABLE_P0_WL>();
+    l_data.setBit<TT::RTT_WR_SWAP_ENABLE_P0_CTR>();
 
-// Touch of sugar here to allow mss::wc::<api>. When we support
-// other targets (not just MCA) we will need to remove the default
-// template argument for wc_class and we can just rename the class
-// then to wc.
-using wc = wc_class<fapi2::TARGET_TYPE_MCA>;
+    FAPI_DBG("wc_rtt_wr_swap_enable reset 0x%llx", l_data);
+    FAPI_TRY( write_rtt_wr_swap_enable(i_target, l_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+///
+/// @brief reset wc
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode reset( const fapi2::Target<T>& i_target )
+{
+    FAPI_TRY( reset_config0(i_target) );
+    FAPI_TRY( reset_config1(i_target) );
+    FAPI_TRY( reset_config2(i_target) );
+    FAPI_TRY( reset_config3(i_target) );
+
+    FAPI_TRY( reset_rtt_wr_swap_enable(i_target) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+
+}
 
 }