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| author | Alex Taft <amtaft@us.ibm.com> | 2017-04-23 13:55:51 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-05-03 11:07:28 -0400 |
| commit | 0454abc3ae5785821f1806496eafbce2807ab7c0 (patch) | |
| tree | 35bc5f851a810e0b0f1a8b19a957dfa36c3f60fb /src | |
| parent | 16ce1e16c3458b4ca5189fe4e9060164a7c12e7f (diff) | |
| download | talos-hostboot-0454abc3ae5785821f1806496eafbce2807ab7c0.tar.gz talos-hostboot-0454abc3ae5785821f1806496eafbce2807ab7c0.zip | |
L3 initfile updates
1) L3_CERRS_LRU_DECR_PROB_SEL_CFG should be left at default value
and not altered
3) HW375255 should be applied to all systems since rejected by ccb
4) rddsp_demotion_init_lru_cnt_cfg performance chages
Change-Id: Ic36f360da342c8f98e940642b15111d0540ddfc6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39577
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39607
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 35 |
1 files changed, 18 insertions, 17 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index a2d0eb322..85e8495f2 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -1256,23 +1256,6 @@ </attribute> <!-- ******************************************************************** --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_HW375255</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - Nimbus DD1 only: HW375255; Defer to DD2: Rd mach goes inactive without sending PF data bypass to L2 - </description> - <chipEcFeature> - <chip> - <name>ENUM_ATTR_NAME_NIMBUS</name> - <ec> - <value>0x20</value> - <test>LESS_THAN</test> - </ec> - </chip> - </chipEcFeature> - </attribute> - <!-- ******************************************************************** --> - <attribute> <id>ATTR_CHIP_EC_FEATURE_SRAM_RELAXED_SETTINGS</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -1958,6 +1941,24 @@ </attribute> <!-- ******************************************************************** --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW405880_LCO_IN_RETENTION</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nimbus DD1; set to 0b000 + Numbus DD2+; set to 0b110 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_OPTIMAL_LCO_SCAN_ONLY</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> |
