diff options
| author | Ben Gass <bgass@us.ibm.com> | 2015-12-04 10:17:50 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-03-05 17:53:51 -0500 |
| commit | fea64fafb4689217c509e7aa9b737ebd38a85f9d (patch) | |
| tree | 98e5a04f2ac272e5d4eac8fc1d5b02e0bb1ba1d0 /src | |
| parent | 0974e974565b33378aecbee11a6789a9101293f0 (diff) | |
| download | talos-hostboot-fea64fafb4689217c509e7aa9b737ebd38a85f9d.tar.gz talos-hostboot-fea64fafb4689217c509e7aa9b737ebd38a85f9d.zip | |
Intermediate updates for header files.
Added include to p9_const to _fld.H files
Correct NPU constant names
Correct some PB constant names
Change-Id: I4b3ca94847ee65b0c15f031932c9deda45b27147
Original-Change-Id: I0eb9fda9f5386bd8fbd4dad7a406405a2d81dfdd
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22464
Tested-by: Jenkins Server
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21731
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H | 1159 |
1 files changed, 894 insertions, 265 deletions
diff --git a/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H index 579074ff9..6abee95c3 100644 --- a/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H +++ b/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H @@ -25,6 +25,9 @@ // *HWP Team: SOA // *HWP Level: 1 // *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE + +#include <p9_const_common.H> + #ifndef __P9_MISC_SCOM_ADDRESSES_FLD_H #define __P9_MISC_SCOM_ADDRESSES_FLD_H @@ -756,6 +759,24 @@ REG64_FLD( PU_MCD1_BANK0_MCD_VGC_MASK_AGV_DISABLE_MODE , 36 , SH_UN REG64_FLD( PU_MCD1_BANK0_MCD_VGC_XLATE_TO_ADDR_ID_ENABLE , 37 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_XLATE_TO_ADDR_ID_ENABLE ); +REG64_FLD( PEC_STACK2_BARE_REG_PE_MMIO_BAR0_EN , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , + SH_FLD_PE_MMIO_BAR0_EN ); +REG64_FLD( PEC_STACK2_BARE_REG_PE_MMIO_BAR1_EN , 1 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , + SH_FLD_PE_MMIO_BAR1_EN ); +REG64_FLD( PEC_STACK2_BARE_REG_PE_PHB_BAR_EN , 2 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , + SH_FLD_PE_PHB_BAR_EN ); +REG64_FLD( PEC_STACK2_BARE_REG_PE_INT_BAR_EN , 3 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , + SH_FLD_PE_INT_BAR_EN ); + +REG64_FLD( PEC_STACK1_BARE_REG_PE_MMIO_BAR0_EN , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , + SH_FLD_PE_MMIO_BAR0_EN ); +REG64_FLD( PEC_STACK1_BARE_REG_PE_MMIO_BAR1_EN , 1 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , + SH_FLD_PE_MMIO_BAR1_EN ); +REG64_FLD( PEC_STACK1_BARE_REG_PE_PHB_BAR_EN , 2 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , + SH_FLD_PE_PHB_BAR_EN ); +REG64_FLD( PEC_STACK1_BARE_REG_PE_INT_BAR_EN , 3 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , + SH_FLD_PE_INT_BAR_EN ); + REG64_FLD( PHB_BARE_REG_PE_MMIO_BAR0_EN , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_MMIO_BAR0_EN ); REG64_FLD( PHB_BARE_REG_PE_MMIO_BAR1_EN , 1 , SH_UNT_PHB , SH_ACS_SCOM_RW , @@ -765,6 +786,15 @@ REG64_FLD( PHB_BARE_REG_PE_PHB_BAR_EN , 2 , SH_UN REG64_FLD( PHB_BARE_REG_PE_INT_BAR_EN , 3 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_INT_BAR_EN ); +REG64_FLD( PEC_STACK0_BARE_REG_PE_MMIO_BAR0_EN , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , + SH_FLD_PE_MMIO_BAR0_EN ); +REG64_FLD( PEC_STACK0_BARE_REG_PE_MMIO_BAR1_EN , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , + SH_FLD_PE_MMIO_BAR1_EN ); +REG64_FLD( PEC_STACK0_BARE_REG_PE_PHB_BAR_EN , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , + SH_FLD_PE_PHB_BAR_EN ); +REG64_FLD( PEC_STACK0_BARE_REG_PE_INT_BAR_EN , 3 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , + SH_FLD_PE_INT_BAR_EN ); + REG64_FLD( PU_BCDE_CTL_STOP , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STOP ); REG64_FLD( PU_BCDE_CTL_START , 1 , SH_UNT , SH_ACS_SCOM , @@ -33774,11 +33804,26 @@ REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_22E , 22 , SH_UN REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_23E , 23 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREE_USAGE_23E ); +REG64_FLD( PEC_STACK2_CQSTAT_REG_PE_INBOUND_ACTIVE , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PE_INBOUND_ACTIVE ); +REG64_FLD( PEC_STACK2_CQSTAT_REG_PE_OUTBOUND_ACTIVE , 1 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PE_OUTBOUND_ACTIVE ); + +REG64_FLD( PEC_STACK1_CQSTAT_REG_PE_INBOUND_ACTIVE , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PE_INBOUND_ACTIVE ); +REG64_FLD( PEC_STACK1_CQSTAT_REG_PE_OUTBOUND_ACTIVE , 1 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PE_OUTBOUND_ACTIVE ); + REG64_FLD( PHB_CQSTAT_REG_PE_INBOUND_ACTIVE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RO , SH_FLD_PE_INBOUND_ACTIVE ); REG64_FLD( PHB_CQSTAT_REG_PE_OUTBOUND_ACTIVE , 1 , SH_UNT_PHB , SH_ACS_SCOM_RO , SH_FLD_PE_OUTBOUND_ACTIVE ); +REG64_FLD( PEC_STACK0_CQSTAT_REG_PE_INBOUND_ACTIVE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RO , + SH_FLD_PE_INBOUND_ACTIVE ); +REG64_FLD( PEC_STACK0_CQSTAT_REG_PE_OUTBOUND_ACTIVE , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RO , + SH_FLD_PE_OUTBOUND_ACTIVE ); + REG64_FLD( PU_CSAR_SRAM_ADDRESS , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_ADDRESS ); REG64_FLD( PU_CSAR_SRAM_ADDRESS_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , @@ -40188,14 +40233,14 @@ REG64_FLD( PU_FIR_ACTION0_REG_ACTION0 , 0 , SH_UN REG64_FLD( PU_FIR_ACTION0_REG_ACTION0_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); -REG64_FLD( _SM0_FIR_ACTION0_REG_0_0 , 0 , SH_UNT__SM0 , SH_ACS_SCOM_RW , +REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION0_REG_0_0 , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , SH_FLD_0 ); -REG64_FLD( _SM0_FIR_ACTION0_REG_0_0_LEN , 64 , SH_UNT__SM0 , SH_ACS_SCOM_RW , +REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION0_REG_0_0_LEN , 64 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , SH_FLD_0_LEN ); -REG64_FLD( _SM2_FIR_ACTION0_REG_1_1 , 0 , SH_UNT__SM2 , SH_ACS_SCOM_RW , +REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION0_REG_1_1 , 0 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_RW , SH_FLD_1 ); -REG64_FLD( _SM2_FIR_ACTION0_REG_1_1_LEN , 64 , SH_UNT__SM2 , SH_ACS_SCOM_RW , +REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION0_REG_1_1_LEN , 64 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_RW , SH_FLD_1_LEN ); REG64_FLD( CAPP_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_CAPP , SH_ACS_SCOM_RO , @@ -40213,14 +40258,14 @@ REG64_FLD( PU_FIR_ACTION1_REG_ACTION1 , 0 , SH_UN REG64_FLD( PU_FIR_ACTION1_REG_ACTION1_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); -REG64_FLD( _SM0_FIR_ACTION1_REG_0_0 , 0 , SH_UNT__SM0 , SH_ACS_SCOM_RW , +REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION1_REG_0_0 , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , SH_FLD_0 ); -REG64_FLD( _SM0_FIR_ACTION1_REG_0_0_LEN , 64 , SH_UNT__SM0 , SH_ACS_SCOM_RW , +REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION1_REG_0_0_LEN , 64 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , SH_FLD_0_LEN ); -REG64_FLD( _SM2_FIR_ACTION1_REG_1_1 , 0 , SH_UNT__SM2 , SH_ACS_SCOM_RW , +REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION1_REG_1_1 , 0 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_RW , SH_FLD_1 ); -REG64_FLD( _SM2_FIR_ACTION1_REG_1_1_LEN , 64 , SH_UNT__SM2 , SH_ACS_SCOM_RW , +REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION1_REG_1_1_LEN , 64 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_RW , SH_FLD_1_LEN ); REG64_FLD( PEC_FIR_MASK_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , @@ -40454,14 +40499,14 @@ REG64_FLD( PU_FIR_MASK_REGISTER_WRT_RST_INTRPT_FACES , 25 , SH_UN REG64_FLD( PU_FIR_MASK_REGISTER_RD_RST_INTRPT_FACES , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_RD_RST_INTRPT_FACES ); -REG64_FLD( _SM0_FIR_MASK_REG_0_0 , 0 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_MASK_REG_0_0 , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_0 ); -REG64_FLD( _SM0_FIR_MASK_REG_0_0_LEN , 64 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_MASK_REG_0_0_LEN , 64 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_0_LEN ); -REG64_FLD( _SM2_FIR_MASK_REG_1_1 , 0 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_MASK_REG_1_1 , 0 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_1 ); -REG64_FLD( _SM2_FIR_MASK_REG_1_1_LEN , 64 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_MASK_REG_1_1_LEN , 64 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_1_LEN ); REG64_FLD( CAPP_FIR_REG_BAR_PE , 0 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , @@ -40584,262 +40629,262 @@ REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR , 5 , SH_UN REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR_CLONE , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); -REG64_FLD( _SM0_FIR_REG_0_NTL_ARRAY_CE , 0 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_ARRAY_CE , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_ARRAY_CE ); -REG64_FLD( _SM0_FIR_REG_0_NTL_ARRAY_HDR_UE , 1 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_ARRAY_HDR_UE , 1 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_ARRAY_HDR_UE ); -REG64_FLD( _SM0_FIR_REG_0_NTL_ARRAY_DATA_UE , 2 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_ARRAY_DATA_UE , 2 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_ARRAY_DATA_UE ); -REG64_FLD( _SM0_FIR_REG_0_NTL_NVL_FLIT_PERR , 3 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_FLIT_PERR , 3 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_NVL_FLIT_PERR ); -REG64_FLD( _SM0_FIR_REG_0_NTL_NVL_DATA_PERR , 4 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_DATA_PERR , 4 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_NVL_DATA_PERR ); -REG64_FLD( _SM0_FIR_REG_0_NTL_NVL_PKT_MALFOR , 5 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_PKT_MALFOR , 5 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_NVL_PKT_MALFOR ); -REG64_FLD( _SM0_FIR_REG_0_NTL_NVL_PKT_UNSUPPORTED , 6 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_PKT_UNSUPPORTED , 6 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_NVL_PKT_UNSUPPORTED ); -REG64_FLD( _SM0_FIR_REG_0_NTL_NVL_CONFIG_ERR , 7 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_CONFIG_ERR , 7 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_NVL_CONFIG_ERR ); -REG64_FLD( _SM0_FIR_REG_0_NTL_NVL_CRC_ERR , 8 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_CRC_ERR , 8 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_NVL_CRC_ERR ); -REG64_FLD( _SM0_FIR_REG_0_NTL_PRI_ERR , 9 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_PRI_ERR , 9 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_PRI_ERR ); -REG64_FLD( _SM0_FIR_REG_0_NTL_LOGIC_ERR , 10 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_LOGIC_ERR , 10 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_LOGIC_ERR ); -REG64_FLD( _SM0_FIR_REG_0_NTL_LMD_POISON , 11 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_LMD_POISON , 11 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_LMD_POISON ); -REG64_FLD( _SM0_FIR_REG_0_NTL_ARRAY_DATA_SUE , 12 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_ARRAY_DATA_SUE , 12 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_ARRAY_DATA_SUE ); -REG64_FLD( _SM0_FIR_REG_0_CTL_ARRAY_CE , 13 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_ARRAY_CE , 13 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_ARRAY_CE ); -REG64_FLD( _SM0_FIR_REG_0_CTL_PBUS_RECOV_ERR , 14 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PBUS_RECOV_ERR , 14 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_PBUS_RECOV_ERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_RING_ERR , 15 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_RING_ERR , 15 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_RING_ERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_MMIO_ST_DATA_UE , 16 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_MMIO_ST_DATA_UE , 16 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_MMIO_ST_DATA_UE ); -REG64_FLD( _SM0_FIR_REG_0_CTL_PEF , 17 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PEF , 17 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_PEF ); -REG64_FLD( _SM0_FIR_REG_0_CTL_NVL_CFG_ERR , 18 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_NVL_CFG_ERR , 18 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_NVL_CFG_ERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_NVL_FATAL_ERR , 19 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_NVL_FATAL_ERR , 19 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_NVL_FATAL_ERR ); -REG64_FLD( _SM0_FIR_REG_0_RESERVED_1 , 20 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_RESERVED_1 , 20 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_RESERVED_1 ); -REG64_FLD( _SM0_FIR_REG_0_CTL_ARRAY_UE , 21 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_ARRAY_UE , 21 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_ARRAY_UE ); -REG64_FLD( _SM0_FIR_REG_0_CTL_PBUS_PERR , 22 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PBUS_PERR , 22 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_PBUS_PERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_PBUS_FATAL_ERR , 23 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PBUS_FATAL_ERR , 23 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_PBUS_FATAL_ERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_PBUS_CONFIG_ERR , 24 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PBUS_CONFIG_ERR , 24 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_PBUS_CONFIG_ERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_FWD_PROGRESS_ERR , 25 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_FWD_PROGRESS_ERR , 25 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_FWD_PROGRESS_ERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_LOGIC_ERR , 26 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_LOGIC_ERR , 26 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_LOGIC_ERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_PEST_DIS , 27 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PEST_DIS , 27 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_PEST_DIS ); -REG64_FLD( _SM0_FIR_REG_0_CTL_RSVD_15 , 28 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_RSVD_15 , 28 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_RSVD_15 ); -REG64_FLD( _SM0_FIR_REG_0_DAT_DATA_BE_UE , 29 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_DATA_BE_UE , 29 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_DATA_BE_UE ); -REG64_FLD( _SM0_FIR_REG_0_DAT_DATA_BE_CE , 30 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_DATA_BE_CE , 30 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_DATA_BE_CE ); -REG64_FLD( _SM0_FIR_REG_0_DAT_DATA_BE_PERR , 31 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_DATA_BE_PERR , 31 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_DATA_BE_PERR ); -REG64_FLD( _SM0_FIR_REG_0_DAT_CREG_PERR , 32 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_CREG_PERR , 32 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_CREG_PERR ); -REG64_FLD( _SM0_FIR_REG_0_DAT_RTAG_PERR , 33 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_RTAG_PERR , 33 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_RTAG_PERR ); -REG64_FLD( _SM0_FIR_REG_0_DAT_STATE_PERR , 34 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_STATE_PERR , 34 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_STATE_PERR ); -REG64_FLD( _SM0_FIR_REG_0_DAT_LOGIC_ERR , 35 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_LOGIC_ERR , 35 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_LOGIC_ERR ); -REG64_FLD( _SM0_FIR_REG_0_DAT_DATA_BE_SUE , 36 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_DATA_BE_SUE , 36 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_DATA_BE_SUE ); -REG64_FLD( _SM0_FIR_REG_0_DAT_PBRX_SUE , 37 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_PBRX_SUE , 37 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_PBRX_SUE ); -REG64_FLD( _SM0_FIR_REG_0_DAT_RSVD_9 , 38 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_RSVD_9 , 38 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_RSVD_9 ); -REG64_FLD( _SM0_FIR_REG_0_DAT_RSVD_10 , 39 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_RSVD_10 , 39 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_RSVD_10 ); -REG64_FLD( _SM0_FIR_REG_0_XTS_INT , 40 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_INT , 40 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_INT ); -REG64_FLD( _SM0_FIR_REG_0_XTS_SRAM_CE , 41 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_SRAM_CE , 41 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_SRAM_CE ); -REG64_FLD( _SM0_FIR_REG_0_XTS_SRAM_UE , 42 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_SRAM_UE , 42 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_SRAM_UE ); -REG64_FLD( _SM0_FIR_REG_0_XTS_PROTOCOL_CE , 43 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_PROTOCOL_CE , 43 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_PROTOCOL_CE ); -REG64_FLD( _SM0_FIR_REG_0_XTS_PROTOCOL_UE , 44 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_PROTOCOL_UE , 44 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_PROTOCOL_UE ); -REG64_FLD( _SM0_FIR_REG_0_XTS_PBUS_PROTOCOL , 45 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_PBUS_PROTOCOL , 45 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_PBUS_PROTOCOL ); -REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_6 , 46 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_6 , 46 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_6 ); -REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_7 , 47 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_7 , 47 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_7 ); -REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_8 , 48 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_8 , 48 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_8 ); -REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_9 , 49 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_9 , 49 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_9 ); -REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_10 , 50 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_10 , 50 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_10 ); -REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_11 , 51 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_11 , 51 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_11 ); -REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_12 , 52 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_12 , 52 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_12 ); -REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_13 , 53 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_13 , 53 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_13 ); -REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_14 , 54 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_14 , 54 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_14 ); -REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_15 , 55 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_15 , 55 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_15 ); -REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_16 , 56 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_16 , 56 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_16 ); -REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_17 , 57 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_17 , 57 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_17 ); -REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_18 , 58 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_18 , 58 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_18 ); -REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_19 , 59 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_19 , 59 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_19 ); -REG64_FLD( _SM0_FIR_REG_0_SCOMSAT00_ERR , 60 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_SCOMSAT00_ERR , 60 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOMSAT00_ERR ); -REG64_FLD( _SM0_FIR_REG_0_SCOMSAT01_ERR , 61 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_SCOMSAT01_ERR , 61 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOMSAT01_ERR ); -REG64_FLD( _SM0_FIR_REG_0_PARITY_ERR2 , 62 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_PARITY_ERR2 , 62 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR2 ); -REG64_FLD( _SM0_FIR_REG_0_PARITY_ERR , 63 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_PARITY_ERR , 63 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR ); -REG64_FLD( _SM2_FIR_REG_1_NDL_BRK0_STALL , 0 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK0_STALL , 0 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK0_STALL ); -REG64_FLD( _SM2_FIR_REG_1_NDL_BRK0_NOSTALL , 1 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK0_NOSTALL , 1 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK0_NOSTALL ); -REG64_FLD( _SM2_FIR_REG_1_NDL_BRK1_STALL , 2 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK1_STALL , 2 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK1_STALL ); -REG64_FLD( _SM2_FIR_REG_1_NDL_BRK1_NOSTALL , 3 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK1_NOSTALL , 3 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK1_NOSTALL ); -REG64_FLD( _SM2_FIR_REG_1_NDL_BRK2_STALL , 4 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK2_STALL , 4 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK2_STALL ); -REG64_FLD( _SM2_FIR_REG_1_NDL_BRK2_NOSTALL , 5 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK2_NOSTALL , 5 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK2_NOSTALL ); -REG64_FLD( _SM2_FIR_REG_1_NDL_BRK3_STALL , 6 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK3_STALL , 6 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK3_STALL ); -REG64_FLD( _SM2_FIR_REG_1_NDL_BRK3_NOSTALL , 7 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK3_NOSTALL , 7 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK3_NOSTALL ); -REG64_FLD( _SM2_FIR_REG_1_NDL_BRK4_STALL , 8 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK4_STALL , 8 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK4_STALL ); -REG64_FLD( _SM2_FIR_REG_1_NDL_BRK4_NOSTALL , 9 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK4_NOSTALL , 9 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK4_NOSTALL ); -REG64_FLD( _SM2_FIR_REG_1_NDL_BRK5_STALL , 10 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK5_STALL , 10 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK5_STALL ); -REG64_FLD( _SM2_FIR_REG_1_NDL_BRK5_NOSTALL , 11 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK5_NOSTALL , 11 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK5_NOSTALL ); -REG64_FLD( _SM2_FIR_REG_1_MISC_RING_ERR , 12 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_MISC_RING_ERR , 12 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_MISC_RING_ERR ); -REG64_FLD( _SM2_FIR_REG_1_MISC_INT_RA_PERR , 13 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_MISC_INT_RA_PERR , 13 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_MISC_INT_RA_PERR ); -REG64_FLD( _SM2_FIR_REG_1_MISC_DA_ADDR_PERR , 14 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_MISC_DA_ADDR_PERR , 14 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_MISC_DA_ADDR_PERR ); -REG64_FLD( _SM2_FIR_REG_1_MISC_CTRL_PERR , 15 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_MISC_CTRL_PERR , 15 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_MISC_CTRL_PERR ); -REG64_FLD( _SM2_FIR_REG_1_MISC_NMMU_ERR , 16 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_MISC_NMMU_ERR , 16 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_MISC_NMMU_ERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TVT_ENTRY_INVALID , 17 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TVT_ENTRY_INVALID , 17 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TVT_ENTRY_INVALID ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TVT_ADDR_RANGE_ERR , 18 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TVT_ADDR_RANGE_ERR , 18 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TVT_ADDR_RANGE_ERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TCE_PAGE_ACCESS_CA_ERR , 19 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TCE_PAGE_ACCESS_CA_ERR , 19 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TCE_PAGE_ACCESS_CA_ERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TCE_CACHE_MULT_HIT_ERR , 20 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TCE_CACHE_MULT_HIT_ERR , 20 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TCE_CACHE_MULT_HIT_ERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TCE_PAGE_ACCESS_TW_ERR , 21 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TCE_PAGE_ACCESS_TW_ERR , 21 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TCE_PAGE_ACCESS_TW_ERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TCE_REQ_TO_ERR , 22 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TCE_REQ_TO_ERR , 22 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TCE_REQ_TO_ERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TCD_PERR , 23 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TCD_PERR , 23 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TCD_PERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TDR_PERR , 24 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TDR_PERR , 24 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TDR_PERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_AT_EA_UE , 25 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_EA_UE , 25 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_EA_UE ); -REG64_FLD( _SM2_FIR_REG_1_ATS_AT_EA_CE , 26 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_EA_CE , 26 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_EA_CE ); -REG64_FLD( _SM2_FIR_REG_1_ATS_AT_TDRMEM_UE , 27 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_TDRMEM_UE , 27 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_TDRMEM_UE ); -REG64_FLD( _SM2_FIR_REG_1_ATS_AT_TDRMEM_CE , 28 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_TDRMEM_CE , 28 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_TDRMEM_CE ); -REG64_FLD( _SM2_FIR_REG_1_ATS_AT_RSPOUT_UE , 29 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_RSPOUT_UE , 29 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_RSPOUT_UE ); -REG64_FLD( _SM2_FIR_REG_1_ATS_AT_RSPOUT_CE , 30 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_RSPOUT_CE , 30 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_RSPOUT_CE ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TVT_PERR , 31 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TVT_PERR , 31 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TVT_PERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_IODA_ADDR_PERR , 32 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_IODA_ADDR_PERR , 32 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_IODA_ADDR_PERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_NPU_CTRL_PERR , 33 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_NPU_CTRL_PERR , 33 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_NPU_CTRL_PERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_NPU_TOR_PERR , 34 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_NPU_TOR_PERR , 34 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_NPU_TOR_PERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_INVAL_IODA_TBL_SEL , 35 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_INVAL_IODA_TBL_SEL , 35 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_INVAL_IODA_TBL_SEL ); -REG64_FLD( _SM2_FIR_REG_1_ATS_RSVD_19 , 36 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_RSVD_19 , 36 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_RSVD_19 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_37 , 37 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_37 , 37 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_37 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_38 , 38 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_38 , 38 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_38 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_39 , 39 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_39 , 39 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_39 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_40 , 40 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_40 , 40 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_40 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_41 , 41 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_41 , 41 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_41 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_42 , 42 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_42 , 42 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_42 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_43 , 43 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_43 , 43 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_43 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_44 , 44 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_44 , 44 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_44 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_45 , 45 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_45 , 45 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_45 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_46 , 46 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_46 , 46 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_46 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_47 , 47 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_47 , 47 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_47 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_48 , 48 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_48 , 48 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_48 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_49 , 49 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_49 , 49 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_49 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_50 , 50 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_50 , 50 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_50 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_51 , 51 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_51 , 51 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_51 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_52 , 52 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_52 , 52 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_52 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_53 , 53 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_53 , 53 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_53 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_54 , 54 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_54 , 54 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_54 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_55 , 55 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_55 , 55 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_55 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_56 , 56 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_56 , 56 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_56 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_57 , 57 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_57 , 57 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_57 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_58 , 58 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_58 , 58 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_58 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_59 , 59 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_59 , 59 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_59 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_60 , 60 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_60 , 60 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_60 ); -REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_61 , 61 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_61 , 61 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_61 ); -REG64_FLD( _SM2_FIR_REG_1_PARITY_ERR2 , 62 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_PARITY_ERR2 , 62 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR2 ); -REG64_FLD( _SM2_FIR_REG_1_PARITY_ERR , 63 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_PARITY_ERR , 63 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR ); REG64_FLD( PEC_FIR_STATUS_REG_HSSCALERR , 0 , SH_UNT_PEC , SH_ACS_SCOM2_OR , @@ -40922,14 +40967,14 @@ REG64_FLD( PEC_FIR_WOF_REG_WOF , 0 , SH_UN REG64_FLD( PEC_FIR_WOF_REG_WOF_LEN , 37 , SH_UNT_PEC , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LEN ); -REG64_FLD( _SM0_FIR_WOF_REG_0_0 , 0 , SH_UNT__SM0 , SH_ACS_SCOM_WCLRREG, +REG64_FLD( PU_NPU_MSC_SM0_FIR_WOF_REG_0_0 , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_0 ); -REG64_FLD( _SM0_FIR_WOF_REG_0_0_LEN , 64 , SH_UNT__SM0 , SH_ACS_SCOM_WCLRREG, +REG64_FLD( PU_NPU_MSC_SM0_FIR_WOF_REG_0_0_LEN , 64 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_0_LEN ); -REG64_FLD( _SM2_FIR_WOF_REG_1_1 , 0 , SH_UNT__SM2 , SH_ACS_SCOM_WCLRREG, +REG64_FLD( PU_NPU_MSC_SM2_FIR_WOF_REG_1_1 , 0 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_WCLRREG, SH_FLD_1 ); -REG64_FLD( _SM2_FIR_WOF_REG_1_1_LEN , 64 , SH_UNT__SM2 , SH_ACS_SCOM_WCLRREG, +REG64_FLD( PU_NPU_MSC_SM2_FIR_WOF_REG_1_1_LEN , 64 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_WCLRREG, SH_FLD_1_LEN ); REG64_FLD( CAPP_FLUSHCPIG_FLUSH_CP_IG_STATE_MAP , 0 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -44422,11 +44467,26 @@ REG64_FLD( PEC_INJECT_REG_THERM_MODE , 2 , SH_UN REG64_FLD( PEC_INJECT_REG_THERM_MODE_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_THERM_MODE_LEN ); +REG64_FLD( PEC_STACK2_INTBAR_REG_PE_INT_BAR , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , + SH_FLD_PE_INT_BAR ); +REG64_FLD( PEC_STACK2_INTBAR_REG_PE_INT_BAR_LEN , 28 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , + SH_FLD_PE_INT_BAR_LEN ); + +REG64_FLD( PEC_STACK1_INTBAR_REG_PE_INT_BAR , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , + SH_FLD_PE_INT_BAR ); +REG64_FLD( PEC_STACK1_INTBAR_REG_PE_INT_BAR_LEN , 28 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , + SH_FLD_PE_INT_BAR_LEN ); + REG64_FLD( PHB_INTBAR_REG_PE_INT_BAR , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_INT_BAR ); REG64_FLD( PHB_INTBAR_REG_PE_INT_BAR_LEN , 28 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_INT_BAR_LEN ); +REG64_FLD( PEC_STACK0_INTBAR_REG_PE_INT_BAR , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , + SH_FLD_PE_INT_BAR ); +REG64_FLD( PEC_STACK0_INTBAR_REG_PE_INT_BAR_LEN , 28 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , + SH_FLD_PE_INT_BAR_LEN ); + REG64_FLD( PU_INTERRUPTS_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_INTERRUPTS_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , @@ -50468,26 +50528,86 @@ REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK , 48 , SH_UN REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK_LEN , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DMA_WR_VG_RESET_TIMER_MASK_LEN ); +REG64_FLD( PEC_STACK2_MMIOBAR0_MASK_REG_PE_MMIO_MASK0 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , + SH_FLD_PE_MMIO_MASK0 ); +REG64_FLD( PEC_STACK2_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN , 40 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , + SH_FLD_PE_MMIO_MASK0_LEN ); + +REG64_FLD( PEC_STACK1_MMIOBAR0_MASK_REG_PE_MMIO_MASK0 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , + SH_FLD_PE_MMIO_MASK0 ); +REG64_FLD( PEC_STACK1_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN , 40 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , + SH_FLD_PE_MMIO_MASK0_LEN ); + REG64_FLD( PHB_MMIOBAR0_MASK_REG_PE_MMIO_MASK0 , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK0 ); REG64_FLD( PHB_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN , 40 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK0_LEN ); +REG64_FLD( PEC_STACK0_MMIOBAR0_MASK_REG_PE_MMIO_MASK0 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , + SH_FLD_PE_MMIO_MASK0 ); +REG64_FLD( PEC_STACK0_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN , 40 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , + SH_FLD_PE_MMIO_MASK0_LEN ); + +REG64_FLD( PEC_STACK2_MMIOBAR0_REG_PE_MMIO_BAR0 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , + SH_FLD_PE_MMIO_BAR0 ); +REG64_FLD( PEC_STACK2_MMIOBAR0_REG_PE_MMIO_BAR0_LEN , 40 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , + SH_FLD_PE_MMIO_BAR0_LEN ); + +REG64_FLD( PEC_STACK1_MMIOBAR0_REG_PE_MMIO_BAR0 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , + SH_FLD_PE_MMIO_BAR0 ); +REG64_FLD( PEC_STACK1_MMIOBAR0_REG_PE_MMIO_BAR0_LEN , 40 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , + SH_FLD_PE_MMIO_BAR0_LEN ); + REG64_FLD( PHB_MMIOBAR0_REG_PE_MMIO_BAR0 , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR0 ); REG64_FLD( PHB_MMIOBAR0_REG_PE_MMIO_BAR0_LEN , 40 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR0_LEN ); +REG64_FLD( PEC_STACK0_MMIOBAR0_REG_PE_MMIO_BAR0 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , + SH_FLD_PE_MMIO_BAR0 ); +REG64_FLD( PEC_STACK0_MMIOBAR0_REG_PE_MMIO_BAR0_LEN , 40 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , + SH_FLD_PE_MMIO_BAR0_LEN ); + +REG64_FLD( PEC_STACK2_MMIOBAR1_MASK_REG_PE_MMIO_MASK1 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , + SH_FLD_PE_MMIO_MASK1 ); +REG64_FLD( PEC_STACK2_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN , 40 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , + SH_FLD_PE_MMIO_MASK1_LEN ); + +REG64_FLD( PEC_STACK1_MMIOBAR1_MASK_REG_PE_MMIO_MASK1 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , + SH_FLD_PE_MMIO_MASK1 ); +REG64_FLD( PEC_STACK1_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN , 40 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , + SH_FLD_PE_MMIO_MASK1_LEN ); + REG64_FLD( PHB_MMIOBAR1_MASK_REG_PE_MMIO_MASK1 , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK1 ); REG64_FLD( PHB_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN , 40 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK1_LEN ); +REG64_FLD( PEC_STACK0_MMIOBAR1_MASK_REG_PE_MMIO_MASK1 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , + SH_FLD_PE_MMIO_MASK1 ); +REG64_FLD( PEC_STACK0_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN , 40 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , + SH_FLD_PE_MMIO_MASK1_LEN ); + +REG64_FLD( PEC_STACK2_MMIOBAR1_REG_PE_MMIO_BAR1 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , + SH_FLD_PE_MMIO_BAR1 ); +REG64_FLD( PEC_STACK2_MMIOBAR1_REG_PE_MMIO_BAR1_LEN , 40 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , + SH_FLD_PE_MMIO_BAR1_LEN ); + +REG64_FLD( PEC_STACK1_MMIOBAR1_REG_PE_MMIO_BAR1 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , + SH_FLD_PE_MMIO_BAR1 ); +REG64_FLD( PEC_STACK1_MMIOBAR1_REG_PE_MMIO_BAR1_LEN , 40 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , + SH_FLD_PE_MMIO_BAR1_LEN ); + REG64_FLD( PHB_MMIOBAR1_REG_PE_MMIO_BAR1 , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR1 ); REG64_FLD( PHB_MMIOBAR1_REG_PE_MMIO_BAR1_LEN , 40 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR1_LEN ); +REG64_FLD( PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , + SH_FLD_PE_MMIO_BAR1 ); +REG64_FLD( PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1_LEN , 40 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , + SH_FLD_PE_MMIO_BAR1_LEN ); + REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_BKINV_INTERLOCK_DIS , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_BKINV_INTERLOCK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_LFSR_DIS , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -51247,16 +51367,252 @@ REG64_FLD( PU_NPU1_SM0_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UN REG64_FLD( PU_NPU1_SM0_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_NDT1_RESERVED2_LEN ); +REG64_FLD( PEC_STACK0_NET_CTRL0_CHIPLET_ENABLE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_CHIPLET_ENABLE ); +REG64_FLD( PEC_STACK0_NET_CTRL0_PCB_EP_RESET , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_PCB_EP_RESET ); +REG64_FLD( PEC_STACK0_NET_CTRL0_CLK_ASYNC_RESET , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_CLK_ASYNC_RESET ); +REG64_FLD( PEC_STACK0_NET_CTRL0_PLL_TEST_EN , 3 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_PLL_TEST_EN ); +REG64_FLD( PEC_STACK0_NET_CTRL0_PLL_RESET , 4 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_PLL_RESET ); +REG64_FLD( PEC_STACK0_NET_CTRL0_PLL_BYPASS , 5 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_PLL_BYPASS ); +REG64_FLD( PEC_STACK0_NET_CTRL0_VITAL_SCAN , 6 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_VITAL_SCAN ); +REG64_FLD( PEC_STACK0_NET_CTRL0_VITAL_SCAN_IN , 7 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_VITAL_SCAN_IN ); +REG64_FLD( PEC_STACK0_NET_CTRL0_VITAL_PHASE , 8 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_VITAL_PHASE ); +REG64_FLD( PEC_STACK0_NET_CTRL0_FLUSH_ALIGN_OVR , 9 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_FLUSH_ALIGN_OVR ); +REG64_FLD( PEC_STACK0_NET_CTRL0_VITAL_AL , 10 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_VITAL_AL ); +REG64_FLD( PEC_STACK0_NET_CTRL0_ACT_DIS , 11 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_ACT_DIS ); +REG64_FLD( PEC_STACK0_NET_CTRL0_MPW1 , 12 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_MPW1 ); +REG64_FLD( PEC_STACK0_NET_CTRL0_MPW2 , 13 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_MPW2 ); +REG64_FLD( PEC_STACK0_NET_CTRL0_MPW3 , 14 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_MPW3 ); +REG64_FLD( PEC_STACK0_NET_CTRL0_DELAY_LCLKR , 15 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_DELAY_LCLKR ); +REG64_FLD( PEC_STACK0_NET_CTRL0_VITAL_THOLD , 16 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_VITAL_THOLD ); +REG64_FLD( PEC_STACK0_NET_CTRL0_FLUSH_SCAN_N , 17 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_FLUSH_SCAN_N ); +REG64_FLD( PEC_STACK0_NET_CTRL0_FENCE_EN , 18 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_FENCE_EN ); +REG64_FLD( PEC_STACK0_NET_CTRL0_CPLT_RCTRL , 19 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_CPLT_RCTRL ); +REG64_FLD( PEC_STACK0_NET_CTRL0_CPLT_DCTRL , 20 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_CPLT_DCTRL ); +REG64_FLD( PEC_STACK0_NET_CTRL0_L3_EDRAM_ENABLE0 , 23 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_L3_EDRAM_ENABLE0 ); +REG64_FLD( PEC_STACK0_NET_CTRL0_L3_EDRAM_ENABLE1 , 24 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_L3_EDRAM_ENABLE1 ); +REG64_FLD( PEC_STACK0_NET_CTRL0_TP_FENCE_PCB , 25 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_TP_FENCE_PCB ); +REG64_FLD( PEC_STACK0_NET_CTRL0_LVLTRANS_FENCE , 26 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_LVLTRANS_FENCE ); +REG64_FLD( PEC_STACK0_NET_CTRL0_ARRAY_WRITE_ASSIST_EN , 27 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_ARRAY_WRITE_ASSIST_EN ); +REG64_FLD( PEC_STACK0_NET_CTRL0_HTB_INTEST , 28 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_HTB_INTEST ); +REG64_FLD( PEC_STACK0_NET_CTRL0_HTB_EXTEST , 29 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_HTB_EXTEST ); + +REG64_FLD( PEC_STACK0_NET_CTRL1_PLL_CLKIN_SEL , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_PLL_CLKIN_SEL ); +REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_DCC_BYPASS_EN , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_CLK_DCC_BYPASS_EN ); +REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PDLY_BYPASS_EN , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_CLK_PDLY_BYPASS_EN ); +REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_DIV_BYPASS_EN , 3 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_CLK_DIV_BYPASS_EN ); +REG64_FLD( PEC_STACK0_NET_CTRL1_REFCLK_CLKMUX0_SEL , 4 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_REFCLK_CLKMUX0_SEL ); +REG64_FLD( PEC_STACK0_NET_CTRL1_REFCLK_CLKMUX1_SEL , 5 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_REFCLK_CLKMUX1_SEL ); +REG64_FLD( PEC_STACK0_NET_CTRL1_PLL_BNDY_BYPASS_EN , 6 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_PLL_BNDY_BYPASS_EN ); +REG64_FLD( PEC_STACK0_NET_CTRL1_DPLL_TEST_SEL , 8 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_DPLL_TEST_SEL ); +REG64_FLD( PEC_STACK0_NET_CTRL1_DPLL_TEST_SEL_LEN , 8 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_DPLL_TEST_SEL_LEN ); +REG64_FLD( PEC_STACK0_NET_CTRL1_SB_STRENGTH , 16 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_SB_STRENGTH ); +REG64_FLD( PEC_STACK0_NET_CTRL1_SB_STRENGTH_LEN , 4 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_SB_STRENGTH_LEN ); +REG64_FLD( PEC_STACK0_NET_CTRL1_ASYNC_TYPE , 20 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_ASYNC_TYPE ); +REG64_FLD( PEC_STACK0_NET_CTRL1_ASYNC_OBS , 21 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_ASYNC_OBS ); +REG64_FLD( PEC_STACK0_NET_CTRL1_CPM_CAL_SET , 22 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_CPM_CAL_SET ); +REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PULSE_EN , 25 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_CLK_PULSE_EN ); +REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PULSE_MODE , 26 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_CLK_PULSE_MODE ); +REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PULSE_MODE_LEN , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_CLK_PULSE_MODE_LEN ); + +REG64_FLD( PEC_STACK2_NFIRACTION0_REG_NFIRACTION0 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , + SH_FLD_NFIRACTION0 ); +REG64_FLD( PEC_STACK2_NFIRACTION0_REG_NFIRACTION0_LEN , 30 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , + SH_FLD_NFIRACTION0_LEN ); + +REG64_FLD( PEC_STACK1_NFIRACTION0_REG_NFIRACTION0 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , + SH_FLD_NFIRACTION0 ); +REG64_FLD( PEC_STACK1_NFIRACTION0_REG_NFIRACTION0_LEN , 30 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , + SH_FLD_NFIRACTION0_LEN ); + REG64_FLD( PHB_NFIRACTION0_REG_NFIRACTION0 , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_NFIRACTION0 ); REG64_FLD( PHB_NFIRACTION0_REG_NFIRACTION0_LEN , 30 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_NFIRACTION0_LEN ); +REG64_FLD( PEC_STACK0_NFIRACTION0_REG_NFIRACTION0 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , + SH_FLD_NFIRACTION0 ); +REG64_FLD( PEC_STACK0_NFIRACTION0_REG_NFIRACTION0_LEN , 30 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , + SH_FLD_NFIRACTION0_LEN ); + +REG64_FLD( PEC_STACK2_NFIRACTION1_REG_NFIRACTION1 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , + SH_FLD_NFIRACTION1 ); +REG64_FLD( PEC_STACK2_NFIRACTION1_REG_NFIRACTION1_LEN , 30 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , + SH_FLD_NFIRACTION1_LEN ); + +REG64_FLD( PEC_STACK1_NFIRACTION1_REG_NFIRACTION1 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , + SH_FLD_NFIRACTION1 ); +REG64_FLD( PEC_STACK1_NFIRACTION1_REG_NFIRACTION1_LEN , 30 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , + SH_FLD_NFIRACTION1_LEN ); + REG64_FLD( PHB_NFIRACTION1_REG_NFIRACTION1 , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_NFIRACTION1 ); REG64_FLD( PHB_NFIRACTION1_REG_NFIRACTION1_LEN , 30 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_NFIRACTION1_LEN ); +REG64_FLD( PEC_STACK0_NFIRACTION1_REG_NFIRACTION1 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , + SH_FLD_NFIRACTION1 ); +REG64_FLD( PEC_STACK0_NFIRACTION1_REG_NFIRACTION1_LEN , 30 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , + SH_FLD_NFIRACTION1_LEN ); + +REG64_FLD( PEC_STACK2_NFIRMASK_REG_BAR_PE_MASK , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_BAR_PE_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_NONBAR_PE_MASK , 1 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_NONBAR_PE_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_TO_PEC_CE_MASK , 2 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_CE_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_TO_PEC_UE_MASK , 3 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_UE_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_TO_PEC_SUE_MASK , 4 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_SUE_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_ARY_ECC_CE_MASK , 5 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_CE_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_ARY_ECC_UE_MASK , 6 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_UE_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_ARY_ECC_SUE_MASK , 7 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_SUE_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_REGISTER_ARRAY_PE_MASK , 8 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_REGISTER_ARRAY_PE_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_INTERFACE_PE_MASK , 9 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PB_INTERFACE_PE_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_DATA_HANG_ERRORS_MASK , 10 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PB_DATA_HANG_ERRORS_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_HANG_ERRORS_MASK , 11 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PB_HANG_ERRORS_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_RD_ARE_ERRORS_MASK , 12 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_RD_ARE_ERRORS_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_NONRD_ARE_ERRORS_MASK , 13 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_NONRD_ARE_ERRORS_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_PCI_HANG_ERROR_MASK , 14 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PCI_HANG_ERROR_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_PCI_CLOCK_ERROR_MASK , 15 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PCI_CLOCK_ERROR_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_AIB_FENCE_MASK , 16 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_AIB_FENCE_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_HW_ERRORS_MASK , 17 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_HW_ERRORS_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_UNSOLICITIEDPBDATA_MASK , 18 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_UNSOLICITIEDPBDATA_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_UNEXPECTEDCRESP_MASK , 19 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_UNEXPECTEDCRESP_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_INVALIDCRESP_MASK , 20 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_INVALIDCRESP_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_PBUNSUPPORTEDSIZE_MASK , 21 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PBUNSUPPORTEDSIZE_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_PBUNSUPPORTEDCMD_MASK , 22 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PBUNSUPPORTEDCMD_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_AIB_PE_MASK , 23 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_AIB_PE_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_CAPP_ERROR_MASK , 24 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_CAPP_ERROR_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_PEC_SCOM_ERR_MASK , 27 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PEC_SCOM_ERR_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_STACK_SCOM_ERR0_MASK , 28 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_STACK_SCOM_ERR0_MASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_STACK_SCOM_ERR1_MASK , 29 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_STACK_SCOM_ERR1_MASK ); + +REG64_FLD( PEC_STACK1_NFIRMASK_REG_BAR_PE_MASK , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_BAR_PE_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_NONBAR_PE_MASK , 1 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_NONBAR_PE_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_TO_PEC_CE_MASK , 2 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_CE_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_TO_PEC_UE_MASK , 3 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_UE_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_TO_PEC_SUE_MASK , 4 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_SUE_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_ARY_ECC_CE_MASK , 5 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_CE_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_ARY_ECC_UE_MASK , 6 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_UE_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_ARY_ECC_SUE_MASK , 7 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_SUE_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_REGISTER_ARRAY_PE_MASK , 8 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_REGISTER_ARRAY_PE_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_INTERFACE_PE_MASK , 9 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PB_INTERFACE_PE_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_DATA_HANG_ERRORS_MASK , 10 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PB_DATA_HANG_ERRORS_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_HANG_ERRORS_MASK , 11 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PB_HANG_ERRORS_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_RD_ARE_ERRORS_MASK , 12 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_RD_ARE_ERRORS_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_NONRD_ARE_ERRORS_MASK , 13 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_NONRD_ARE_ERRORS_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_PCI_HANG_ERROR_MASK , 14 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PCI_HANG_ERROR_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_PCI_CLOCK_ERROR_MASK , 15 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PCI_CLOCK_ERROR_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_AIB_FENCE_MASK , 16 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_AIB_FENCE_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_HW_ERRORS_MASK , 17 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_HW_ERRORS_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_UNSOLICITIEDPBDATA_MASK , 18 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_UNSOLICITIEDPBDATA_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_UNEXPECTEDCRESP_MASK , 19 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_UNEXPECTEDCRESP_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_INVALIDCRESP_MASK , 20 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_INVALIDCRESP_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_PBUNSUPPORTEDSIZE_MASK , 21 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PBUNSUPPORTEDSIZE_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_PBUNSUPPORTEDCMD_MASK , 22 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PBUNSUPPORTEDCMD_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_AIB_PE_MASK , 23 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_AIB_PE_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_CAPP_ERROR_MASK , 24 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_CAPP_ERROR_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_PEC_SCOM_ERR_MASK , 27 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PEC_SCOM_ERR_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_STACK_SCOM_ERR0_MASK , 28 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_STACK_SCOM_ERR0_MASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_STACK_SCOM_ERR1_MASK , 29 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_STACK_SCOM_ERR1_MASK ); + REG64_FLD( PHB_NFIRMASK_REG_BAR_PE_MASK , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_BAR_PE_MASK ); REG64_FLD( PHB_NFIRMASK_REG_NONBAR_PE_MASK , 1 , SH_UNT_PHB , SH_ACS_SCOM2_OR , @@ -51314,6 +51670,177 @@ REG64_FLD( PHB_NFIRMASK_REG_STACK_SCOM_ERR0_MASK , 28 , SH_UN REG64_FLD( PHB_NFIRMASK_REG_STACK_SCOM_ERR1_MASK , 29 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR1_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_BAR_PE_MASK , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_BAR_PE_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_NONBAR_PE_MASK , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_NONBAR_PE_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_TO_PEC_CE_MASK , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_CE_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_TO_PEC_UE_MASK , 3 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_UE_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_TO_PEC_SUE_MASK , 4 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_SUE_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_ARY_ECC_CE_MASK , 5 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_CE_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_ARY_ECC_UE_MASK , 6 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_UE_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_ARY_ECC_SUE_MASK , 7 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_SUE_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_REGISTER_ARRAY_PE_MASK , 8 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_REGISTER_ARRAY_PE_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_INTERFACE_PE_MASK , 9 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PB_INTERFACE_PE_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_DATA_HANG_ERRORS_MASK , 10 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PB_DATA_HANG_ERRORS_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_HANG_ERRORS_MASK , 11 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PB_HANG_ERRORS_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_RD_ARE_ERRORS_MASK , 12 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_RD_ARE_ERRORS_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_NONRD_ARE_ERRORS_MASK , 13 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_NONRD_ARE_ERRORS_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_PCI_HANG_ERROR_MASK , 14 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PCI_HANG_ERROR_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_PCI_CLOCK_ERROR_MASK , 15 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PCI_CLOCK_ERROR_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_AIB_FENCE_MASK , 16 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_AIB_FENCE_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_HW_ERRORS_MASK , 17 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_HW_ERRORS_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_UNSOLICITIEDPBDATA_MASK , 18 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_UNSOLICITIEDPBDATA_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_UNEXPECTEDCRESP_MASK , 19 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_UNEXPECTEDCRESP_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_INVALIDCRESP_MASK , 20 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_INVALIDCRESP_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_PBUNSUPPORTEDSIZE_MASK , 21 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PBUNSUPPORTEDSIZE_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_PBUNSUPPORTEDCMD_MASK , 22 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PBUNSUPPORTEDCMD_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_AIB_PE_MASK , 23 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_AIB_PE_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_CAPP_ERROR_MASK , 24 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_CAPP_ERROR_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_PEC_SCOM_ERR_MASK , 27 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PEC_SCOM_ERR_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_STACK_SCOM_ERR0_MASK , 28 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_STACK_SCOM_ERR0_MASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_STACK_SCOM_ERR1_MASK , 29 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_STACK_SCOM_ERR1_MASK ); + +REG64_FLD( PEC_STACK2_NFIR_REG_BAR_PE , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_BAR_PE ); +REG64_FLD( PEC_STACK2_NFIR_REG_NONBAR_PE , 1 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_NONBAR_PE ); +REG64_FLD( PEC_STACK2_NFIR_REG_PB_TO_PEC_CE , 2 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_CE ); +REG64_FLD( PEC_STACK2_NFIR_REG_PB_TO_PEC_UE , 3 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_UE ); +REG64_FLD( PEC_STACK2_NFIR_REG_PB_TO_PEC_SUE , 4 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_SUE ); +REG64_FLD( PEC_STACK2_NFIR_REG_ARY_ECC_CE , 5 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_CE ); +REG64_FLD( PEC_STACK2_NFIR_REG_ARY_ECC_UE , 6 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_UE ); +REG64_FLD( PEC_STACK2_NFIR_REG_ARY_ECC_SUE , 7 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_SUE ); +REG64_FLD( PEC_STACK2_NFIR_REG_REGISTER_ARRAY_PE , 8 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_REGISTER_ARRAY_PE ); +REG64_FLD( PEC_STACK2_NFIR_REG_PB_INTERFACE_PE , 9 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PB_INTERFACE_PE ); +REG64_FLD( PEC_STACK2_NFIR_REG_PB_DATA_HANG_ERRORS , 10 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PB_DATA_HANG_ERRORS ); +REG64_FLD( PEC_STACK2_NFIR_REG_PB_HANG_ERRORS , 11 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PB_HANG_ERRORS ); +REG64_FLD( PEC_STACK2_NFIR_REG_RD_ARE_ERRORS , 12 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_RD_ARE_ERRORS ); +REG64_FLD( PEC_STACK2_NFIR_REG_NONRD_ARE_ERRORS , 13 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_NONRD_ARE_ERRORS ); +REG64_FLD( PEC_STACK2_NFIR_REG_PCI_HANG_ERROR , 14 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PCI_HANG_ERROR ); +REG64_FLD( PEC_STACK2_NFIR_REG_PCI_CLOCK_ERROR , 15 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PCI_CLOCK_ERROR ); +REG64_FLD( PEC_STACK2_NFIR_REG_AIB_FENCE , 16 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_AIB_FENCE ); +REG64_FLD( PEC_STACK2_NFIR_REG_HW_ERRORS , 17 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_HW_ERRORS ); +REG64_FLD( PEC_STACK2_NFIR_REG_UNSOLICITIEDPBDATA , 18 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_UNSOLICITIEDPBDATA ); +REG64_FLD( PEC_STACK2_NFIR_REG_UNEXPECTEDCRESP , 19 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_UNEXPECTEDCRESP ); +REG64_FLD( PEC_STACK2_NFIR_REG_INVALIDCRESP , 20 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_INVALIDCRESP ); +REG64_FLD( PEC_STACK2_NFIR_REG_PBUNSUPPORTEDSIZE , 21 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PBUNSUPPORTEDSIZE ); +REG64_FLD( PEC_STACK2_NFIR_REG_PBUNSUPPORTEDCMD , 22 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PBUNSUPPORTEDCMD ); +REG64_FLD( PEC_STACK2_NFIR_REG_AIB_PE , 23 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_AIB_PE ); +REG64_FLD( PEC_STACK2_NFIR_REG_CAPP_ERROR , 24 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_CAPP_ERROR ); +REG64_FLD( PEC_STACK2_NFIR_REG_PEC_SCOM_ERR , 27 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PEC_SCOM_ERR ); +REG64_FLD( PEC_STACK2_NFIR_REG_STACK_SCOM_ERR0 , 28 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_STACK_SCOM_ERR0 ); +REG64_FLD( PEC_STACK2_NFIR_REG_STACK_SCOM_ERR1 , 29 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_STACK_SCOM_ERR1 ); + +REG64_FLD( PEC_STACK1_NFIR_REG_BAR_PE , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_BAR_PE ); +REG64_FLD( PEC_STACK1_NFIR_REG_NONBAR_PE , 1 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_NONBAR_PE ); +REG64_FLD( PEC_STACK1_NFIR_REG_PB_TO_PEC_CE , 2 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_CE ); +REG64_FLD( PEC_STACK1_NFIR_REG_PB_TO_PEC_UE , 3 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_UE ); +REG64_FLD( PEC_STACK1_NFIR_REG_PB_TO_PEC_SUE , 4 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_SUE ); +REG64_FLD( PEC_STACK1_NFIR_REG_ARY_ECC_CE , 5 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_CE ); +REG64_FLD( PEC_STACK1_NFIR_REG_ARY_ECC_UE , 6 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_UE ); +REG64_FLD( PEC_STACK1_NFIR_REG_ARY_ECC_SUE , 7 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_SUE ); +REG64_FLD( PEC_STACK1_NFIR_REG_REGISTER_ARRAY_PE , 8 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_REGISTER_ARRAY_PE ); +REG64_FLD( PEC_STACK1_NFIR_REG_PB_INTERFACE_PE , 9 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PB_INTERFACE_PE ); +REG64_FLD( PEC_STACK1_NFIR_REG_PB_DATA_HANG_ERRORS , 10 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PB_DATA_HANG_ERRORS ); +REG64_FLD( PEC_STACK1_NFIR_REG_PB_HANG_ERRORS , 11 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PB_HANG_ERRORS ); +REG64_FLD( PEC_STACK1_NFIR_REG_RD_ARE_ERRORS , 12 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_RD_ARE_ERRORS ); +REG64_FLD( PEC_STACK1_NFIR_REG_NONRD_ARE_ERRORS , 13 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_NONRD_ARE_ERRORS ); +REG64_FLD( PEC_STACK1_NFIR_REG_PCI_HANG_ERROR , 14 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PCI_HANG_ERROR ); +REG64_FLD( PEC_STACK1_NFIR_REG_PCI_CLOCK_ERROR , 15 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PCI_CLOCK_ERROR ); +REG64_FLD( PEC_STACK1_NFIR_REG_AIB_FENCE , 16 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_AIB_FENCE ); +REG64_FLD( PEC_STACK1_NFIR_REG_HW_ERRORS , 17 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_HW_ERRORS ); +REG64_FLD( PEC_STACK1_NFIR_REG_UNSOLICITIEDPBDATA , 18 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_UNSOLICITIEDPBDATA ); +REG64_FLD( PEC_STACK1_NFIR_REG_UNEXPECTEDCRESP , 19 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_UNEXPECTEDCRESP ); +REG64_FLD( PEC_STACK1_NFIR_REG_INVALIDCRESP , 20 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_INVALIDCRESP ); +REG64_FLD( PEC_STACK1_NFIR_REG_PBUNSUPPORTEDSIZE , 21 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PBUNSUPPORTEDSIZE ); +REG64_FLD( PEC_STACK1_NFIR_REG_PBUNSUPPORTEDCMD , 22 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PBUNSUPPORTEDCMD ); +REG64_FLD( PEC_STACK1_NFIR_REG_AIB_PE , 23 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_AIB_PE ); +REG64_FLD( PEC_STACK1_NFIR_REG_CAPP_ERROR , 24 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_CAPP_ERROR ); +REG64_FLD( PEC_STACK1_NFIR_REG_PEC_SCOM_ERR , 27 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PEC_SCOM_ERR ); +REG64_FLD( PEC_STACK1_NFIR_REG_STACK_SCOM_ERR0 , 28 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_STACK_SCOM_ERR0 ); +REG64_FLD( PEC_STACK1_NFIR_REG_STACK_SCOM_ERR1 , 29 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_STACK_SCOM_ERR1 ); + REG64_FLD( PHB_NFIR_REG_BAR_PE , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_BAR_PE ); REG64_FLD( PHB_NFIR_REG_NONBAR_PE , 1 , SH_UNT_PHB , SH_ACS_SCOM2_OR , @@ -51371,6 +51898,63 @@ REG64_FLD( PHB_NFIR_REG_STACK_SCOM_ERR0 , 28 , SH_UN REG64_FLD( PHB_NFIR_REG_STACK_SCOM_ERR1 , 29 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR1 ); +REG64_FLD( PEC_STACK0_NFIR_REG_BAR_PE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_BAR_PE ); +REG64_FLD( PEC_STACK0_NFIR_REG_NONBAR_PE , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_NONBAR_PE ); +REG64_FLD( PEC_STACK0_NFIR_REG_PB_TO_PEC_CE , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_CE ); +REG64_FLD( PEC_STACK0_NFIR_REG_PB_TO_PEC_UE , 3 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_UE ); +REG64_FLD( PEC_STACK0_NFIR_REG_PB_TO_PEC_SUE , 4 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PB_TO_PEC_SUE ); +REG64_FLD( PEC_STACK0_NFIR_REG_ARY_ECC_CE , 5 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_CE ); +REG64_FLD( PEC_STACK0_NFIR_REG_ARY_ECC_UE , 6 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_UE ); +REG64_FLD( PEC_STACK0_NFIR_REG_ARY_ECC_SUE , 7 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_ARY_ECC_SUE ); +REG64_FLD( PEC_STACK0_NFIR_REG_REGISTER_ARRAY_PE , 8 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_REGISTER_ARRAY_PE ); +REG64_FLD( PEC_STACK0_NFIR_REG_PB_INTERFACE_PE , 9 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PB_INTERFACE_PE ); +REG64_FLD( PEC_STACK0_NFIR_REG_PB_DATA_HANG_ERRORS , 10 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PB_DATA_HANG_ERRORS ); +REG64_FLD( PEC_STACK0_NFIR_REG_PB_HANG_ERRORS , 11 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PB_HANG_ERRORS ); +REG64_FLD( PEC_STACK0_NFIR_REG_RD_ARE_ERRORS , 12 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_RD_ARE_ERRORS ); +REG64_FLD( PEC_STACK0_NFIR_REG_NONRD_ARE_ERRORS , 13 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_NONRD_ARE_ERRORS ); +REG64_FLD( PEC_STACK0_NFIR_REG_PCI_HANG_ERROR , 14 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PCI_HANG_ERROR ); +REG64_FLD( PEC_STACK0_NFIR_REG_PCI_CLOCK_ERROR , 15 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PCI_CLOCK_ERROR ); +REG64_FLD( PEC_STACK0_NFIR_REG_AIB_FENCE , 16 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_AIB_FENCE ); +REG64_FLD( PEC_STACK0_NFIR_REG_HW_ERRORS , 17 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_HW_ERRORS ); +REG64_FLD( PEC_STACK0_NFIR_REG_UNSOLICITIEDPBDATA , 18 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_UNSOLICITIEDPBDATA ); +REG64_FLD( PEC_STACK0_NFIR_REG_UNEXPECTEDCRESP , 19 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_UNEXPECTEDCRESP ); +REG64_FLD( PEC_STACK0_NFIR_REG_INVALIDCRESP , 20 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_INVALIDCRESP ); +REG64_FLD( PEC_STACK0_NFIR_REG_PBUNSUPPORTEDSIZE , 21 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PBUNSUPPORTEDSIZE ); +REG64_FLD( PEC_STACK0_NFIR_REG_PBUNSUPPORTEDCMD , 22 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PBUNSUPPORTEDCMD ); +REG64_FLD( PEC_STACK0_NFIR_REG_AIB_PE , 23 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_AIB_PE ); +REG64_FLD( PEC_STACK0_NFIR_REG_CAPP_ERROR , 24 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_CAPP_ERROR ); +REG64_FLD( PEC_STACK0_NFIR_REG_PEC_SCOM_ERR , 27 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_PEC_SCOM_ERR ); +REG64_FLD( PEC_STACK0_NFIR_REG_STACK_SCOM_ERR0 , 28 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_STACK_SCOM_ERR0 ); +REG64_FLD( PEC_STACK0_NFIR_REG_STACK_SCOM_ERR1 , 29 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_STACK_SCOM_ERR1 ); + REG64_FLD( PU_NOTRUST_BAR0_UNTRUSTED , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNTRUSTED ); REG64_FLD( PU_NOTRUST_BAR0_UNTRUSTED_LEN , 30 , SH_UNT , SH_ACS_SCOM , @@ -56815,11 +57399,26 @@ REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_MC_PREFETCH , 62 , SH_UN REG64_FLD( PEC_PBCQHWCFG_REG_PE_IGNORE_SFSTAT , 63 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_IGNORE_SFSTAT ); +REG64_FLD( PEC_STACK2_PBCQMODE_REG_PE_PEER2PEER_MODDE , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , + SH_FLD_PE_PEER2PEER_MODDE ); +REG64_FLD( PEC_STACK2_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE , 1 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , + SH_FLD_PE_ENHANCED_PEER2PEER_MODDE ); + +REG64_FLD( PEC_STACK1_PBCQMODE_REG_PE_PEER2PEER_MODDE , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , + SH_FLD_PE_PEER2PEER_MODDE ); +REG64_FLD( PEC_STACK1_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE , 1 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , + SH_FLD_PE_ENHANCED_PEER2PEER_MODDE ); + REG64_FLD( PHB_PBCQMODE_REG_PE_PEER2PEER_MODDE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_PEER2PEER_MODDE ); REG64_FLD( PHB_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE , 1 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_ENHANCED_PEER2PEER_MODDE ); +REG64_FLD( PEC_STACK0_PBCQMODE_REG_PE_PEER2PEER_MODDE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , + SH_FLD_PE_PEER2PEER_MODDE ); +REG64_FLD( PEC_STACK0_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , + SH_FLD_PE_ENHANCED_PEER2PEER_MODDE ); + REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_VALID , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MB_VALID ); REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_WR_NOT_RD , 1 , SH_UNT , SH_ACS_SCOM , @@ -56874,88 +57473,88 @@ REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_SPARE , 12 , SH_UN REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_SPARE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_MB_SPARE_LEN ); -REG64_FLD( _SM0_PB_CENT_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT__SM0 , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); -REG64_FLD( _SM0_PB_CENT_FIR_ACTION0_REG_ACTION0_LEN , 18 , SH_UNT__SM0 , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0_LEN , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); -REG64_FLD( _SM0_PB_CENT_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT__SM0 , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); -REG64_FLD( _SM0_PB_CENT_FIR_ACTION1_REG_ACTION1_LEN , 18 , SH_UNT__SM0 , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG_ACTION1_LEN , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_PROTOCOL_ERROR , 0 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_PROTOCOL_ERROR , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_PROTOCOL_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_OVERFLOW_ERROR , 1 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_OVERFLOW_ERROR , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_OVERFLOW_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_HW_PARITY_ERROR , 2 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_HW_PARITY_ERROR , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_HW_PARITY_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SPARE_3 , 3 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_3 , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_3 ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_COHERENCY_ERROR , 4 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_COHERENCY_ERROR , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_COHERENCY_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_CRESP_ADDR_ERROR , 5 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_CRESP_ADDR_ERROR , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_CRESP_ADDR_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_CRESP_ERROR , 6 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_CRESP_ERROR , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_CRESP_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_HANG_RECOVERY_LIMIT_ERROR , 7 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_HANG_RECOVERY_LIMIT_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_DATA_ROUTE_ERROR , 8 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_HANG_RECOVERY_LIMIT_ERROR , 7 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM2_OR , SH_FLD_HANG_RECOVERY_LIMIT_ERROR ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_DATA_ROUTE_ERROR , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_DATA_ROUTE_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_HANG_RECOVERY_GTE_LEVEL1 , 9 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_HANG_RECOVERY_GTE_LEVEL1 , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_HANG_RECOVERY_GTE_LEVEL1 ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_FORCE_MP_IPL , 10 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_FORCE_MP_IPL , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_FORCE_MP_IPL ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SPARE_11 , 11 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_11 , 11 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_11 ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SPARE_12 , 12 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_12 , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_12 ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SPARE_13 , 13 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_13 , 13 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_13 ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SPARE_14 , 14 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_14 , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_14 ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SPARE_15 , 15 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_15 , 15 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_15 ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SCOM_ERR , 16 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SCOM_ERR , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); -REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SCOM_ERR_DUP , 17 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SCOM_ERR_DUP , 17 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_PROTOCOL_ERROR , 0 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_PROTOCOL_ERROR , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_PROTOCOL_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_OVERFLOW_ERROR , 1 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_OVERFLOW_ERROR , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_OVERFLOW_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_HW_PARITY_ERROR , 2 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_HW_PARITY_ERROR , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_HW_PARITY_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_SPARE_3 , 3 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_3 , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_3 ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_COHERENCY_ERROR , 4 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_COHERENCY_ERROR , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_COHERENCY_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_CRESP_ADDR_ERROR , 5 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_CRESP_ADDR_ERROR , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_CRESP_ADDR_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_CRESP_ERROR , 6 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_CRESP_ERROR , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_CRESP_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_HANG_RECOVERY_LIMIT_ERROR , 7 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_HANG_RECOVERY_LIMIT_ERROR , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_HANG_RECOVERY_LIMIT_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_DATA_ROUTE_ERROR , 8 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_DATA_ROUTE_ERROR , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_DATA_ROUTE_ERROR ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_HANG_RECOVERY_GTE_LEVEL1 , 9 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_HANG_RECOVERY_GTE_LEVEL1 , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_HANG_RECOVERY_GTE_LEVEL1 ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_FORCE_MP_IPL , 10 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_FORCE_MP_IPL , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_FORCE_MP_IPL ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_SPARE_11 , 11 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_11 , 11 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_11 ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_SPARE_12 , 12 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_12 , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_12 ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_SPARE_13 , 13 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_13 , 13 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_13 ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_SPARE_14 , 14 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_14 , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_14 ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_SPARE_15 , 15 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_15 , 15 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_15 ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_SCOM_ERR , 16 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SCOM_ERR , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); -REG64_FLD( _SM0_PB_CENT_FIR_REG_SCOM_ERR_DUP , 17 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SCOM_ERR_DUP , 17 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PU_PB_EAST_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , @@ -58952,152 +59551,152 @@ REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK07_LO , 60 , SH_UN REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK07_LO_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK07_LO_LEN ); -REG64_FLD( _SM0_PB_WEST_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT__SM0 , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); -REG64_FLD( _SM0_PB_WEST_FIR_ACTION0_REG_ACTION0_LEN , 34 , SH_UNT__SM0 , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG_ACTION0_LEN , 34 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); -REG64_FLD( _SM0_PB_WEST_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT__SM0 , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); -REG64_FLD( _SM0_PB_WEST_FIR_ACTION1_REG_ACTION1_LEN , 34 , SH_UNT__SM0 , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG_ACTION1_LEN , 34 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_HW1_ERROR , 0 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_HW1_ERROR , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_HW1_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_HW2_ERROR , 1 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_HW2_ERROR , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_HW2_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_PROTOCOL_ERROR , 2 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_PBIEQ00_PBH_PROTOCOL_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_OVERFLOW_ERROR , 3 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_PBIEQ00_PBH_OVERFLOW_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_HW1_ERROR , 4 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_PROTOCOL_ERROR , 2 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_PROTOCOL_ERROR ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_OVERFLOW_ERROR , 3 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_OVERFLOW_ERROR ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_HW1_ERROR , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_HW1_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_HW2_ERROR , 5 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_HW2_ERROR , 5 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_HW2_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_PROTOCOL_ERROR , 6 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_PBIEQ01_PBH_PROTOCOL_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_OVERFLOW_ERROR , 7 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_PBIEQ01_PBH_OVERFLOW_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_HW1_ERROR , 8 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_PROTOCOL_ERROR , 6 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_PROTOCOL_ERROR ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_OVERFLOW_ERROR , 7 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_OVERFLOW_ERROR ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_HW1_ERROR , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_HW1_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_HW2_ERROR , 9 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_HW2_ERROR , 9 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_HW2_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_PROTOCOL_ERROR , 10 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_PBIEQ02_PBH_PROTOCOL_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_OVERFLOW_ERROR , 11 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_PBIEQ02_PBH_OVERFLOW_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_HW1_ERROR , 12 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_PROTOCOL_ERROR , 10 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_PROTOCOL_ERROR ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_OVERFLOW_ERROR , 11 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_OVERFLOW_ERROR ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_HW1_ERROR , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_HW1_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_HW2_ERROR , 13 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_HW2_ERROR , 13 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_HW2_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_PROTOCOL_ERROR , 14 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_PBIEQ03_PBH_PROTOCOL_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_OVERFLOW_ERROR , 15 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_PBIEQ03_PBH_OVERFLOW_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_16 , 16 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_PROTOCOL_ERROR , 14 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_PROTOCOL_ERROR ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_OVERFLOW_ERROR , 15 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_OVERFLOW_ERROR ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_16 , 16 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_16 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_17 , 17 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_17 , 17 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_17 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_18 , 18 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_18 , 18 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_18 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_19 , 19 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_19 , 19 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_19 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_20 , 20 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_20 , 20 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_20 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_21 , 21 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_21 , 21 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_21 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_22 , 22 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_22 , 22 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_22 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_23 , 23 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_23 , 23 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_23 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_24 , 24 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_24 , 24 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_24 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_25 , 25 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_25 , 25 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_25 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_26 , 26 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_26 , 26 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_26 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_27 , 27 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_27 , 27 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_27 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_28 , 28 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_28 , 28 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_28 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_29 , 29 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_29 , 29 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_29 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_30 , 30 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_30 , 30 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_30 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_31 , 31 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_31 , 31 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_31 ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SCOM_ERR , 32 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SCOM_ERR , 32 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); -REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SCOM_ERR_DUP , 33 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SCOM_ERR_DUP , 33 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_HW1_ERROR , 0 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_HW1_ERROR , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_HW1_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_HW2_ERROR , 1 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_HW2_ERROR , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_HW2_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_PROTOCOL_ERROR , 2 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_PROTOCOL_ERROR , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_PROTOCOL_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_OVERFLOW_ERROR , 3 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_OVERFLOW_ERROR , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_OVERFLOW_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_HW1_ERROR , 4 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_HW1_ERROR , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_HW1_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_HW2_ERROR , 5 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_HW2_ERROR , 5 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_HW2_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_PROTOCOL_ERROR , 6 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_PROTOCOL_ERROR , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_PROTOCOL_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_OVERFLOW_ERROR , 7 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_OVERFLOW_ERROR , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_OVERFLOW_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_HW1_ERROR , 8 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_HW1_ERROR , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_HW1_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_HW2_ERROR , 9 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_HW2_ERROR , 9 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_HW2_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_PROTOCOL_ERROR , 10 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_PROTOCOL_ERROR , 10 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_PROTOCOL_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_OVERFLOW_ERROR , 11 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_OVERFLOW_ERROR , 11 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_OVERFLOW_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_HW1_ERROR , 12 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_HW1_ERROR , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_HW1_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_HW2_ERROR , 13 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_HW2_ERROR , 13 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_HW2_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_PROTOCOL_ERROR , 14 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_PROTOCOL_ERROR , 14 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_PROTOCOL_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_OVERFLOW_ERROR , 15 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_OVERFLOW_ERROR , 15 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_OVERFLOW_ERROR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_16 , 16 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_16 , 16 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_16 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_17 , 17 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_17 , 17 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_17 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_18 , 18 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_18 , 18 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_18 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_19 , 19 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_19 , 19 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_19 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_20 , 20 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_20 , 20 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_20 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_21 , 21 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_21 , 21 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_21 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_22 , 22 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_22 , 22 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_22 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_23 , 23 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_23 , 23 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_23 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_24 , 24 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_24 , 24 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_24 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_25 , 25 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_25 , 25 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_25 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_26 , 26 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_26 , 26 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_26 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_27 , 27 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_27 , 27 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_27 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_28 , 28 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_28 , 28 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_28 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_29 , 29 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_29 , 29 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_29 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_30 , 30 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_30 , 30 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_30 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_31 , 31 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_31 , 31 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_31 ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SCOM_ERR , 32 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR , 32 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); -REG64_FLD( _SM0_PB_WEST_FIR_REG_SCOM_ERR_DUP , 33 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR_DUP , 33 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PEC_PCS_M1_CONTROL_REG_CONTROL , 48 , SH_UNT_PEC , SH_ACS_SCOM , @@ -60087,16 +60686,46 @@ REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE8_DMA_STOPPED_STATE , 0 , SH_UN REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE9_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); +REG64_FLD( PEC_STACK2_PE_DFREEZE_REG_DFREEZE , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , + SH_FLD_DFREEZE ); +REG64_FLD( PEC_STACK2_PE_DFREEZE_REG_DFREEZE_LEN , 28 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , + SH_FLD_DFREEZE_LEN ); + +REG64_FLD( PEC_STACK1_PE_DFREEZE_REG_DFREEZE , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , + SH_FLD_DFREEZE ); +REG64_FLD( PEC_STACK1_PE_DFREEZE_REG_DFREEZE_LEN , 28 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , + SH_FLD_DFREEZE_LEN ); + REG64_FLD( PHB_PE_DFREEZE_REG_DFREEZE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_DFREEZE ); REG64_FLD( PHB_PE_DFREEZE_REG_DFREEZE_LEN , 28 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_DFREEZE_LEN ); +REG64_FLD( PEC_STACK0_PE_DFREEZE_REG_DFREEZE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , + SH_FLD_DFREEZE ); +REG64_FLD( PEC_STACK0_PE_DFREEZE_REG_DFREEZE_LEN , 28 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , + SH_FLD_DFREEZE_LEN ); + +REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , + SH_FLD_PE_PHB_BAR ); +REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR_LEN , 42 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , + SH_FLD_PE_PHB_BAR_LEN ); + +REG64_FLD( PEC_STACK1_PHBBAR_REG_PE_PHB_BAR , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , + SH_FLD_PE_PHB_BAR ); +REG64_FLD( PEC_STACK1_PHBBAR_REG_PE_PHB_BAR_LEN , 42 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , + SH_FLD_PE_PHB_BAR_LEN ); + REG64_FLD( PHB_PHBBAR_REG_PE_PHB_BAR , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_PHB_BAR ); REG64_FLD( PHB_PHBBAR_REG_PE_PHB_BAR_LEN , 42 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_PHB_BAR_LEN ); +REG64_FLD( PEC_STACK0_PHBBAR_REG_PE_PHB_BAR , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , + SH_FLD_PE_PHB_BAR ); +REG64_FLD( PEC_STACK0_PHBBAR_REG_PE_PHB_BAR_LEN , 42 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , + SH_FLD_PE_PHB_BAR_LEN ); + REG64_FLD( PU_PBAIB_STACK5_PHBRESET_REG_PE_ETU_RESET , 0 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW , SH_FLD_PE_ETU_RESET ); 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