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| author | Greg Still <stillgs@us.ibm.com> | 2015-11-16 07:35:01 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-03-02 16:05:49 -0500 |
| commit | 9fee5c25606e5cebfa6f305d3acdf194601ce957 (patch) | |
| tree | 1e779a351033ca282f5247e6faaf9e58dd36baa3 /src | |
| parent | 7f0cc3f76d36e95aced0aa5bd58af0539641609c (diff) | |
| download | talos-hostboot-9fee5c25606e5cebfa6f305d3acdf194601ce957.tar.gz talos-hostboot-9fee5c25606e5cebfa6f305d3acdf194601ce957.zip | |
p9_sbe_select_ex Level 2
- SUET tested (this included updates to suet.scomdef)
- Awan unit (re)test (note yet through IPL script inclusion)
- Update Multicast Group assignment per HW/FW interlock
- Addressed review comments, including Round 2
- Changed to use of PERV targets only as ATTR_CHIP_UNIT_POS
of these are supported on the SBE
- Added support for ATTR_MASTER_CORE and ATTR_MASTER_EX where
core/EX numbers (not Pervasive chiplet numbers) of the boot
core and EX are stored
- Fix attribute conflict
Change-Id: I5c52c4c378f40361bca84a5dbba5b28dd286380d
RTC: 141486
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22508
Tested-by: Jenkins Server
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21549
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index ea7b17f12..588b59cb4 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -181,7 +181,9 @@ <attribute> <id>ATTR_SYS_FORCE_ALL_CORES</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Indicates that SBE should init all cores</description> + <description>Indicate that p9_sbe_select_ex should force selection to ALL good + EX chiplets having good cores even if only a single EX chiplet mode is executed. + </description> <valueType>uint8</valueType> <enum>FALSE = 0x0,TRUE = 0x1</enum> <persistRuntime/> @@ -501,4 +503,27 @@ <platInit/> </attribute> +<attribute> + <id>ATTR_MASTER_CORE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates the master boot core chiplet selected by p9_sbe_select_ex. + </description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_MASTER_EX</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates the EX targert associated with the master boot core selected + by p9_sbe_select_ex. + </description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + </attributes> |
