Support P8 memory map from PHYP

Change-Id: I19e5c373713b6e8b12386266c5c2c3a015068d5a
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1132
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

11 files changed, 34 insertions, 23 deletions

diff --git a/src/build/citest/autocitest b/src/build/citest/autocitest
index cc49290ea..5b755e0b8 100755
--- a/src/build/citest/autocitest
+++ b/src/build/citest/autocitest
@@ -6,7 +6,7 @@
 #
 #  IBM CONFIDENTIAL
 #
-#  COPYRIGHT International Business Machines Corp. 2011
+#  COPYRIGHT International Business Machines Corp. 2011-2012
 #
 #  p1
 #
@@ -20,8 +20,7 @@
 #
 #  Origin: 30
 #
-#  IBM_PROLOG_END
-
+#  IBM_PROLOG_END_TAG
 ################################################################################
 ##  Simics automation using autosim
 ##  2011-05-23  mww modified to run hostboot in simics
@@ -388,7 +387,7 @@ tracecalls=`cat $SBXHOME/tracecalls.log | xargs echo -n`
 
 
 echo "====> dump printk buffer..."
-autosim $NOWIN --simcmd "p8Proc0.l3_cache_image.save ${SBXHOME}/testprintk.log 0x$printk_buffer_addr 0x$printk_buffer_size"  1> /dev/null 2> /dev/null
+autosim $NOWIN --simcmd "(system_cmp0.phys_mem)->map[0][1]->image.save ${SBXHOME}/testprintk.log 0x$printk_buffer_addr 0x$printk_buffer_size"  1> /dev/null 2> /dev/null
 if [ $? -ne 0 ] ; then
 echo "ERROR: Unable to run $?"
        stopsim
diff --git a/src/build/citest/etc/bbuild b/src/build/citest/etc/bbuild
index 588c3b8b7..99efbed04 100644
--- a/src/build/citest/etc/bbuild
+++ b/src/build/citest/etc/bbuild
@@ -1 +1 @@
-/esw/fips810/Builds/b0510a_1219.810
+/esw/fips810/Builds/b0530b_1221.810
diff --git a/src/build/citest/etc/workarounds.presimsetup b/src/build/citest/etc/workarounds.presimsetup
index d8616729f..049996a1e 100755
--- a/src/build/citest/etc/workarounds.presimsetup
+++ b/src/build/citest/etc/workarounds.presimsetup
@@ -28,6 +28,12 @@
 ##
 
 
+echo "+++ Updates for memory map."
+mkdir -p $sb/simu/data
+egrep -v "WSALIAS DEFAULT FIPSLEVEL|WSALIAS DEFAULT PHYPLEVEL" $BACKING_BUILD/src/simu/data/simicsInfo > $sb/simu/data/simicsInfo
+echo "WSALIAS DEFAULT FIPSLEVEL env/gfwd/simics-4.2.0/simics-4.2.85/fips/fld36/fi120530c700.42" >> $sb/simu/data/simicsInfo
+echo "WSALIAS DEFAULT PHYPLEVEL env/phypb/simics-4.2.0/simics-4.2.85/ph120531a700.42" >> $sb/simu/data/simicsInfo
+
 #### Examples ####
 #echo "+++ Some message about why you need to do this."
 #mkdir -p $sb/simu/data
diff --git a/src/build/debug/simics-debug-framework.py b/src/build/debug/simics-debug-framework.py
index 682c8aa56..33fcee913 100755
--- a/src/build/debug/simics-debug-framework.py
+++ b/src/build/debug/simics-debug-framework.py
@@ -6,7 +6,7 @@
 #
 #  IBM CONFIDENTIAL
 #
-#  COPYRIGHT International Business Machines Corp. 2011 - 2012
+#  COPYRIGHT International Business Machines Corp. 2011-2012
 #
 #  p1
 #
@@ -399,7 +399,7 @@ def magic_instruction_callback(user_arg, cpu, arg):
             # fsp-trace style.
             writeLongLong(tracBinaryInfoAddr+8,1)
         # Save the tracBinary buffer to a file named tracBINARY in current dir
-        saveCommand = "p8Proc0.l3_cache_image.save tracBINARY 0x%x %d"%(pTracBinaryBuffer,cbUsed)
+        saveCommand = "(system_cmp0.phys_mem)->map[0][1]->image.save tracBINARY 0x%x %d"%(pTracBinaryBuffer,cbUsed)
         SIM_run_alone(run_command, saveCommand )
         # Run fsp-trace on tracBINARY file (implied), append output to tracMERG
         os.system( "fsp-trace ./ -s hbotStringFile >>tracMERG  2>/dev/null" )
diff --git a/src/build/simics/hb-simdebug.py b/src/build/simics/hb-simdebug.py
index 7041bd2e5..c8aba37e1 100755
--- a/src/build/simics/hb-simdebug.py
+++ b/src/build/simics/hb-simdebug.py
@@ -5,7 +5,7 @@
 #
 #  IBM CONFIDENTIAL
 #
-#  COPYRIGHT International Business Machines Corp. 2011 - 2012
+#  COPYRIGHT International Business Machines Corp. 2011-2012
 #
 #  p1
 #
@@ -44,7 +44,7 @@ def dumpL3():
     #print t
 
     #dump L3 to hbdump.<timestamp>
-    string = "p8Proc0.l3_cache_image.save hbdump.%s 0 0x%x"%(t, L3_SIZE)
+    string = "(system_cmp0.phys_mem)->map[0][1]->image.save hbdump.%s 0 0x%x"%(t, L3_SIZE)
     #print string
     result = run_command(string)
     #print result
diff --git a/src/build/simics/post_model_hook.simics b/src/build/simics/post_model_hook.simics
index 3a8e54be1..fb5480c26 100755
--- a/src/build/simics/post_model_hook.simics
+++ b/src/build/simics/post_model_hook.simics
@@ -43,9 +43,10 @@ phys-mem.load-file ./sysspd.dat 0x701000
 #Setup the mailbox 
 venice_cec_chip_cmp0.psi_hb->psihb_psihbcr=0x5f00000000000000
 # for mbox on core 0 use:
-venice_cec_chip_cmp0.psi_hb->psihb_xivr_fsi=0x0140000000     #02010917
-# for mbox on core 1 use:
-#venice_cec_chip_cmp0.psi_hb->psihb_xivr_fsi=0x0000200140000000
+# venice_cec_chip_cmp0.psi_hb->psihb_xivr_fsi=0x0140000000     #02010917
+# for mbox on core 5 use:
+venice_cec_chip_cmp0.psi_hb->psihb_xivr_fsi=0x0000A00140000000   #02010917
+
 venice_cec_chip_cmp0.psi_hb->psihb_irsn=0x00030000FFFF0000   #0201091b
 p8Proc0.proc_fsi2host_mbox->responder_enable=1
 
diff --git a/src/include/sys/interrupt.h b/src/include/sys/interrupt.h
index 1b44c5260..8031f817e 100644
--- a/src/include/sys/interrupt.h
+++ b/src/include/sys/interrupt.h
@@ -33,7 +33,7 @@ enum
 {
     ICPBAR_SCOM_ADDR = 0x020109ca,      //!< for P8, P7 = 0x02011C09
     // This BAR value agrees with simics (for now)
-    ICPBAR_VAL = 0x03FBFF90,            //!< ICPBAR value bits[0:29]>>34
+    ICPBAR_VAL = 0x3FFFF800,            //!< ICPBAR value bits[0:29]>>34
 };
 
 #endif
diff --git a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C
index f8a21d621..09404b559 100644
--- a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C
+++ b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C
@@ -66,6 +66,7 @@
 //remove these once memory setup workaround is removed
 #include <devicefw/driverif.H>
 #include <spd/spdenums.H>
+#include <sys/time.h>
 
 namespace   DRAM_INITIALIZATION
 {
@@ -352,7 +353,7 @@ void    call_proc_setup_bars( void    *io_pArgs )
     //  loop through all processor targets
     //     1) loop on associated MCSs
     //          a) Get associated logical dimms, sum total size of memory
-    //          b) Write memory base addr/size out to MCFGP 0x02011800 
+    //          b) Write memory base addr/size out to MCFGP 0x02011800
 
     //Don't do this in VPO -- shouldn't be run anyway, but return as a precaution
     if( TARGETING::is_vpo() )
@@ -510,6 +511,9 @@ void    call_proc_setup_bars( void    *io_pArgs )
     //Now need to scom the L3 bar on my EX to trigger Simics cache contained exit
     if(!l_errl)
     {
+        // TODO: Remove workaround with RTC: 42922.
+        nanosleep(1,0); // workaround Simics race condition.
+
         TARGETING::Target* procTarget = NULL;
         TARGETING::targetService().masterProcChipTargetHandle( procTarget );
 
@@ -521,6 +525,7 @@ void    call_proc_setup_bars( void    *io_pArgs )
 
         uint64_t scom_data = 0x0; //data doesn't matter, just the write
         size_t size = sizeof(scom_data);
+
         l_errl = deviceWrite( procTarget,
                               &scom_data,
                               size,
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C
index 61f537932..ce2e1a26f 100644
--- a/src/usr/intr/intrrp.C
+++ b/src/usr/intr/intrrp.C
@@ -66,11 +66,11 @@ void IntrRp::init( errlHndl_t   &io_errlHndl_t )
 }
 
 
-//  ICPBAR = INTP.ICP_BAR[0:25] in P7 = 0x3FBFF90 + (8*node) + procPos
+//  ICPBAR = INTP.ICP_BAR[0:25] in P8 = 0x3FFFF800 + (8*node) + procPos
 //  P7 Scom address 0x02011C09 P8 = 0x020109c9
 //  BaseAddress P7:
 //  BA[18:43] = ICPBAR  (P8 says [14:43] (30 bits))
-//  BA[47:49] = COREid (0-7) 
+//  BA[47:49] = COREid (0-7)
 //  BA[50:51] = cpu thread (0-3)
 //
 //  BaseAddress P8:
@@ -408,7 +408,7 @@ errlHndl_t IntrRp::setBAR(TARGETING::Target * i_target,
 {
     errlHndl_t err = NULL;
 
-    uint64_t barValue = static_cast<uint64_t>(ICPBAR_VAL) + 
+    uint64_t barValue = static_cast<uint64_t>(ICPBAR_VAL) +
             (8 * i_pir.nodeId) + i_pir.chipId;
     barValue <<= 34;
 
@@ -523,7 +523,7 @@ void IntrRp::deconfigureInterruptPresenter(const PIR_t i_pir) const
         reinterpret_cast<uint32_t *>(baseAddr + LINKA_OFFSET);
 
     // non- side effect xirr register
-    uint32_t * xirrAddr = 
+    uint32_t * xirrAddr =
         reinterpret_cast<uint32_t *>(baseAddr) + XIRR_RO_OFFSET;
 
     uint32_t xirr = *xirrAddr & 0x00FFFFFF;
diff --git a/src/usr/intr/test/intrtest.H b/src/usr/intr/test/intrtest.H
index f7c6b37f4..d395ab9ac 100644
--- a/src/usr/intr/test/intrtest.H
+++ b/src/usr/intr/test/intrtest.H
@@ -78,7 +78,7 @@ class IntrTest: public CxxTest::TestSuite
                             *(addr + 2)
                             );
                 }
-                
+
             }
 
             // Potentially could check all link registers on other chips
@@ -129,7 +129,7 @@ class IntrTest: public CxxTest::TestSuite
         void test_intr( void )
         {
 
-            // DISABLE in VBU 
+            // DISABLE in VBU
             if( TARGETING::is_vpo() )
             {
                 return;
@@ -148,7 +148,7 @@ class IntrTest: public CxxTest::TestSuite
             }
 
             // Force an interrupt by writing to the MFFR on master
-            volatile uint8_t * mfrr = 
+            volatile uint8_t * mfrr =
                 reinterpret_cast<uint8_t *>(iv_masterAddr+12);
             *(mfrr) = 0x55;
             *(mfrr) = 0xff;
@@ -211,7 +211,7 @@ class IntrTest: public CxxTest::TestSuite
 };
 
 //note: this must be changed if the BAR changes
-const uint64_t IntrTest::cv_realAddr = 0x3fbff9000000ul;
+const uint64_t IntrTest::cv_realAddr = 0x3ffff80000000ul;
 
 
 
diff --git a/src/usr/xscom/xscom.H b/src/usr/xscom/xscom.H
index 86773120a..88cb0aeaf 100644
--- a/src/usr/xscom/xscom.H
+++ b/src/usr/xscom/xscom.H
@@ -39,7 +39,7 @@
  *  @brief  The (fixed) base address value for master proc
  */
 //@todo - Verify this value for HW
-#define MASTER_PROC_XSCOM_BASE_ADDR     0x300000000000
+#define MASTER_PROC_XSCOM_BASE_ADDR     0x0003FC0000000000
 
 /**
  *  @brief  Type definition for XSCom address and Chip ID