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| author | Thi Tran <thi@us.ibm.com> | 2014-05-21 11:12:19 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-05-21 14:08:27 -0500 |
| commit | c40793af8423dbdaeb2119c4498b2e086943da53 (patch) | |
| tree | 1079e8257387643e799844983496a6ae1d4cd285 /src/usr | |
| parent | abc6a385d2f8b14d6f32a663712bea4bdd66ca77 (diff) | |
| download | talos-hostboot-c40793af8423dbdaeb2119c4498b2e086943da53.tar.gz talos-hostboot-c40793af8423dbdaeb2119c4498b2e086943da53.zip | |
SW262695: INITPROC: Tuleta systems fail at AIX Idle PMCFIR[11:17] LFIR_IDLE
Change-Id: I3ac5ebd5c3203cf6f973607defb5fcc9dfedd404
CQ:SW262695
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11211
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11213
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr')
| -rw-r--r-- | src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.H | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.H b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.H index f5a3920ef..94d2863b2 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.H +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pore_table_gen_api.H,v 1.24 2014/01/25 05:29:19 cmolsen Exp $ +// $Id: p8_pore_table_gen_api.H,v 1.25 2014/05/12 16:04:52 cmolsen Exp $ /*------------------------------------------------------------------------------*/ /* *! (C) Copyright International Business Machines Corp. 2012 */ /* *! All Rights Reserved -- Property of IBM */ @@ -120,8 +120,9 @@ CONST_UINT64_T( EX_PERV_SCRATCH5 , ULL(0x10013288) ); CONST_UINT64_T( EX_PERV_SCRATCH6 , ULL(0x10013289) ); CONST_UINT64_T( EX_PERV_SCRATCH7 , ULL(0x1001328A) ); -// RAM Status reg settings. -CONST_UINT64_T( RAM_STATUS_REG_AFTER_RAM, 0x5000000000000000); +// Ramming settings. +CONST_UINT64_T( RAM_STATUS_REG_AFTER_RAM, 0x5000000000000000); +CONST_UINT64_T( RAM_COMPLETE_POLLS, 0x0000000000000040); // mfspr gpr0, scratch0 opcode left-shifted 29 bits, ready for ramming. CONST_UINT64_T( MTSPR_SCRATCH0_GPR0_RAM_READY, (0x000000007C1543A6<<29)); |
