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authorThi Tran <thi@us.ibm.com>2013-08-29 13:11:46 -0500
committerA. Patrick Williams III <iawillia@us.ibm.com>2013-09-11 14:39:01 -0500
commit5c3ade25a9bc86a41a4a9840202ead6ae4f3e7fc (patch)
tree7276854e2094f1d0428544794e5803ea7ca1d105 /src/usr
parent782de5edafdbc02a756cd6eadb6dfc551496df85 (diff)
downloadtalos-hostboot-5c3ade25a9bc86a41a4a9840202ead6ae4f3e7fc.tar.gz
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Hostboot - Only init PLLs on functional portions of chip
SW196844 Change-Id: I28e7b18cce88abaff0de54e8ff01341ed2d3c49b Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5970 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr')
-rw-r--r--src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C82
1 files changed, 74 insertions, 8 deletions
diff --git a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
index 5f0f338b9..81d19258b 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
@@ -129,13 +129,46 @@ void* call_proc_a_x_pci_dmi_pll_initf( void *io_pArgs )
"Running proc_a_x_pci_dmi_pll_initf HWP on "
"target HUID %.8X", TARGETING::get_huid(l_proc_target));
+ bool l_startXbusPll = false;
+ bool l_startAbusPll = false;
+ bool l_startPCIEPll = false;
+ bool l_startDMIPll = false;
+
+ TARGETING::TargetHandleList l_xbus;
+ getChildChiplets( l_xbus, l_proc_target, TYPE_XBUS );
+ if (l_xbus.size() > 0)
+ {
+ l_startXbusPll = true;
+ }
+
+ TARGETING::TargetHandleList l_abus;
+ getChildChiplets( l_abus, l_proc_target, TYPE_ABUS );
+ if (l_abus.size() > 0)
+ {
+ l_startAbusPll = true;
+ }
+
+ TARGETING::TargetHandleList l_pci;
+ getChildChiplets( l_pci, l_proc_target, TYPE_PCI );
+ if (l_pci.size() > 0)
+ {
+ l_startPCIEPll = true;
+ }
+
+ TARGETING::TargetHandleList l_mcs;
+ getChildChiplets( l_mcs, l_proc_target, TYPE_MCS );
+ if (l_mcs.size() > 0)
+ {
+ l_startDMIPll = true;
+ }
+
// call proc_a_x_pci_dmi_pll_initf
FAPI_INVOKE_HWP(l_err, proc_a_x_pci_dmi_pll_initf,
l_fapi_proc_target,
- true, // xbus
- true, // abus
- true, // pcie
- true); // dmi
+ l_startXbusPll, // xbus
+ l_startAbusPll, // abus
+ l_startPCIEPll, // pcie
+ l_startDMIPll); // dmi
if (l_err)
{
@@ -206,13 +239,46 @@ void* call_proc_a_x_pci_dmi_pll_setup( void *io_pArgs )
"Running proc_a_x_pci_dmi_pll_setup HWP on "
"target HUID %.8X", TARGETING::get_huid(l_proc_target));
+ bool l_startXbusPll = false;
+ bool l_startAbusPll = false;
+ bool l_startPCIEPll = false;
+ bool l_startDMIPll = false;
+
+ TARGETING::TargetHandleList l_xbus;
+ getChildChiplets( l_xbus, l_proc_target, TYPE_XBUS );
+ if (l_xbus.size() > 0)
+ {
+ l_startXbusPll = true;
+ }
+
+ TARGETING::TargetHandleList l_abus;
+ getChildChiplets( l_abus, l_proc_target, TYPE_ABUS );
+ if (l_abus.size() > 0)
+ {
+ l_startAbusPll = true;
+ }
+
+ TARGETING::TargetHandleList l_pci;
+ getChildChiplets( l_pci, l_proc_target, TYPE_PCI );
+ if (l_pci.size() > 0)
+ {
+ l_startPCIEPll = true;
+ }
+
+ TARGETING::TargetHandleList l_mcs;
+ getChildChiplets( l_mcs, l_proc_target, TYPE_MCS );
+ if (l_mcs.size() > 0)
+ {
+ l_startDMIPll = true;
+ }
+
// call proc_a_x_pci_dmi_pll_setup
FAPI_INVOKE_HWP(l_err, proc_a_x_pci_dmi_pll_setup,
l_fapi_proc_target,
- true, // xbus
- true, // abus
- true, // pcie
- true); // dmi
+ l_startXbusPll, // xbus
+ l_startAbusPll, // abus
+ l_startPCIEPll, // pcie
+ l_startDMIPll); // dmi
if (l_err)
{
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