diff options
author | Thi Tran <thi@us.ibm.com> | 2015-11-20 11:31:31 -0600 |
---|---|---|
committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2015-12-09 17:49:34 -0600 |
commit | cc8eb026f1e16e9b810797d831dc47b614cffc05 (patch) | |
tree | cde76ab81d0f80aa467f8a26343038e34d85b53f /src/usr | |
parent | 156c3958175c6c07b1b07d56b50ac4e043bb4647 (diff) | |
download | talos-hostboot-cc8eb026f1e16e9b810797d831dc47b614cffc05.tar.gz talos-hostboot-cc8eb026f1e16e9b810797d831dc47b614cffc05.zip |
SW328360: HW PROC: Update to proc_setup_bars to support group = chip
Change-Id: Ibeb2d3f51462616368c9d41332f30d8023e5c006
CQ:SW328360
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22232
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22239
Tested-by: Jenkins Server
Tested-by: Jenkins OP Build CI
Tested-by: Jenkins OP HW
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr')
3 files changed, 72 insertions, 32 deletions
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C index c20bc97e3..2315b73cd 100644 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_setup_bars.C,v 1.28 2015/04/14 22:19:55 jmcgill Exp $ +// $Id: proc_setup_bars.C,v 1.29 2015/11/10 19:39:58 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.C,v $ //------------------------------------------------------------------------------ // *| @@ -992,6 +992,7 @@ fapi::ReturnCode proc_setup_bars_process_chip( uint8_t pcie_enabled; uint8_t nx_enabled; uint8_t nv_present; + uint8_t init_group_as_chip; uint8_t dual_capp_present; // mark function entry @@ -1073,6 +1074,17 @@ fapi::ReturnCode proc_setup_bars_process_chip( io_smp_chip.pcie_enabled = (pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE); + // configure group BARs to cover chip ranges? + rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_INIT_GROUP_BARS_AS_CHIP_BARS, + &(io_smp_chip.chip->this_chip), + init_group_as_chip); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_CHIP_EC_FEATURE_INIT_GROUP_BARS_AS_CHIP_BARS"); + break; + } + io_smp_chip.init_group_as_chip = (init_group_as_chip != 0); + // get NV link presence attribute rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_NV_PRESENT, &(io_smp_chip.chip->this_chip), @@ -2668,17 +2680,23 @@ proc_setup_bars_write_local_node_region_bars( FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Start"); + // set non-mirrored/mirrored ranges based on group=chip EC feature attribute + proc_setup_bars_addr_range non_mirrored_range = + ((i_smp_chip.init_group_as_chip)?(i_smp_chip.non_mirrored_range):(i_smp_node.non_mirrored_range)); + proc_setup_bars_addr_range mirrored_range = + ((i_smp_chip.init_group_as_chip)?(i_smp_chip.mirrored_range):(i_smp_node.mirrored_range)); + do { // NX (non-mirrored) - if (i_smp_node.non_mirrored_range.enabled && i_smp_chip.nx_enabled) + if (non_mirrored_range.enabled && i_smp_chip.nx_enabled) { FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX CXA0 APC Group Non-Mirrored BAR register"); rc = proc_setup_bars_common_write_bar_reg( i_smp_chip.chip->this_chip, NX_APC_GROUP_BAR0_0x0201302F, common_nf_scope_bar_reg_def, - i_smp_node.non_mirrored_range); + non_mirrored_range); if (!rc.ok()) { FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); @@ -2692,7 +2710,7 @@ proc_setup_bars_write_local_node_region_bars( i_smp_chip.chip->this_chip, NX_CXA1_APC_GROUP_BAR0_0x020131AF, common_nf_scope_bar_reg_def, - i_smp_node.non_mirrored_range); + non_mirrored_range); if (!rc.ok()) { FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); @@ -2705,7 +2723,7 @@ proc_setup_bars_write_local_node_region_bars( i_smp_chip.chip->this_chip, NX_GROUP_BAR0_0x02013097, common_nf_scope_bar_reg_def, - i_smp_node.non_mirrored_range); + non_mirrored_range); if (!rc.ok()) { FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); @@ -2714,14 +2732,14 @@ proc_setup_bars_write_local_node_region_bars( } // NX (mirrored) - if (i_smp_node.mirrored_range.enabled && i_smp_chip.nx_enabled) + if (mirrored_range.enabled && i_smp_chip.nx_enabled) { FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX CXA0 APC Group Mirrored BAR register"); rc = proc_setup_bars_common_write_bar_reg( i_smp_chip.chip->this_chip, NX_APC_GROUP_BAR1_0x02013030, common_nf_scope_bar_reg_def, - i_smp_node.mirrored_range); + mirrored_range); if (!rc.ok()) { FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); @@ -2735,7 +2753,7 @@ proc_setup_bars_write_local_node_region_bars( i_smp_chip.chip->this_chip, NX_CXA1_APC_GROUP_BAR1_0x020131B0, common_nf_scope_bar_reg_def, - i_smp_node.mirrored_range); + mirrored_range); if (!rc.ok()) { FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); @@ -2748,7 +2766,7 @@ proc_setup_bars_write_local_node_region_bars( i_smp_chip.chip->this_chip, NX_GROUP_BAR1_0x02013098, common_nf_scope_bar_reg_def, - i_smp_node.mirrored_range); + mirrored_range); if (!rc.ok()) { FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); @@ -2756,7 +2774,7 @@ proc_setup_bars_write_local_node_region_bars( } } // NPU (non-mirrored) - if (i_smp_chip.non_mirrored_range.enabled && i_smp_chip.nv_present) + if (non_mirrored_range.enabled && i_smp_chip.nv_present) { for (uint8_t u = 0; u < PROC_SETUP_BARS_NPU_NUM_UNITS; u++) { @@ -2765,7 +2783,7 @@ proc_setup_bars_write_local_node_region_bars( i_smp_chip.chip->this_chip, PROC_SETUP_BARS_NPU_NODE_NON_MIRRORED_BAR[u], common_nf_scope_bar_reg_def, - i_smp_node.non_mirrored_range); + non_mirrored_range); if (!rc.ok()) { FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); @@ -2780,7 +2798,7 @@ proc_setup_bars_write_local_node_region_bars( } // NPU (mirrored) - if (i_smp_chip.mirrored_range.enabled && i_smp_chip.nv_present) + if (mirrored_range.enabled && i_smp_chip.nv_present) { for (uint8_t u = 0; u < PROC_SETUP_BARS_NPU_NUM_UNITS; u++) { @@ -2789,7 +2807,7 @@ proc_setup_bars_write_local_node_region_bars( i_smp_chip.chip->this_chip, PROC_SETUP_BARS_NPU_NODE_MIRRORED_BAR[u], common_nf_scope_bar_reg_def, - i_smp_node.mirrored_range); + mirrored_range); if (!rc.ok()) { FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); @@ -2803,12 +2821,12 @@ proc_setup_bars_write_local_node_region_bars( } // L3 (non-mirrored) - if (i_smp_node.non_mirrored_range.enabled) + if (non_mirrored_range.enabled) { rc = proc_setup_bars_l3_write_local_node_memory_bar_attr( &(i_smp_chip.chip->this_chip), true, - i_smp_node.non_mirrored_range, + non_mirrored_range, i_smp_chip.non_mirrored_range); if (!rc.ok()) @@ -2819,12 +2837,12 @@ proc_setup_bars_write_local_node_region_bars( } // L3 (mirrored) - if (i_smp_node.mirrored_range.enabled) + if (mirrored_range.enabled) { rc = proc_setup_bars_l3_write_local_node_memory_bar_attr( &(i_smp_chip.chip->this_chip), false, - i_smp_node.mirrored_range, + mirrored_range, i_smp_chip.mirrored_range); if (!rc.ok()) @@ -2840,8 +2858,8 @@ proc_setup_bars_write_local_node_region_bars( rc = proc_setup_bars_pcie_write_local_node_memory_bars( i_smp_chip.chip->this_chip, i_smp_chip.num_phb, - i_smp_node.non_mirrored_range, - i_smp_node.mirrored_range); + non_mirrored_range, + mirrored_range); if (!rc.ok()) { FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_pcie_write_local_node_memory_bars"); diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H index 2870ed53b..7e70a1e4d 100644 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_setup_bars_defs.H,v 1.4 2015/02/02 18:58:18 jmcgill Exp $ +// $Id: proc_setup_bars_defs.H,v 1.6 2015/11/10 19:39:58 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars_defs.H,v $ //------------------------------------------------------------------------------ // *| @@ -247,6 +247,7 @@ struct proc_setup_bars_smp_chip bool nx_enabled; bool pcie_enabled; bool nv_present; + bool init_group_as_chip; bool dual_capp_present; // number of valid PCIe PHBs uint8_t num_phb; @@ -440,15 +441,16 @@ struct proc_setup_bars_hca_nm_bar_size static std::map<uint64_t, uint64_t> create_map() { std::map<uint64_t, uint64_t> m; - m[PROC_SETUP_BARS_SIZE_1_TB] = 0xFFULL; - m[PROC_SETUP_BARS_SIZE_512_GB] = 0x7FULL; - m[PROC_SETUP_BARS_SIZE_256_GB] = 0x3FULL; - m[PROC_SETUP_BARS_SIZE_128_GB] = 0x1FULL; - m[PROC_SETUP_BARS_SIZE_64_GB] = 0x0FULL; - m[PROC_SETUP_BARS_SIZE_32_GB] = 0x07ULL; - m[PROC_SETUP_BARS_SIZE_16_GB] = 0x03ULL; - m[PROC_SETUP_BARS_SIZE_8_GB] = 0x01ULL; - m[PROC_SETUP_BARS_SIZE_4_GB] = 0x00ULL; + m[PROC_SETUP_BARS_SIZE_2_TB] = 0x1FFULL; + m[PROC_SETUP_BARS_SIZE_1_TB] = 0x0FFULL; + m[PROC_SETUP_BARS_SIZE_512_GB] = 0x07FULL; + m[PROC_SETUP_BARS_SIZE_256_GB] = 0x03FULL; + m[PROC_SETUP_BARS_SIZE_128_GB] = 0x01FULL; + m[PROC_SETUP_BARS_SIZE_64_GB] = 0x00FULL; + m[PROC_SETUP_BARS_SIZE_32_GB] = 0x007ULL; + m[PROC_SETUP_BARS_SIZE_16_GB] = 0x003ULL; + m[PROC_SETUP_BARS_SIZE_8_GB] = 0x001ULL; + m[PROC_SETUP_BARS_SIZE_4_GB] = 0x000ULL; return m; } static const std::map<uint64_t, uint64_t> xlate_map; @@ -1000,8 +1002,8 @@ const proc_setup_bars_bar_reg_def hca_nm_bar_reg_def = 31, false, // enable: bit 63 (off for SW258328) 63, - true, // size: bits 33:40 - 33, + true, // size: bits 32:40 + 32, 40, &proc_setup_bars_hca_nm_bar_size::xlate_map, 0x0ULL, diff --git a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml index 2151ef8f5..fb81eebde 100644 --- a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml +++ b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml @@ -22,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_chip_ec_feature.xml,v 1.62 2015/06/29 01:45:13 jmcgill Exp $ --> +<!-- $Id: proc_chip_ec_feature.xml,v 1.63 2015/11/10 19:38:14 jmcgill Exp $ --> <!-- Defines the attributes that are based on EC level --> <attributes> <!-- ********************************************************************* --> @@ -124,6 +124,26 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_INIT_GROUP_BARS_AS_CHIP_BARS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Returns true if the fabric unit BARs which track group memory ranges + should be initialized to track the chip memory range instead of the + group memory range. True if: + Naples EC 0x10 or greater + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NAPLES</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_PCI_NEST_FIR_ACTION2_PRESENT</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> |