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authorDean Sanner <dsanner@us.ibm.com>2015-11-10 07:33:39 -0600
committerPatrick Williams <iawillia@us.ibm.com>2015-12-11 13:56:27 -0600
commit1d7b38ba816f52b12e0c131ec5daf86b00886c63 (patch)
treef2ad0a1036582ac20abc1d6c931f78a135acd4ea /src/usr
parent90245203585d4212f507770094183aca1f73c4e6 (diff)
downloadtalos-hostboot-1d7b38ba816f52b12e0c131ec5daf86b00886c63.tar.gz
talos-hostboot-1d7b38ba816f52b12e0c131ec5daf86b00886c63.zip
Establish a working P9 Hostboot and Simics base
Includes changes for nimbus.por Making recent Simics usable by Hostboot Removing portions of code not yet ready Basic LPC read/write Change-Id: Ic40a9613934fab7bb6a28a8100685496246bb5ea RTC:132170 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21931 Tested-by: Jenkins Server Reviewed-by: WILLIAM G. HOFFA <wghoffa@us.ibm.com> Reviewed-by: Christian Geddes <crgeddes@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr')
-rw-r--r--src/usr/hwas/common/hwas.C12
-rw-r--r--src/usr/hwpf/hwp/start_payload/start_payload.C7
-rwxr-xr-xsrc/usr/i2c/i2c.C3
-rw-r--r--src/usr/initservice/extinitsvc/extinitsvctasks.H6
-rw-r--r--src/usr/initservice/istepdispatcher/istepdispatcher.C4
-rw-r--r--src/usr/lpc/lpcdd.C275
-rw-r--r--src/usr/lpc/lpcdd.H126
-rw-r--r--src/usr/mbox/mailboxsp.C6
-rw-r--r--src/usr/mbox/mbox_dma_buffer.C3
-rw-r--r--src/usr/pnor/HBconfig6
-rw-r--r--src/usr/pnor/pnorrp.C3
-rw-r--r--src/usr/pnor/test/sfc_ast2400test.H71
-rwxr-xr-x[-rw-r--r--]src/usr/targeting/attrrp.C2
-rwxr-xr-x[-rw-r--r--]src/usr/targeting/attrrp_common.C6
-rwxr-xr-x[-rw-r--r--]src/usr/targeting/common/predicates/predicatepostfixexpr.C12
-rwxr-xr-x[-rw-r--r--]src/usr/targeting/common/xmltohb/common.mk3
-rwxr-xr-xsrc/usr/targeting/common/xmltohb/simics_NIMBUS.mrw.xml26
-rw-r--r--src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml34
-rwxr-xr-x[-rw-r--r--]src/usr/targeting/common/xmltohb/target_types.xml24
-rwxr-xr-x[-rw-r--r--]src/usr/targeting/common/xmltohb/target_types_hb.xml201
-rwxr-xr-x[-rw-r--r--]src/usr/targeting/common/xmltohb/vbu_NAPLES.mrw.xml6
-rwxr-xr-xsrc/usr/targeting/common/xmltohb/xmltohb.pl6
-rwxr-xr-x[-rw-r--r--]src/usr/targeting/targetservicestart.C2
-rw-r--r--src/usr/xscom/piberror.C7
-rw-r--r--src/usr/xscom/xscom.C3
-rw-r--r--src/usr/xscom/xscom.H18
26 files changed, 470 insertions, 402 deletions
diff --git a/src/usr/hwas/common/hwas.C b/src/usr/hwas/common/hwas.C
index 2e6445415..d5d8521a6 100644
--- a/src/usr/hwas/common/hwas.C
+++ b/src/usr/hwas/common/hwas.C
@@ -370,8 +370,9 @@ errlHndl_t discoverTargets()
if (l_procEntry.maxEXs == 0)
{
// this is PROBABLY bad PR, so YELL...
- HWAS_ERR("pTarget %.8X - PR VPD says 0 CORES",
- pTarget->getAttr<ATTR_HUID>());
+ // @todo RTC:137627 - remove for P9 bringup
+ //HWAS_ERR("pTarget %.8X - PR VPD says 0 CORES",
+ // pTarget->getAttr<ATTR_HUID>());
}
}
}
@@ -927,6 +928,9 @@ errlHndl_t restrictEXunits(
HWAS_INF("restrictEXunits entry, %d elements", i_procList.size());
errlHndl_t errl = NULL;
+ // @todo RTC:137627 - return from restrictEXunits for P9 bringup
+ return errl;
+
// sort by group so PROC# are in the right groupings.
std::sort(i_procList.begin(), i_procList.end(),
compareProcGroup);
@@ -1414,6 +1418,8 @@ errlHndl_t checkMinimumHardware(const TARGETING::ConstTargetHandle_t i_nodeOrSys
HWAS_DBG( "checkMinimumHardware: %d functional dimms",
l_dimms.size());
+// @todo RTC:137627 - remov dimm stuff for P9 bringup
+#if (0)
if (l_dimms.empty())
{
HWAS_ERR( "Insufficient hardware to continue IPL (func DIMM)");
@@ -1526,7 +1532,7 @@ errlHndl_t checkMinimumHardware(const TARGETING::ConstTargetHandle_t i_nodeOrSys
errlCommit(l_errl, HWAS_COMP_ID);
// errl is now NULL
}
-
+#endif
// ------------------------------------------------------------
// Check for Mirrored memory -
// If the user requests mirrored memory and we do not have it,
diff --git a/src/usr/hwpf/hwp/start_payload/start_payload.C b/src/usr/hwpf/hwp/start_payload/start_payload.C
index c582696a0..27bf4b780 100644
--- a/src/usr/hwpf/hwp/start_payload/start_payload.C
+++ b/src/usr/hwpf/hwp/start_payload/start_payload.C
@@ -567,7 +567,10 @@ void* call_host_start_payload( void *io_pArgs )
if( l_errl == NULL )
{
+// todo RTC:137627 - remove for P9 bringup
+#if (0)
l_errl = disableSpecialWakeup();
+#endif
}
if( l_errl == NULL )
@@ -721,6 +724,8 @@ errlHndl_t callShutdown ( uint64_t i_masterInstance,
}
+// @todo RTC:137627 - remove i2cSetupActiveMasters for P9 bringup
+#if (0)
// Phyp needs us to program all of the I2C masters with the bus
// divisor
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
@@ -733,7 +738,7 @@ errlHndl_t callShutdown ( uint64_t i_masterInstance,
// just commit the error and keep going
errlCommit(err, ISTEP_COMP_ID);
}
-
+#endif
// Get Target Service, and the system target.
TargetService& tS = targetService();
TARGETING::Target* sys = NULL;
diff --git a/src/usr/i2c/i2c.C b/src/usr/i2c/i2c.C
index e88504f23..0b77c1b03 100755
--- a/src/usr/i2c/i2c.C
+++ b/src/usr/i2c/i2c.C
@@ -2898,10 +2898,13 @@ errlHndl_t i2cResetActiveMasters ( i2cProcessType i_resetType,
"i_functional=%d",
i_resetType, i_functional );
+ // @todo RTC:137627 - remove for P9 bringup
+#if (0)
err = i2cProcessActiveMasters (i_resetType, // select engines
I2C_OP_RESET, // reset engines
I2C_BUS_SPEED_FROM_MRW,
i_functional);
+#endif
TRACFCOMP( g_trac_i2c,
EXIT_MRK"i2cResetActiveMasters(): err rc=0x%X, plid=0x%X",
diff --git a/src/usr/initservice/extinitsvc/extinitsvctasks.H b/src/usr/initservice/extinitsvc/extinitsvctasks.H
index 6e2cf324e..959f19b68 100644
--- a/src/usr/initservice/extinitsvc/extinitsvctasks.H
+++ b/src/usr/initservice/extinitsvc/extinitsvctasks.H
@@ -96,6 +96,8 @@ const TaskInfo g_exttaskinfolist[] = {
}
},
+ // @todo RTC:126643 P9 interrupt support
+#if (0)
/**
* @brief External interrupt resource provider
*/
@@ -107,6 +109,7 @@ const TaskInfo g_exttaskinfolist[] = {
EXT_IMAGE, // Extended Module
}
},
+#endif
/**
* @brief Mailbox service provider
@@ -285,6 +288,8 @@ const TaskInfo g_exttaskinfolist[] = {
}
},
+ // @todo RTC:137627 - remove for p9 bringup
+#if (0)
/**
* @brief Start slave threads
*/
@@ -304,6 +309,7 @@ const TaskInfo g_exttaskinfolist[] = {
EXT_IMAGE, // Extended Module
}
},
+#endif
/**
* @brief bus_training library.
diff --git a/src/usr/initservice/istepdispatcher/istepdispatcher.C b/src/usr/initservice/istepdispatcher/istepdispatcher.C
index aaf476f0e..794afc295 100644
--- a/src/usr/initservice/istepdispatcher/istepdispatcher.C
+++ b/src/usr/initservice/istepdispatcher/istepdispatcher.C
@@ -737,6 +737,9 @@ errlHndl_t IStepDispatcher::doIstep(uint32_t i_istep,
TRACFCOMP(g_trac_initsvc, ERR_MRK"doIstep: Istep failed, plid 0x%x",
err->plid());
}
+
+// @todo RTC:137627 - Removed for P9 bringup
+#if (0)
// Check for any attentions and invoke PRD for analysis
// if not in MPIPL mode
else if ((true == theStep->taskflags.check_attn) &&
@@ -753,6 +756,7 @@ errlHndl_t IStepDispatcher::doIstep(uint32_t i_istep,
"checkForIplAttentions");
}
}
+#endif
#ifdef CONFIG_RECONFIG_LOOP_TESTS_ENABLE
// Read ATTR_RECONFIG_LOOP_TESTS_ENABLE attribute
diff --git a/src/usr/lpc/lpcdd.C b/src/usr/lpc/lpcdd.C
index db217bda4..1e421bbe8 100644
--- a/src/usr/lpc/lpcdd.C
+++ b/src/usr/lpc/lpcdd.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2014 */
+/* Contributors Listed Below - COPYRIGHT 2014,2015 */
/* [+] Google Inc. */
/* [+] International Business Machines Corp. */
/* */
@@ -378,8 +378,13 @@ LpcDD::LpcDD( TARGETING::Target* i_proc )
,iv_resetActive(false)
{
TRACFCOMP(g_trac_lpc, "LpcDD::LpcDD> " );
-
mutex_init( &iv_mutex );
+ LPCBase_t baseAddr = LPC_PHYS_BASE + LPC_ADDR_START;
+
+
+ setLPCBaseAddr( static_cast<uint64_t *>(
+ mmio_dev_map(reinterpret_cast<void *>(baseAddr),
+ LPC_SPACE_SIZE )));
if( i_proc == TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL )
{
@@ -397,13 +402,14 @@ LpcDD::LpcDD( TARGETING::Target* i_proc )
ivp_mutex = &iv_mutex;
}
+ //@todo RTC:126644
// Initialize the hardware
- errlHndl_t l_errl = hwReset(LpcDD::RESET_INIT);
- if( l_errl )
- {
- TRACFCOMP( g_trac_lpc, "Errors initializing LPC logic... Beware! PLID=%.8X", l_errl->plid() );
- errlCommit(l_errl, LPC_COMP_ID);
- }
+// errlHndl_t l_errl = hwReset(LpcDD::RESET_INIT);
+// if( l_errl )
+// {
+// TRACFCOMP( g_trac_lpc, "Errors initializing LPC logic... Beware! PLID=%.8X", l_errl->plid() );
+// errlCommit(l_errl, LPC_COMP_ID);
+// }
}
LpcDD::~LpcDD()
@@ -411,13 +417,17 @@ LpcDD::~LpcDD()
mutex_destroy( &iv_mutex );
}
+
/**
* @brief Reset hardware to get into clean state
*/
errlHndl_t LpcDD::hwReset( ResetLevels i_resetLevel )
{
+ errlHndl_t l_err = NULL;
+// @todo RTC:133649 Support P9 LPC controller - error detection
+#if 0
TRACFCOMP( g_trac_lpc, ENTER_MRK"LpcDD::hwReset(i_resetLevel=%d)>", i_resetLevel );
- errlHndl_t l_err = NULL;
+
// check iv_resetActive to avoid infinite loops
// and don't reset if in the middle of FFDC collection
@@ -442,7 +452,6 @@ errlHndl_t LpcDD::hwReset( ResetLevels i_resetLevel )
{// Nothing to do here, so just break
break;
}
-
case RESET_INIT:
{
// Set OPB LPCM FIR Mask
@@ -509,7 +518,6 @@ errlHndl_t LpcDD::hwReset( ResetLevels i_resetLevel )
opsize );
if (l_err) { break; }
-
// Clear FIR register
scom_data_64 = ~(OPB_LPCM_FIR_ERROR_MASK);
l_err = deviceOp(
@@ -606,6 +614,7 @@ errlHndl_t LpcDD::hwReset( ResetLevels i_resetLevel )
}
TRACFCOMP( g_trac_lpc, EXIT_MRK"LpcDD::hwReset()=%.8X:%.4X", ERRL_GETEID_SAFE(l_err), ERRL_GETRC_SAFE(l_err) );
+#endif
return l_err;
}
@@ -615,7 +624,7 @@ errlHndl_t LpcDD::hwReset( ResetLevels i_resetLevel )
*/
errlHndl_t LpcDD::checkAddr(LPC::TransType i_type,
uint32_t i_addr,
- uint32_t *o_addr)
+ uint64_t *o_addr)
{
bool invalid_address = false;
switch ( i_type )
@@ -626,7 +635,7 @@ errlHndl_t LpcDD::checkAddr(LPC::TransType i_type,
invalid_address = true;
break;
}
- *o_addr = i_addr + LPCHC_IO_SPACE;
+ *o_addr = getLPCBaseAddr()+ i_addr+ LPCHC_IO_SPACE- LPC_ADDR_START;
break;
case LPC::TRANS_MEM:
if( i_addr >= 0x10000000 )
@@ -634,17 +643,28 @@ errlHndl_t LpcDD::checkAddr(LPC::TransType i_type,
invalid_address = true;
break;
}
- *o_addr = i_addr + LPCHC_MEM_SPACE;
+
+ *o_addr = getLPCBaseAddr()+ i_addr+ LPCHC_MEM_SPACE- LPC_ADDR_START;
break;
case LPC::TRANS_FW:
- *o_addr = i_addr + LPCHC_FW_SPACE;
+ if( i_addr >= 0x10000000 )
+ {
+ invalid_address = true;
+ break;
+ }
+ *o_addr = getLPCBaseAddr()+ i_addr + LPCHC_FW_SPACE- LPC_ADDR_START;
break;
case LPC::TRANS_REG:
- *o_addr = i_addr + LPCHC_REG_SPACE;
+ if( i_addr >= 0x100 )
+ {
+ invalid_address = true;
+ break;
+ }
+ *o_addr =getLPCBaseAddr()+ i_addr + LPCHC_REG_SPACE- LPC_ADDR_START;
break;
case LPC::TRANS_ABS:
//Just use the address as given
- *o_addr = i_addr;
+ *o_addr = getLPCBaseAddr() + i_addr;
break;
default:
invalid_address = true;
@@ -683,37 +703,18 @@ errlHndl_t LpcDD::_readLPC(LPC::TransType i_type,
size_t& io_buflen)
{
errlHndl_t l_err = NULL;
- uint32_t l_addr = 0;
+ uint64_t l_addr = 0;
do {
// Generate the full absolute LPC address
l_err = checkAddr( i_type, i_addr, &l_addr );
if( l_err ) { break; }
- // Execute command.
- ControlReg_t eccb_cmd;
- eccb_cmd.data_len = io_buflen;
- eccb_cmd.read_op = 1;
- eccb_cmd.addr_len = sizeof(l_addr);
- eccb_cmd.address = l_addr;
- size_t scom_size = sizeof(uint64_t);
- l_err = deviceOp( DeviceFW::WRITE,
- iv_proc,
- &(eccb_cmd.data64),
- scom_size,
- DEVICE_SCOM_ADDRESS(ECCB_CTL_REG) );
- if( l_err ) { break; }
-
- // Poll for completion
- StatusReg_t eccb_stat;
- l_err = pollComplete( eccb_cmd, eccb_stat );
- if( l_err ) { break; }
// Copy data out to caller's buffer.
if( io_buflen <= sizeof(uint32_t) )
{
- uint32_t tmpbuf = eccb_stat.read_data;
- memcpy( o_buffer, &tmpbuf, io_buflen );
+ memcpy( o_buffer, reinterpret_cast<void*>(l_addr), io_buflen );
}
else
{
@@ -755,210 +756,21 @@ errlHndl_t LpcDD::_writeLPC(LPC::TransType i_type,
size_t& io_buflen)
{
errlHndl_t l_err = NULL;
- uint32_t l_addr = 0;
+ uint64_t l_addr = 0;
do {
// Generate the full absolute LPC address
l_err = checkAddr( i_type, i_addr, &l_addr );
if( l_err ) { break; }
- uint64_t eccb_data = 0;
- // Left-justify user data into data register.
- switch ( io_buflen )
- {
- case 1:
- eccb_data = static_cast<uint64_t>(
- *reinterpret_cast<const uint8_t*>( i_buffer ) ) << 56;
- break;
- case 2:
- eccb_data = static_cast<uint64_t>(
- *reinterpret_cast<const uint16_t*>( i_buffer ) ) << 48;
- break;
- case 4:
- eccb_data = static_cast<uint64_t>(
- *reinterpret_cast<const uint32_t*>( i_buffer ) ) << 32;
- break;
- default:
- TRACFCOMP( g_trac_lpc, "writeLPC> Unsupported buffer size : %d", io_buflen );
- assert( false );
- break;
- }
-
- // Write data out
- size_t scom_size = sizeof(uint64_t);
- l_err = deviceOp( DeviceFW::WRITE,
- iv_proc,
- &eccb_data,
- scom_size,
- DEVICE_SCOM_ADDRESS(ECCB_DATA_REG) );
- if( l_err ) { break; }
-
- // Execute command.
- ControlReg_t eccb_cmd;
- eccb_cmd.data_len = io_buflen;
- eccb_cmd.read_op = 0;
- eccb_cmd.addr_len = sizeof(l_addr);
- eccb_cmd.address = l_addr;
- l_err = deviceOp( DeviceFW::WRITE,
- iv_proc,
- &(eccb_cmd.data64),
- scom_size,
- DEVICE_SCOM_ADDRESS(ECCB_CTL_REG) );
- if( l_err ) { break; }
-
- // Poll for completion
- StatusReg_t eccb_stat;
- l_err = pollComplete( eccb_cmd, eccb_stat );
- if( l_err ) { break; }
+ memcpy(reinterpret_cast<void*>(l_addr), i_buffer, io_buflen);
} while(0);
return l_err;
}
-/**
- * @brief Poll for completion of LPC operation
- */
-errlHndl_t LpcDD::pollComplete(const ControlReg_t &i_ctrl,
- StatusReg_t& o_stat)
-{
- // Note: Caller must lock mutex before calling this function
- errlHndl_t l_err = NULL;
- ResetLevels l_resetLevel = RESET_CLEAR;
- do {
- uint64_t poll_time = 0;
- uint64_t loop = 0;
- do
- {
- size_t scom_size = sizeof(uint64_t);
- l_err = deviceOp( DeviceFW::READ,
- iv_proc,
- &(o_stat.data64),
- scom_size,
- DEVICE_SCOM_ADDRESS(ECCB_STAT_REG) );
- LPC_TRACFCOMP( g_trac_lpc, "writeLPC> Poll on ECCB Status, "
- "poll_time=0x%.16x, stat=0x%.16x",
- poll_time,
- o_stat.data64 );
- if( l_err )
- {
- break;
- }
-
- if( o_stat.op_done )
- {
- break;
- }
-
- // want to start out incrementing by small numbers then get bigger
- // to avoid a really tight loop in an error case so we'll increase
- // the wait each time through
- nanosleep( 0, ECCB_POLL_INCR_NS*(++loop) );
- poll_time += ECCB_POLL_INCR_NS * loop;
- } while ( poll_time < ECCB_POLL_TIME_NS );
-
- // Check for hw errors or timeout if no previous logs
- if( (l_err == NULL) &&
- ((o_stat.data64 & ECCB_STAT_REG_ERROR_MASK)
- || (!o_stat.op_done)) )
- {
- TRACFCOMP( g_trac_lpc, "LpcDD::pollComplete> LPC error or timeout: "
- "addr=0x%.8X, status=0x%.16X",
- i_ctrl.address, o_stat.data64 );
-
- if( i_ctrl.read_op )
- {
- /*@
- * @errortype
- * @moduleid LPC::MOD_LPCDD_READLPC
- * @reasoncode LPC::RC_ECCB_ERROR
- * @userdata1[0:31] LPC Address
- * @userdata1[32:63] Total poll time (ns)
- * @userdata2 ECCB Status Register
- * @devdesc LpcDD::pollComplete> LPC error or timeout
- * @custdesc Hardware error accessing internal
- * bus during IPL
- */
- l_err = new ERRORLOG::ErrlEntry(
- ERRORLOG::ERRL_SEV_UNRECOVERABLE,
- LPC::MOD_LPCDD_READLPC,
- LPC::RC_ECCB_ERROR,
- TWO_UINT32_TO_UINT64(
- i_ctrl.address, poll_time),
- o_stat.data64 );
- }
- else
- {
- /*@
- * @errortype
- * @moduleid LPC::MOD_LPCDD_WRITELPC
- * @reasoncode LPC::RC_ECCB_ERROR
- * @userdata1[0:31] LPC Address
- * @userdata1[32:63] Total poll time (ns)
- * @userdata2 ECCB Status Register
- * @devdesc LpcDD::pollComplete> LPC error or timeout
- * @custdesc Hardware error accessing internal
- * bus during IPL
- */
- l_err = new ERRORLOG::ErrlEntry(
- ERRORLOG::ERRL_SEV_UNRECOVERABLE,
- LPC::MOD_LPCDD_WRITELPC,
- LPC::RC_ECCB_ERROR,
- TWO_UINT32_TO_UINT64(
- i_ctrl.address, poll_time),
- o_stat.data64 );
- }
- // Limited in callout: no LPC sub-target, so calling out processor
- l_err->addHwCallout( iv_proc,
- HWAS::SRCI_PRIORITY_HIGH,
- HWAS::NO_DECONFIG,
- HWAS::GARD_NULL );
-
- addFFDC(l_err);
- l_err->collectTrace(LPC_COMP_NAME);
- l_err->collectTrace(XSCOM_COMP_NAME);
-
- // Reset ECCB - handled below
- l_resetLevel = RESET_ECCB;
-
- break;
- }
-
- // check for errors at OPB level
- l_err = checkForOpbErrors( l_resetLevel );
- if( l_err ) { break; }
-
- } while(0);
-
- // If we have an error that requires a reset, do that here
- if ( l_err && ( l_resetLevel != RESET_CLEAR ) )
- {
- errlHndl_t tmp_err = hwReset(l_resetLevel);
- if ( tmp_err )
- {
- // Commit reset error since we have original error l_err
- TRACFCOMP(g_trac_lpc, "LpcDD::pollComplete> Error from reset() after previous error eid=0x%X. Committing reset() error log eid=0x%X.", l_err->eid(), tmp_err->eid());
-
- tmp_err->setSev(ERRORLOG::ERRL_SEV_INFORMATIONAL);
- tmp_err->collectTrace(LPC_COMP_NAME);
- tmp_err->plid(l_err->plid());
- errlCommit(tmp_err, LPC_COMP_ID);
- }
-
- // Limited in callout: no LPC sub-target, so calling out processor
- l_err->addHwCallout( iv_proc,
- HWAS::SRCI_PRIORITY_HIGH,
- HWAS::NO_DECONFIG,
- HWAS::GARD_NULL );
-
- addFFDC(l_err);
- l_err->collectTrace(LPC_COMP_NAME);
- l_err->collectTrace(XSCOM_COMP_NAME);
- }
-
- return l_err;
-}
/**
* @brief Add Error Registers to an existing Error Log
@@ -975,11 +787,12 @@ void LpcDD::addFFDC(errlHndl_t & io_errl)
ERRORLOG::ErrlUserDetailsLogRegister l_eud(iv_proc);
+ // @todo RTC:133649 Support P9 LPC controller - error detection
// Add ECCB Status Register
- l_eud.addData(DEVICE_SCOM_ADDRESS(ECCB_STAT_REG));
+ //l_eud.addData(DEVICE_SCOM_ADDRESS(ECCB_STAT_REG));
// Add OPB LPC Master FIR
- l_eud.addData(DEVICE_SCOM_ADDRESS(OPB_LPCM_FIR_REG));
+ //l_eud.addData(DEVICE_SCOM_ADDRESS(OPB_LPCM_FIR_REG));
//@todo - add more LPC regs RTC:37744
//LPCIRQ_STATUS = 0x38
diff --git a/src/usr/lpc/lpcdd.H b/src/usr/lpc/lpcdd.H
index 460a031d7..48fefa64c 100644
--- a/src/usr/lpc/lpcdd.H
+++ b/src/usr/lpc/lpcdd.H
@@ -32,6 +32,8 @@
#include <errl/errlentry.H>
#include <lpc/lpcif.H>
+typedef uint64_t LPCBase_t;
+
/** @file lpcdd.H
* @brief Provides the interfaces to the LPC Device Driver
*/
@@ -40,6 +42,7 @@
* @brief LPC Device Driver Class
* Provides access to the LPC bus for a specific Processor
*/
+
class LpcDD
{
public:
@@ -109,6 +112,26 @@ class LpcDD
};
/**
+ * @brief Get the base address of the LPC space
+ *
+ * @return Pointer to base address
+ */
+ uint64_t getLPCBaseAddr(void)
+ {
+ return iv_lpcBaseAddr;
+ };
+
+ /**
+ * @brief Set the base address of the LPC space
+ *
+ * @return Void
+ */
+ void setLPCBaseAddr(uint64_t * i_baseLPCAddr)
+ {
+ iv_lpcBaseAddr = reinterpret_cast<uint64_t>(i_baseLPCAddr);
+ };
+
+ /**
* @brief Constructor
* @param[in] Processor target associated with the ECCB logic
*/
@@ -122,17 +145,6 @@ class LpcDD
~LpcDD();
protected:
- /**
- * @brief LPC HC Registers
- * These are offsets within the LPC Host Controller Register Space
- */
- enum LpcRegAddr {
- LPC_REG_BAR0 = 0x00, /**< BAR0 : OPB register */
- LPC_REG_BAR1 = 0x04, /**< BAR1 : LPC I/O space */
- LPC_REG_BAR2 = 0x08, /**< BAR2 : LPC Memory space */
- LPC_REG_BAR3 = 0x0C, /**< BAR3 : LPC Firmware space */
- LPC_REG_ABRTCNT = 0x2C, /**< ABORT COUNT */
- };
/**
@@ -145,19 +157,15 @@ class LpcDD
LPCHC_IO_SPACE = 0xD0010000, /**< LPC Host Controller I/O Space */
LPCHC_REG_SPACE = 0xC0012000, /**< LPC Host Ctlr Register Space */
- ECCB_NON_FW_RESET_REG = 0x000B0001, /**< ECCB Reset Reg (non-FW) */
+ /** Start of LPC Addr within the memory mapped space*/
+ LPC_ADDR_START = 0xC0000000,
+ /** Size that LPC takes up (0xC0000000 to 0xFFFFFFFF)*/
+ LPC_SPACE_SIZE = 0x40000000,
+ /** Physical addr of the start of LPC address space*/
+ LPC_PHYS_BASE = 0x6030000000000,
- ECCB_CTL_REG = 0x000B0020, /**< ECCB Control Reg (FW) */
- ECCB_RESET_REG = 0x000B0021, /**< ECCB Reset Reg (FW) */
- ECCB_STAT_REG = 0x000B0022, /**< ECCB Status Reg (FW) */
- ECCB_DATA_REG = 0x000B0023, /**< ECCB Data Reg (FW) */
- // Default Values to set for all operations
- // 1101.0100.0000.000x.0000.0001.0000.0000.<address>
- ECCB_CTL_REG_DEFAULT = 0xD400010000000000,
- // Error bits: 41-43, 56 (52=cmd complete) (not 57: only non-fw use)
- ECCB_STAT_REG_ERROR_MASK = 0x0000000000700080, /**< Error Bits */
/**< OPB LPCM Sync FIR Reg - used to read the FIR*/
OPB_LPCM_FIR_REG = 0x01010C00,
@@ -174,68 +182,10 @@ class LpcDD
OPB_MASTER_LS_CONTROL_REG = 0x008, /**<OPBM LS Control Reg */
LPCHC_RESET_REG = 0x0FC, /**<LPC HC Reset Register */
- ECCB_RESET_LPC_FAST_RESET = 1ULL << 62, /**< bit 1 = Fast reset */
-
- #ifndef CONFIG_SFC_IS_IBM_DPSS
- // Intel spec requires no LPC timeout during boot, however that guidance
- // presumes the system can still boot without the LPC, which is not true
- // for systems that require PNOR access. Therefore we'll allow plenty
- // of time for delays to work themselves out, but still flag an error
- // ahead of the watchdog timer expiring, so that it's easier to debug
- // any problems.
- ECCB_POLL_TIME_NS = 90000000, /**< max time should be 90s */
- #else
- ECCB_POLL_TIME_NS = 400000, /**< max time should be 400ms */
- #endif
- ECCB_POLL_INCR_NS = 10, /**< minimum increment during poll */
LPCHC_SYNC_CYCLE_COUNTER_INFINITE = 0xFF000000
};
- /**
- * @brief ECCB Control Register Layout
- */
- union ControlReg_t
- {
- uint64_t data64;
- struct
- {
- // unused sections should be set to zero
- uint64_t magic1 : 4; /**< 0:3 = b1101 per spec */
- uint64_t data_len : 4; /**< 4:7 = b0100 means 4 byte */
- uint64_t unused1 : 7; /**< 8:14 */
- uint64_t read_op : 1; /**< 15 = set for read operation */
- uint64_t unused2 : 7; /**< 16:22 */
- uint64_t addr_len : 3; /**< 23:25 = b100 means 4 byte */
- uint64_t unused3 : 6; /**< 26:31 */
- uint64_t address : 32; /**< 32:63 = LPC Address */
- };
-
- ControlReg_t() : data64(ECCB_CTL_REG_DEFAULT) {};
- };
-
- /**
- * @brief ECCB Status Register Layout
- */
- union StatusReg_t
- {
- uint64_t data64;
- struct
- {
- uint64_t unused : 6; /**< 0:5 */
- uint64_t read_data : 32; /**< 6:37 */
- uint64_t unused1 : 3; /**< 38:40 */
- uint64_t eccb_err : 3; /**< 41:43 = ECCB_Error_Info */
- uint64_t busy : 1; /**< 44 = Operation Busy */
- uint64_t unused2 : 7; /**< 45:51 */
- uint64_t op_done : 1; /**< 52 = Command Complete */
- uint64_t unused3 : 3; /**< 53:55 */
- uint64_t addr_parity_err : 1; /**< 56 = ECC Address Register
- Parity Error */
- uint64_t unused4 : 7; /**< 57:63 */
- };
- StatusReg_t() : data64(0) {};
- };
/**
* @brief OPB-LPCM FIR Register Layout
@@ -279,18 +229,7 @@ class LpcDD
*/
errlHndl_t checkAddr( LPC::TransType i_type,
uint32_t i_addr,
- uint32_t* o_addr );
-
- /**
- * @brief Poll for completion of LPC operation
- *
- * @param[in] i_ctrl Control register describing operation
- * @param[out] o_stat Status register for failures
- *
- * @return errlHndl_t NULL on success, else error log
- */
- errlHndl_t pollComplete( const ControlReg_t& i_ctrl,
- StatusReg_t& o_stat );
+ uint64_t* o_addr );
/**
* @brief Add Error Registers to an existing Error Log
@@ -373,6 +312,11 @@ class LpcDD
*/
bool iv_resetActive;
+ /**
+ * @brief Virtual Address of the begining of LPC address space
+ */
+ uint64_t iv_lpcBaseAddr;
+
};
diff --git a/src/usr/mbox/mailboxsp.C b/src/usr/mbox/mailboxsp.C
index 3f01cfd65..db3cc0979 100644
--- a/src/usr/mbox/mailboxsp.C
+++ b/src/usr/mbox/mailboxsp.C
@@ -170,11 +170,13 @@ errlHndl_t MailboxSp::_init()
}
}
+ // @todo RTC:126643
+#if (0)
// Register for IPC messages
err = INTR::registerMsgQ(iv_msgQ,
MSG_IPC,
INTR::ISN_INTERPROC);
-
+#endif
if(mbxComm)
{
@@ -2222,7 +2224,7 @@ void * MBOX::allocate(size_t i_size)
{
response = malloc(i_size);
}
-
+
return response;
}
diff --git a/src/usr/mbox/mbox_dma_buffer.C b/src/usr/mbox/mbox_dma_buffer.C
index ca333e1c8..dd372eccc 100644
--- a/src/usr/mbox/mbox_dma_buffer.C
+++ b/src/usr/mbox/mbox_dma_buffer.C
@@ -45,7 +45,8 @@ DmaBuffer::DmaBuffer() :
iv_dma_req_sent(false)
{
iv_head = reinterpret_cast<void*>(VmmManager::MBOX_DMA_ADDR);
- initPhysicalArea(iv_head, iv_phys_head);
+ // RTC:137627 - remove for P9 bringup
+ //initPhysicalArea(iv_head, iv_phys_head);
}
diff --git a/src/usr/pnor/HBconfig b/src/usr/pnor/HBconfig
index c780986a0..3b6843b14 100644
--- a/src/usr/pnor/HBconfig
+++ b/src/usr/pnor/HBconfig
@@ -1,11 +1,11 @@
config SFC_IS_IBM_DPSS
- default y
+ default n
depends on !SFC_IS_AST2400 && !SFC_IS_FAKE
help
The Serial Flash Controller is the IBM DPSS FPGA.
config SFC_IS_AST2400
- default n
+ default y
depends on !SFC_IS_IBM_DPSS && !SFC_IS_FAKE
help
The Serial Flash Controller is the AST2400 BMC.
@@ -17,7 +17,7 @@ config SFC_IS_FAKE
The Serial Flash Controller is emulated using memory.
config BMC_DOES_SFC_INIT
- default y
+ default n
help
The BMC is completely responsible for initializing and configuring the
SFC before Hostboot is started. The BMC is also responsible for doing
diff --git a/src/usr/pnor/pnorrp.C b/src/usr/pnor/pnorrp.C
index d2f739819..6b84e09e6 100644
--- a/src/usr/pnor/pnorrp.C
+++ b/src/usr/pnor/pnorrp.C
@@ -280,8 +280,6 @@ void PnorRP::initDaemon()
INITSERVICE::registerBlock(reinterpret_cast<void*>(BASE_VADDR),
TOTAL_SIZE,PNOR_PRIORITY);
-// @todo-RTC:127337 Fake PNOR support
-#if (0)
//Find and read the TOC in the PNOR to compute the sections and set
//their correct permissions
l_errhdl = findTOC();
@@ -307,7 +305,6 @@ void PnorRP::initDaemon()
// start task to wait on the queue
task_create( wait_for_message, NULL );
-#endif
} while(0);
if( l_errhdl )
diff --git a/src/usr/pnor/test/sfc_ast2400test.H b/src/usr/pnor/test/sfc_ast2400test.H
index 70e0d340b..60421515f 100644
--- a/src/usr/pnor/test/sfc_ast2400test.H
+++ b/src/usr/pnor/test/sfc_ast2400test.H
@@ -105,7 +105,9 @@ class SfcAST2400Test : public CxxTest::TestSuite
void test_FlashReads( void )
{
PnorDD& pnordd = Singleton<PnorDD>::instance();
- SfcAST2400* sfc = reinterpret_cast<SfcAST2400*>(pnordd.iv_sfc );
+
+ //todo RTC:133649 -- enable once LPC error handling is in place
+ // SfcAST2400* sfc = reinterpret_cast<SfcAST2400*>(pnordd.iv_sfc );
mutex_t* l_mutex = pnordd.iv_mutex_ptr;
errlHndl_t l_err = NULL;
@@ -135,37 +137,44 @@ class SfcAST2400Test : public CxxTest::TestSuite
return; //just give up if basic reads don't work
}
- // Put controller into command mode (instead of read mode)
- l_err = sfc->commandMode( true );
- if( l_err )
- {
- TS_FAIL("SfcAST2400Test::test_FlashReads> Error entering command mode");
- mutex_unlock(l_mutex);//unlock before commit
- errlCommit(l_err,PNOR_COMP_ID);
- mutex_lock(l_mutex);//lock again for next op
- }
-
- // Reads should fail
- l_err = pnordd._readFlash(base_address,
- l_size,
- &l_readData);
- if( !l_err )
- {
- TS_FAIL("SfcAST2400Test::test_FlashReads> Read did not fail in command mode");
- }
- else
- {
- delete l_err;
- }
-
- // Put controller back into read mode
- l_err = sfc->commandMode( false );
mutex_unlock(l_mutex);
- if( l_err )
- {
- TS_FAIL("SfcAST2400Test::test_FlashReads> Error exiting command mode");
- errlCommit(l_err,PNOR_COMP_ID);
- }
+// *****************************************************
+// Skipping test where we try to read in command mode
+// We know this will fail, currently no solution in place
+// to relay error from BMC to HB
+// todo RTC:133649 -- enable once LPC error handling is in place
+// ********************************
+// // Put controller into command mode (instead of read mode)
+// l_err = sfc->commandMode( true );
+// if( l_err )
+// {
+// TS_FAIL("SfcAST2400Test::test_FlashReads> Error entering command mode");
+// mutex_unlock(l_mutex);//unlock before commit
+// errlCommit(l_err,PNOR_COMP_ID);
+// mutex_lock(l_mutex);//lock again for next op
+// }
+//
+// // Reads should fail
+// l_err = pnordd._readFlash(base_address,
+// l_size,
+// &l_readData);
+// if( !l_err )
+// {
+// TS_FAIL("SfcAST2400Test::test_FlashReads> Read did not fail in command mode");
+// }
+// else
+// {
+// delete l_err;
+// }
+//
+// // Put controller back into read mode
+// l_err = sfc->commandMode( false );
+// mutex_unlock(l_mutex);
+// if( l_err )
+// {
+// TS_FAIL("SfcAST2400Test::test_FlashReads> Error exiting command mode");
+// errlCommit(l_err,PNOR_COMP_ID);
+// }
}
};
diff --git a/src/usr/targeting/attrrp.C b/src/usr/targeting/attrrp.C
index fbf61b892..de861eb01 100644..100755
--- a/src/usr/targeting/attrrp.C
+++ b/src/usr/targeting/attrrp.C
@@ -61,7 +61,7 @@ namespace TARGETING
void* AttrRP::startMsgServiceTask(void* i_pInstance)
{
// Call msgServiceTask loop on instance.
- TARG_ASSERT(i_pInstance);
+ TARG_ASSERT(i_pInstance, "No instance passed to startMsgServiceTask");
static_cast<AttrRP*>(i_pInstance)->msgServiceTask();
return NULL;
}
diff --git a/src/usr/targeting/attrrp_common.C b/src/usr/targeting/attrrp_common.C
index 9eb796fe1..69810898d 100644..100755
--- a/src/usr/targeting/attrrp_common.C
+++ b/src/usr/targeting/attrrp_common.C
@@ -5,7 +5,9 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* COPYRIGHT International Business Machines Corp. 2013,2014 */
+/* Contributors Listed Below - COPYRIGHT 2013,2015 */
+/* [+] International Business Machines Corp. */
+/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
@@ -54,7 +56,7 @@ namespace TARGETING
msg_q_destroy(iv_msgQ);
#endif
- TARG_ASSERT(false);
+ TARG_ASSERT(false, "Assert to exit ~AttrRP");
}
void AttrRP::init(errlHndl_t &io_taskRetErrl)
diff --git a/src/usr/targeting/common/predicates/predicatepostfixexpr.C b/src/usr/targeting/common/predicates/predicatepostfixexpr.C
index 75b699fae..413805da7 100644..100755
--- a/src/usr/targeting/common/predicates/predicatepostfixexpr.C
+++ b/src/usr/targeting/common/predicates/predicatepostfixexpr.C
@@ -5,7 +5,9 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* COPYRIGHT International Business Machines Corp. 2011,2014 */
+/* Contributors Listed Below - COPYRIGHT 2012,2015 */
+/* [+] International Business Machines Corp. */
+/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
@@ -181,7 +183,7 @@ bool PredicatePostfixExpr::operator()(
TARG_ASSERT(l_stack.size() >= 2,
TARG_LOC "Stack for AND must be >=2 but is %d",
- l_stack.size());
+ (uint32_t)(l_stack.size()));
// The stack now has two trailing items, LHS + RHS (back). If
// LHS is still in predicate form, evaluate it first, otherwise
@@ -210,7 +212,7 @@ bool PredicatePostfixExpr::operator()(
TARG_ASSERT(l_stack.size() >= 2,
TARG_LOC "Stack for OR must be >= 2 but is %d",
- l_stack.size());
+ (uint32_t)(l_stack.size()));
// The stack now has two trailing items, LHS + RHS (back). If
// LHS is still in predicate form, evaluate it first, otherwise
@@ -238,7 +240,7 @@ bool PredicatePostfixExpr::operator()(
case NOT:
TARG_ASSERT(l_stack.size() >= 1,
TARG_LOC "Stack for NOT must be >= 1 but is %d",
- l_stack.size());
+ (uint32_t)(l_stack.size()));
// The stack now has a trailing item, LHS (back). If LHS is
// still in predicate form, evaluate it first, otherwise
@@ -270,7 +272,7 @@ bool PredicatePostfixExpr::operator()(
TARG_ASSERT(l_stack.size() == 1,
TARG_LOC "Postfix expression created incorrectly. Stack "
"size should be 1 but is %d",
- l_stack.size());
+ (uint32_t)(l_stack.size()));
// The stack now has a trailing item, LHS (back). If LHS is still in
// predicate form, evaluate it first, otherwise use it directly. This
diff --git a/src/usr/targeting/common/xmltohb/common.mk b/src/usr/targeting/common/xmltohb/common.mk
index bdc529f20..c38b36672 100644..100755
--- a/src/usr/targeting/common/xmltohb/common.mk
+++ b/src/usr/targeting/common/xmltohb/common.mk
@@ -5,7 +5,7 @@
#
# OpenPOWER HostBoot Project
#
-# Contributors Listed Below - COPYRIGHT 2012,2014
+# Contributors Listed Below - COPYRIGHT 2012,2015
# [+] International Business Machines Corp.
#
#
@@ -54,6 +54,7 @@ XMLTOHB_SYSTEM_BINARIES += vbu_NAPLES_targeting.bin
XMLTOHB_SYSTEM_BINARIES += simics_VENICE_targeting.bin
XMLTOHB_SYSTEM_BINARIES += simics_MURANO_targeting.bin
XMLTOHB_SYSTEM_BINARIES += simics_NAPLES_targeting.bin
+XMLTOHB_SYSTEM_BINARIES += simics_NIMBUS_targeting.bin
XMLTOHB_TARGETS += ${XMLTOHB_HEADER_TARGETS}
XMLTOHB_TARGETS += ${XMLTOHB_SOURCE_TARGETS}
diff --git a/src/usr/targeting/common/xmltohb/simics_NIMBUS.mrw.xml b/src/usr/targeting/common/xmltohb/simics_NIMBUS.mrw.xml
new file mode 100755
index 000000000..18398d5d7
--- /dev/null
+++ b/src/usr/targeting/common/xmltohb/simics_NIMBUS.mrw.xml
@@ -0,0 +1,26 @@
+<!-- IBM_PROLOG_BEGIN_TAG -->
+<!-- This is an automatically generated prolog. -->
+<!-- -->
+<!-- $Source: src/usr/targeting/common/xmltohb/simics_NIMBUS.mrw.xml $ -->
+<!-- -->
+<!-- OpenPOWER HostBoot Project -->
+<!-- -->
+<!-- Contributors Listed Below - COPYRIGHT 2015 -->
+<!-- [+] International Business Machines Corp. -->
+<!-- -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
+<!-- implied. See the License for the specific language governing -->
+<!-- permissions and limitations under the License. -->
+<!-- -->
+<!-- IBM_PROLOG_END_TAG -->
+
+
diff --git a/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml b/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
index cdbee09e1..53df0adb8 100644
--- a/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
@@ -42,7 +42,7 @@
* Each Nimbus has 2 OBUS (OB0 and OB3)
* Each Nimbus has 2 NVBUS
* Each Nimbus has 21 PPE units (including the SBE):
- * 1 SBE, 1 Powerbus/Fabric PPE, 4 GPEs, 12 CMEs, and 3 IO PPEs. *
+ * 1 SBE, 1 Powerbus/Fabric PPE, 4 GPEs, 12 CMEs, and 3 IO PPEs. *
* Each chiplet existing in a Nimbus has 1 equivalent PERV unit
* Each Nimbus has 2 CAPP units
* Each Nimbus has 1 SBE unit
@@ -70,6 +70,22 @@
<id>EXECUTION_PLATFORM</id>
<default>1</default>
</attribute>
+ <attribute>
+ <id>SP_FUNCTIONS</id>
+ <default>
+ <field><id>fsiSlaveInit</id><value>0</value></field>
+ <field><id>mailboxEnabled</id><value>0</value></field>
+ <field><id>fsiMasterInit</id><value>0</value></field>
+ <field><id>hardwareChangeDetection</id><value>0</value></field>
+ <field><id>powerLineDisturbance</id><value>0</value></field>
+ <field><id>baseServices</id><value>0</value></field>
+ <field><id>reserved</id><value>0</value></field>
+ </default>
+ </attribute>
+ <attribute>
+ <id>NEST_FREQ_MHZ</id>
+ <default>0x960</default>
+ </attribute>
</targetInstance>
<!-- System node 0 -->
@@ -99,8 +115,8 @@
<attribute><id>POSITION</id><default>4</default></attribute>
<attribute><id>SCOM_SWITCHES</id>
<default>
- <field><id>useFsiScom</id><value>1</value></field>
- <field><id>useXscom</id><value>0</value></field>
+ <field><id>useFsiScom</id><value>0</value></field>
+ <field><id>useXscom</id><value>1</value></field>
<field><id>useInbandScom</id><value>0</value></field>
<field><id>reserved</id><value>0</value></field>
</default>
@@ -197,6 +213,10 @@
<attribute><id>PROC_DCM_INSTALLED</id>
<default>0</default>
</attribute>
+ <attribute>
+ <id>PROC_MASTER_TYPE</id>
+ <default>ACTING_MASTER</default>
+ </attribute>
</targetInstance>
<!-- Nimbus n0p0 EQ units -->
@@ -1805,10 +1825,10 @@
<id>CHIP_UNIT</id>
<default>0</default>
</attribute>
- <attribute>
+<!-- <attribute> // @FIXME RTC 127337
<id>PEER_TARGET</id>
<default>physical:sys-0/node-0/proc-1/xbus-1</default>
- </attribute>
+ </attribute> // @FIXME RTC 127337 -->
</targetInstance>
<targetInstance>
@@ -1827,10 +1847,10 @@
<id>CHIP_UNIT</id>
<default>0</default>
</attribute>
- <attribute>
+<!-- <attribute> // @FIXME RTC 127337
<id>PEER_TARGET</id>
<default>physical:sys-0/node-0/proc-2/xbus-1</default>
- </attribute>
+ </attribute> // @FIXME RTC 127337 -->
</targetInstance>
<!-- nimbus n0p0 CAPP units -->
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 8d1ed2eef..efb45894f 100644..100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -1854,6 +1854,7 @@
<id>IS_SIMULATION</id>
<default>0</default>
</attribute>
+ <attribute><id>HB_HRMOR_NODAL_BASE</id></attribute>
<!-- Max/min config attributes -->
<attribute><id>MAX_PROC_CHIPS_PER_NODE</id></attribute>
<attribute><id>MAX_EXS_PER_PROC_CHIP</id></attribute>
@@ -1948,9 +1949,6 @@
<attribute><id>OPT_MEMMAP_GROUP_POLICY</id></attribute>
<attribute><id>BRAZOS_RX_FIFO_OVERRIDE</id></attribute>
<attribute><id>MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL</id></attribute>
- <attribute><id>SP_FUNCTIONS</id></attribute>
- <attribute><id>HB_SETTINGS</id></attribute>
- <attribute><id>PAYLOAD_KIND</id></attribute>
<attribute><id>MAX_PROC_CHIPS_PER_NODE</id></attribute>
<attribute><id>MAX_EXS_PER_PROC_CHIP</id></attribute>
<attribute><id>MAX_MBAS_PER_MEMBUF_CHIP</id></attribute>
@@ -1960,6 +1958,26 @@
<attribute><id>MAX_MCS_PER_SYSTEM</id></attribute>
<attribute><id>FABRIC_TO_PHYSICAL_NODE_MAP</id></attribute>
<attribute><id>RUN_MAX_MEM_PATTERNS</id></attribute>
+ <attribute><id>HIDDEN_ERRLOGS_ENABLE</id></attribute>
+ <attribute><id>SP_FUNCTIONS</id></attribute>
+ <attribute><id>HB_SETTINGS</id></attribute>
+ <attribute><id>CEC_IPL_TYPE</id></attribute>
+ <attribute><id>PAYLOAD_KIND</id></attribute>
+ <attribute><id>PAYLOAD_BASE</id></attribute>
+ <attribute><id>PAYLOAD_ENTRY</id></attribute>
+ <attribute><id>NEST_FREQ_MHZ</id></attribute>
+ <attribute><id>MFG_TRACE_ENABLE</id></attribute>
+ <attribute><id>ENABLED_THREADS</id></attribute>
+ <attribute><id>ISTEP_MODE</id></attribute>
+ <attribute><id>RECONFIG_LOOP_TESTS_ENABLE</id></attribute>
+ <attribute><id>ISTEP_PAUSE_ENABLE</id></attribute>
+ <attribute><id>ISTEP_PAUSE_CONFIG</id></attribute>
+ <attribute><id>CDM_POLICIES</id></attribute>
+ <attribute><id>NOMINAL_FREQ_MHZ</id></attribute>
+ <attribute><id>MNFG_FLAGS</id></attribute>
+ <attribute><id>FABRIC_TO_PHYSICAL_NODE_MAP</id></attribute>
+ <attribute><id>MFG_TRACE_ENABLE</id></attribute>
+
</targetType>
<!-- enc-node-power9 -->
diff --git a/src/usr/targeting/common/xmltohb/target_types_hb.xml b/src/usr/targeting/common/xmltohb/target_types_hb.xml
index eb69105df..c8bd5f801 100644..100755
--- a/src/usr/targeting/common/xmltohb/target_types_hb.xml
+++ b/src/usr/targeting/common/xmltohb/target_types_hb.xml
@@ -41,6 +41,203 @@
</targetTypeExtension>
<targetTypeExtension>
+ <id>sys-sys-power9</id>
+ <attribute><id>IS_MPIPL_HB</id></attribute>
+ <attribute><id>IBSCOM_ENABLE_OVERRIDE</id></attribute>
+ <attribute><id>HB_MUTEX_TEST_LOCK</id></attribute>
+ <attribute><id>HB_EXISTING_IMAGE</id></attribute>
+ <attribute><id>ADC_CHANNEL_FUNC_IDS</id></attribute>
+ <attribute><id>ADC_CHANNEL_SENSOR_NUMBERS</id></attribute>
+ <attribute><id>ADC_CHANNEL_GNDS</id></attribute>
+ <attribute><id>ADC_CHANNEL_GAINS</id></attribute>
+ <attribute><id>ADC_CHANNEL_OFFSETS</id></attribute>
+ <attribute><id>APSS_GPIO_PORT_MODES</id></attribute>
+ <attribute><id>APSS_GPIO_PORT_PINS</id></attribute>
+ <attribute><id>OPEN_POWER_DIMM_THROTTLE_TEMP_DEG_C</id></attribute>
+ <attribute><id>OPEN_POWER_DIMM_ERROR_TEMP_DEG_C</id></attribute>
+ <attribute><id>OPEN_POWER_MEMCTRL_THROTTLE_TEMP_DEG_C</id></attribute>
+ <attribute><id>OPEN_POWER_PROC_DVFS_TEMP_DEG_C</id></attribute>
+ <attribute><id>OPEN_POWER_MEMCTRL_ERROR_TEMP_DEG_C</id></attribute>
+ <attribute><id>OPEN_POWER_N_BULK_POWER_LIMIT_WATTS</id></attribute>
+ <attribute><id>OPEN_POWER_N_MAX_MEM_POWER_WATTS</id></attribute>
+ <attribute><id>OPEN_POWER_MEMCTRL_READ_TIMEOUT_SEC</id></attribute>
+ <attribute><id>OPEN_POWER_DIMM_READ_TIMEOUT_SEC</id></attribute>
+ <attribute><id>OPEN_POWER_PROC_ERROR_TEMP_DEG_C</id></attribute>
+ <attribute><id>OPEN_POWER_MIN_MEM_UTILIZATION_THROTTLING</id></attribute>
+ <attribute><id>OPEN_POWER_PROC_READ_TIMEOUT_SEC</id></attribute>
+ <attribute><id>OPEN_POWER_REGULATOR_EFFICIENCY_FACTOR</id></attribute>
+ <attribute><id>OPEN_POWER_MIN_POWER_CAP_WATTS</id></attribute>
+ <attribute><id>OPEN_POWER_N_PLUS_ONE_BULK_POWER_LIMIT_WATTS</id></attribute>
+ <attribute><id>OPEN_POWER_N_PLUS_ONE_MAX_MEM_POWER_WATTS</id></attribute>
+ <attribute><id>OPEN_POWER_TURBO_MODE_SUPPORTED</id></attribute>
+ <attribute><id>OCC_CONTROL_DATA</id></attribute>
+ <attribute><id>OPAL_MODEL</id></attribute>
+ <attribute><id>HTMGT_SAFEMODE</id></attribute>
+ <attribute><id>IPMI_SENSORS</id></attribute>
+ <attribute><id>IPMI_MAX_BUFFER_SIZE</id></attribute>
+</targetTypeExtension>
+
+<targetTypeExtension>
+ <id>enc-node-power9</id>
+ <attribute><id>IPMI_SENSORS</id></attribute>
+ <attribute><id>PART_NUMBER</id></attribute>
+ <attribute><id>SERIAL_NUMBER</id></attribute>
+</targetTypeExtension>
+
+<targetTypeExtension>
+ <id>chip-processor</id>
+ <attribute>
+ <id>FSI_MASTER_MUTEX</id>
+ </attribute>
+ <attribute>
+ <id>FSI_SCOM_MUTEX</id>
+ </attribute>
+ <attribute>
+ <id>SCOM_IND_MUTEX</id>
+ </attribute>
+ <attribute><id>SCAN_MUTEX</id></attribute>
+ <attribute>
+ <id>SLW_IMAGE_ADDR</id>
+ </attribute>
+ <attribute>
+ <id>SLW_IMAGE_SIZE</id>
+ </attribute>
+ <attribute>
+ <id>HOMER_PHYS_ADDR</id>
+ </attribute>
+ <attribute>
+ <id>HOMER_VIRT_ADDR</id>
+ </attribute>
+ <attribute>
+ <id>VPD_SWITCHES</id>
+ </attribute>
+ <attribute>
+ <id>SERIAL_NUMBER</id>
+ </attribute>
+ <attribute>
+ <id>PART_NUMBER</id>
+ </attribute>
+</targetTypeExtension>
+
+<targetTypeExtension>
+ <id>chip-processor-power9</id>
+ <attribute>
+ <id>I2C_ENGINE_MUTEX_0</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>I2C_ENGINE_MUTEX_1</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>I2C_ENGINE_MUTEX_2</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>XSCOM_VIRTUAL_ADDR</id>
+ </attribute>
+ <attribute><id>IPMI_SENSORS</id></attribute>
+ <attribute><id>HB_TARGET_SCOMABLE</id></attribute>
+</targetTypeExtension>
+
+<!-- Centaur chip/DMI -->
+
+<targetTypeExtension>
+ <id>chip-membuf-centaur</id>
+ <attribute>
+ <id>FSI_SCOM_MUTEX</id>
+ </attribute>
+ <attribute>
+ <id>SCOM_IND_MUTEX</id>
+ </attribute>
+ <attribute><id>SCAN_MUTEX</id></attribute>
+ <attribute>
+ <id>IBSCOM_VIRTUAL_ADDR</id>
+ </attribute>
+ <attribute>
+ <id>IBSCOM_MUTEX</id>
+ </attribute>
+ <attribute>
+ <id>I2C_ENGINE_MUTEX_0</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>I2C_ENGINE_MUTEX_1</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>GPIO_INFO</id>
+ </attribute>
+ <attribute><id>VPD_SWITCHES</id></attribute>
+ <attribute>
+ <id>ISDIMM_MBVPD_INDEX</id>
+ </attribute>
+ <attribute><id>IPMI_SENSORS</id></attribute>
+ <attribute><id>PART_NUMBER</id></attribute>
+ <attribute><id>SERIAL_NUMBER</id></attribute>
+</targetTypeExtension>
+
+<targetTypeExtension>
+ <id>unit-core-power9</id>
+ <attribute><id>IPMI_SENSORS</id></attribute>
+ <attribute><id>HB_TARGET_SCOMABLE</id></attribute>
+</targetTypeExtension>
+
+<targetTypeExtension>
+ <id>unit-ex-power9</id>
+ <attribute>
+ <id>HB_PM_SPWUP_OHA_FLAG</id>
+ </attribute>
+ <attribute><id>HB_TARGET_SCOMABLE</id></attribute>
+</targetTypeExtension>
+
+<targetTypeExtension>
+ <id>enc-node-power9</id>
+ <attribute><id>VPD_SWITCHES</id></attribute>
+</targetTypeExtension>
+
+<targetTypeExtension>
+ <id>lcard-dimm</id>
+ <attribute><id>VPD_SWITCHES</id></attribute>
+ <attribute><id>IPMI_SENSORS</id></attribute>
+ <attribute><id>PART_NUMBER</id></attribute>
+ <attribute><id>SERIAL_NUMBER</id></attribute>
+</targetTypeExtension>
+
+<targetTypeExtension>
+ <id>occ</id>
+ <attribute>
+ <id>PSTATE_TABLE</id>
+ </attribute>
+ <attribute><id>IPMI_SENSORS</id></attribute>
+</targetTypeExtension>
+
+<targetTypeExtension>
+ <id>unit-mba-power8</id>
+ <attribute><id>OT_MIN_N_PER_MBA</id></attribute>
+ <attribute><id>N_PLUS_ONE_N_PER_MBA</id></attribute>
+ <attribute><id>N_PLUS_ONE_N_PER_CHIP</id></attribute>
+ <attribute><id>OVERSUB_N_PER_MBA</id></attribute>
+ <attribute><id>OVERSUB_N_PER_CHIP</id></attribute>
+ <attribute><id>HB_TARGET_SCOMABLE</id></attribute>
+</targetTypeExtension>
+
+<targetTypeExtension>
+ <id>unit-mcs-nimbus</id>
+ <attribute><id>HB_TARGET_SCOMABLE</id></attribute>
+</targetTypeExtension>
+
+<targetType>
+ <id>unit-xbus-nimbus</id>
+ <attribute><id>HB_TARGET_SCOMABLE</id></attribute>
+</targetType>
+
+<targetType>
+ <id>unit-abus-power8</id>
+ <attribute><id>HB_TARGET_SCOMABLE</id></attribute>
+</targetType>
+
+<targetTypeExtension>
<id>sys-sys-power8</id>
<attribute><id>IS_MPIPL_HB</id></attribute>
<attribute><id>IBSCOM_ENABLE_OVERRIDE</id></attribute>
@@ -254,9 +451,5 @@
<attribute><id>HB_TARGET_SCOMABLE</id></attribute>
</targetType>
-<targetType>
- <id>unit-abus-power8</id>
- <attribute><id>HB_TARGET_SCOMABLE</id></attribute>
-</targetType>
</attributes>
diff --git a/src/usr/targeting/common/xmltohb/vbu_NAPLES.mrw.xml b/src/usr/targeting/common/xmltohb/vbu_NAPLES.mrw.xml
index 02b576858..35769bc38 100644..100755
--- a/src/usr/targeting/common/xmltohb/vbu_NAPLES.mrw.xml
+++ b/src/usr/targeting/common/xmltohb/vbu_NAPLES.mrw.xml
@@ -1,11 +1,13 @@
<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
-<!-- $Source: src/usr/targeting/common/xmltohb/vbu_MURANO.mrw.xml $ -->
+<!-- $Source: src/usr/targeting/common/xmltohb/vbu_NAPLES.mrw.xml $ -->
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
-<!-- COPYRIGHT International Business Machines Corp. 2012,2014 -->
+<!-- Contributors Listed Below - COPYRIGHT 2014,2015 -->
+<!-- [+] International Business Machines Corp. -->
+<!-- -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
diff --git a/src/usr/targeting/common/xmltohb/xmltohb.pl b/src/usr/targeting/common/xmltohb/xmltohb.pl
index 53032d632..709271bc0 100755
--- a/src/usr/targeting/common/xmltohb/xmltohb.pl
+++ b/src/usr/targeting/common/xmltohb/xmltohb.pl
@@ -5111,6 +5111,12 @@ sub generateTargetingImage {
$targetNodeInstance = $targetInstance;
next;
}
+ elsif(($targetInstance->{type} eq "enc-node-power9") && ($targetNodeCnt == 0))
+ {
+ $targetNodeCnt = 1;
+ $targetNodeInstance = $targetInstance;
+ next;
+ }
push(@targetsAoH, $targetInstance);
}
unshift(@targetsAoH, $targetSystemInstance);
diff --git a/src/usr/targeting/targetservicestart.C b/src/usr/targeting/targetservicestart.C
index 203468510..d51fa3dfc 100644..100755
--- a/src/usr/targeting/targetservicestart.C
+++ b/src/usr/targeting/targetservicestart.C
@@ -241,6 +241,7 @@ static void initializeAttributes(TargetService& i_targetService)
l_pMasterProcChip->setAttr<ATTR_I2C_SWITCHES>(l_i2c_switches);
+#if 0 //@fixme RTC 127337
errlHndl_t l_errl = NULL;
size_t l_size = sizeof(uint64_t);
uint64_t l_data;
@@ -266,6 +267,7 @@ static void initializeAttributes(TargetService& i_targetService)
l_isMpipl = true;
}
}
+#endif //@fixme RTC 127337
}
diff --git a/src/usr/xscom/piberror.C b/src/usr/xscom/piberror.C
index 5208604df..abcc4b24a 100644
--- a/src/usr/xscom/piberror.C
+++ b/src/usr/xscom/piberror.C
@@ -5,7 +5,9 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* COPYRIGHT International Business Machines Corp. 2013,2014 */
+/* Contributors Listed Below - COPYRIGHT 2013,2015 */
+/* [+] International Business Machines Corp. */
+/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
@@ -46,6 +48,9 @@ void addFruCallouts(TARGETING::Target* i_target,
uint64_t i_scomAddr,
errlHndl_t& io_errl)
{
+ // @todo RTC:137627 - Remove for p9 bringup
+ return;
+
switch (i_pibErrStatus)
{
case PIB::PIB_CHIPLET_OFFLINE: //b010
diff --git a/src/usr/xscom/xscom.C b/src/usr/xscom/xscom.C
index 3291ce476..a3d8e28dc 100644
--- a/src/usr/xscom/xscom.C
+++ b/src/usr/xscom/xscom.C
@@ -592,6 +592,9 @@ uint64_t* getCpuIdVirtualAddress()
void resetScomEngine(TARGETING::Target* i_target,
uint64_t* i_virtAddr)
{
+ // @todo-RTC:128077 XSCOM support for P9
+ return;
+
errlHndl_t l_err = NULL;
HMER l_hmer;
uint64_t io_buffer = 0;
diff --git a/src/usr/xscom/xscom.H b/src/usr/xscom/xscom.H
index df49b1ac0..0cd7e60a8 100644
--- a/src/usr/xscom/xscom.H
+++ b/src/usr/xscom/xscom.H
@@ -41,7 +41,7 @@
* @brief The (fixed) base address value for master proc
*/
// @todo-RTC:128077 XSCOM support for P9
-#define MASTER_PROC_XSCOM_BASE_ADDR 0x0006010000000000
+#define MASTER_PROC_XSCOM_BASE_ADDR 0x000603FC00000000
/**
* @brief Type definition for XSCom address and Chip ID
@@ -196,13 +196,12 @@ class XSComP8Address
uint64_t mMmioAddress; // mMmio address
struct
{
- uint64_t mReserved1:18; // Not currently used (0:17)
- uint64_t mBaseAddress:5; // Base address (18:22)
- uint64_t mNodeId:3; // Node where target resides (23:25)
- uint64_t mChipId:3; // Targeted chip ID (26:28)
- uint64_t mSComAddrHi:27; // PCB Address High (29:55)
- uint64_t mCacheLine:1; // Cached line (56)
- uint64_t mSComAddrLo:4; // PCB Address low (57:60)
+ uint64_t mReserved1:8; // Not currently used (0:7)
+ uint64_t mBaseAddrHi:7; // Base address [8:14] (8:14)
+ uint64_t mNodeId:4; // Node where target resides (15:18)
+ uint64_t mChipId:3; // Targeted chip ID (19:21)
+ uint64_t mBaseAddrLo:8; // Base address [22:29] (22:29)
+ uint64_t mSComAddr:31; // PIB Address (30:60)
uint64_t mAlign:3; // Align (61:63)
} mAddressParts;
};
@@ -221,8 +220,7 @@ XSComP8Address::XSComP8Address(const XSComAddress_t i_addr)
// Relative address of Node 0, chip 0
// The chip's nodeId and chip id will be taken into account
// when calculating its XSCOM base address
- mAddressParts.mSComAddrHi = i_addr >> 4; // Get 27-bits
- mAddressParts.mSComAddrLo = i_addr; // Get 4 bits
+ mAddressParts.mSComAddr = i_addr;
}
////////////////////////////////////////////////////////////////////////////
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