SW275629: Steering failing intermittently due to spare DRAM spec violation

Change-Id: Ieb1523b1200ba0c1750d7bf3ad9d34d985e4d02a
CQ:SW275629
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13722
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: STEPHEN M. CPREK <smcprek@us.ibm.com>
Tested-by: STEPHEN M. CPREK <smcprek@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13751
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

3 files changed, 23 insertions, 22 deletions

diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
index 12217baae..350efb763 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_mc.C,v 1.46 2014/04/07 19:02:27 gollub Exp $
+// $Id: mss_draminit_mc.C,v 1.47 2014/09/24 14:48:18 dcadiga Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -46,6 +46,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.47   | dcadiga  |09-SEP-14| Removed SPARE cke disable step
 //  1.46   | gollub   |07-APR-14| Removed call to mss_unmask_inband_errors (moved it to proc_cen_framelock)
 //  1.45   | dcadiga  |14-FEB-14| Periodic Cal Fix for DD2
 //  1.44   | bellows  |12-FEB-14| Workaround for ENABLE_RCE_WITH_OTHER_ERRORS_HW246685
@@ -165,18 +166,19 @@ ReturnCode mss_draminit_mc_cloned(Target& i_target)
 
 
 
-    // Step Zero: Turn Off Spare CKE - This needs to be off before IML complete
-    FAPI_INF("+++ Disabling Spare CKE FIX +++");
-    for (uint32_t i=0; i < l_mbaChiplets.size(); i++)
-    {
-       rc = mss_spare_cke_disable(l_mbaChiplets[i]);
-       if(rc)
-       {
-          FAPI_ERR("---Error During Spare CKE Disable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
-          return rc;
-       }
+    // Step Zero: Turn Off Spare CKE - This needs to be off before IML complete 
+    // STEP COMMENTED FOR SW275629
+    FAPI_INF("+++ Disabling Spare CKE FIX DISABLED +++");
+    //for (uint32_t i=0; i < l_mbaChiplets.size(); i++)
+    //{
+    //   rc = mss_spare_cke_disable(l_mbaChiplets[i]);
+    //   if(rc)
+    //   {
+    //      FAPI_ERR("---Error During Spare CKE Disable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
+    //      return rc;
+    //   }
 
-    }
+    //}
 
 
     // Step One: Set IML COMPLETE
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
index 6120657d8..e20806255 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_training.C,v 1.90 2014/07/29 19:35:40 jdsloat Exp $
+// $Id: mss_draminit_training.C,v 1.91 2014/09/24 22:18:24 jdsloat Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -30,6 +30,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|------------------------------------------------
+//  1.91   | jdsloat  |24-SEP-14| Disabling spare CKE bit modify for SW275629.  This bit will be modified via initfile. 
 //  1.90   | jdsloat  |29-JUL-14| disable for delay reset call moved to system level
 //  1.89   | jdsloat  |29-JUL-14| Added a disable for delay reset call 
 //  1.88   | jdsloat  |14-JUL-14| Fixed delay reset call 
@@ -176,8 +177,6 @@
 #include <mss_lrdimm_ddr4_funcs.H>
 #endif
 
-#include <config.h>
-
 #ifndef FAPI_LRDIMM
 using namespace fapi;
 fapi::ReturnCode mss_execute_lrdimm_mb_dram_training(Target& i_target)
@@ -443,6 +442,8 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
     if(rc) return rc;
     rc_num = rc_num | cal_steps_8.insert(cal_steps, 0, 8, 0);
 
+    /*
+    Disabling spare CKE bit modify for SW275629.  This bit will be modified via initfile. 
 
     //Setup SPARE CKE enable bit
     rc = fapiGetScom(i_target, MBA01_MBARPC0Q_0x03010434, data_buffer_64);
@@ -450,6 +451,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
     rc_num = rc_num | data_buffer_64.setBit(42);
     rc = fapiPutScom(i_target, MBA01_MBARPC0Q_0x03010434, data_buffer_64);
     if(rc) return rc;
+    */
 
     //Set up CCS Mode Reg for Init cal
     rc = fapiGetScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64);
@@ -491,8 +493,6 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
 	    rc = mss_execute_zq_cal(i_target, port);
 	    if(rc) return rc;
 
-
-#ifndef CONFIG_VPD_GETMACRO_USE_EFF_ATTR
             // Should only be called for DDR4 LRDIMMs, training code is in development. Does not effect any other configs
 	    if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) &&
                  (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) )
@@ -502,8 +502,6 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
 		 rc = mss_mxd_training(i_target,port,0);
 		 if(rc) return rc;
             }
-#endif
-
 	}
 
         if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) && 
@@ -734,7 +732,6 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
 			       if(rc) return rc;
                             }
 			}
-#ifndef CONFIG_VPD_GETMACRO_USE_EFF_ATTR
                         // Should only be called for DDR4 LRDIMMs, training code is in development. Does not effect any other configs
                         else if ( (group == 0) && (cur_cal_step == 1)
                                   && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
@@ -743,7 +740,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
                            rc = mss_dram_write_leveling(i_target, port);
                            if(rc) return rc;
                         }
-#endif
+
 		        //Set the config register
 			if(port == 0)
 			{
diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
index 4a66dca3a..88aafb9e2 100644
--- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile
+++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
@@ -1,9 +1,10 @@
 
-#-- $Id: mba_def.initfile,v 1.68 2014/04/04 16:46:15 jdsloat Exp $
+#-- $Id: mba_def.initfile,v 1.69 2014/09/24 14:44:15 asaetow Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.69|asaetow | 9/24/14| Force SpareCKE sync. Spare DRAM workaround.
 #--     1.68|jdsloat | 4/04/14| Turned off Power controls for GA1 concerns - Turn back on at a later date
 #--     1.67|tschang | 4/01/14| Adjusted the PUP Avail and SEPD/FEPD time.
 #--     1.66|tschang | 3/28/14| Removed Performance enhancement for rdtag with DMI freq
@@ -2041,6 +2042,7 @@ scom 0x03010434    {
     16:20   ,   0b00110     ,           1            ,   (def_MBARPC0Q_cfg_pup_pdn_dly6 == 1); # MBARPC0Q_cfg_pup_pdn       38
     22      ,   0b0         ,           1            ,   any; # cfg_min_domain_reduction_enable set to 1 to enable power controls
     23:32   ,   0b0000000011,           1            ,   any; # Set min doman reduction time to 30.7 us (10.245us * 3)
+    42      ,   0b1         ,           1            ,   any; # Force SpareCKE sync
     43      ,   0b0         ,           1            ,   any; # Use 1 in 8k 2:1 cycle pulses for min domain reduction time interval
 }