diff options
| author | Dan Crowell <dcrowell@us.ibm.com> | 2012-10-08 14:26:42 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2012-11-07 16:03:23 -0600 |
| commit | d871f70ebe8e9e91d8dd4b604dfee0303461b9aa (patch) | |
| tree | 4e4ee913e7177514f5569df07ff51423a15432e3 /src/usr | |
| parent | 90190a610b3452c34eb1e4848f66ad54d22e6a6f (diff) | |
| download | talos-hostboot-d871f70ebe8e9e91d8dd4b604dfee0303461b9aa.tar.gz talos-hostboot-d871f70ebe8e9e91d8dd4b604dfee0303461b9aa.zip | |
Support for PM Attributes
Adding new HWP attribute xml files and associated Targeting
changes to go along with them. The MURANO and VENICE xml
files contain default values provided by Greg Still. We
are still waiting on the final MRW definition to update
the TULETA generation script.
Also using this commit to add a few other error xml files
for the HostServices procedures. We need this longterm
to get the error parsing stuff working.
Verified IPL against Murano and Tuleta configs.
Depends-On: I3af3b2bf99b4dbedb6efeb2cb35e49ba066a9c19
Change-Id: I3a5be5a7b49c7c6d7e6179f5e28e046a38a12b1e
RTC: 42293
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2002
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr')
21 files changed, 5249 insertions, 1271 deletions
diff --git a/src/usr/hwpf/hwp/p8_pmc_deconfig_setup_errors.xml b/src/usr/hwpf/hwp/p8_pmc_deconfig_setup_errors.xml new file mode 100644 index 000000000..0b5da9d25 --- /dev/null +++ b/src/usr/hwpf/hwp/p8_pmc_deconfig_setup_errors.xml @@ -0,0 +1,31 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/p8_pmc_deconfig_setup_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- Error definitions for p8_pmc_deconfig_setup procedure --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_PMC_DECONFIG_NO_CORES</rc> + <description>p8_pmc_deconfig_setup did not find any configured core.</description> + </hwpError> + <!-- *********************************************************************** --> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/p8_poregpe_errors.xml b/src/usr/hwpf/hwp/p8_poregpe_errors.xml new file mode 100644 index 000000000..152cc34d9 --- /dev/null +++ b/src/usr/hwpf/hwp/p8_poregpe_errors.xml @@ -0,0 +1,45 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/p8_poregpe_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- Error definitions for proc_poregpe procedure --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_GPE0_RESET_TIMEOUT</rc> + <description>GPE0 reset failed in proc_poregpe_init.</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_GPE1_RESET_TIMEOUT</rc> + <description>GPE1 reset failed in proc_poregpe_init.</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_GPE_CODE_BAD_MODE</rc> + <description>Unknown mode passed to proc_poregpe_init.</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_GPE_BAD_ENGINE</rc> + <description>Unknown engine passed to proc_poregpe_init. </description> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/p8_poreslw_errors.xml b/src/usr/hwpf/hwp/p8_poreslw_errors.xml new file mode 100644 index 000000000..6878351ec --- /dev/null +++ b/src/usr/hwpf/hwp/p8_poreslw_errors.xml @@ -0,0 +1,40 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/p8_poreslw_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- Error definitions for p8_poreslw procedure --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_PORESLW_CODE_BAD_TBA</rc> + <description>Invalid Table Base Address value passed to p8_poreslw_init.</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_SLW_RESET_TIMEOUT</rc> + <description>SLW reset failed in p8_poreslw_init.</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_PORESLW_CODE_BAD_MODE</rc> + <description>Unknown mode passed to p8_poreslw_init.</description> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml b/src/usr/hwpf/hwp/runtime_attributes/pm_attributes_all_hwp.xml index 17ecc890c..87a1ab6c6 100644..100755 --- a/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml +++ b/src/usr/hwpf/hwp/runtime_attributes/pm_attributes_all_hwp.xml @@ -1,7 +1,7 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml $ --> +<!-- $Source: src/usr/hwpf/hwp/runtime_attributes/pm_attributes_all_hwp.xml $ --> <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> @@ -20,778 +20,875 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- - XML file specifying Power Management HWPF attributes. - These attributes are initialized to zero by the platform and set to a - meaningful value by a HWP ---> - -<attributes> -<!-- *********************************************************************** --> - -<attribute> - <id>ATTR_PM_POWER_PROXY_TRACE_TIMER</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>The Power Proxy Trace timer (binary in microseconds) defines the time between Power Proxy Trace records when no other event that would otherwise produce a record has occured. Values must be within a range of 32us to 64ms.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PPT_TIMER_MATCH_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>The delay is 32us * ATTR_PM_PPT_TIMER_MATCH_VALUE</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PPT_TIMER_TICK</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Defines the Power Proxy Trace interval timer tick (0=25us, 1=0.5us, 2=1us, and 3=2us)</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_AISS_TIMEOUT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Defines the timeout value for the Architected Idle State Sequencer (AISS).</description> - <valueType>uint8</valueType> - <enum>1MS=0, 2MS=1, 4MS=2, 8MS=3, 16MS=4, 32MS=5, 64MS=6, 128MS=7, 256MS=8, 512MS=9</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PSTATE_STEPSIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Unsigned 7 bit (baby-) stepsize for Pstate transitions between the Global Pstate Actual and the Global Pstate Target. Only non-zero values are supported for this dial. - -Used to setup the PMC voltage controller - -Producer: proc_build_pstate_tables.C - -Consumer: OCC pstate_init()</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Selects the resolution for the step delay count after a voltage change (decimal value N for this field divides the prv clock by 2^(N+3)) - -A 4 bit field selects one of the the upper 16bit of a 19bit counter (16+3) incremented in the nest/4 domain - -Consumer: proc_pm.scominit</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Step delay after a voltage change in increments of vrm_stepdelay_range. Setting this dial to a value N causes a delay of N cycles of the divided nest clk (see dial vrm_stepdelay_range). The closed formula is as follows: Delay_seconds = vrm_stepdelay_value * ( 2^(3 + vrm_stepdelay_range) / (Nest_frequency_Hz/4)) - -Consumer: proc_pm.scominit</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PMC_HANGPULSE_DIVIDER</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Divides the hang pulse to PMC to achieve XXXX. Note that this needs to be set according to the description of dial pmc_occ_heartbeat_time - -Producer: prc_pm_effective - -Consumer: proc_pm.scominit</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PVSAFE_PSTATE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> -Pstate that is invoked in the PMC voltage controller upon the loss of the OCC Heartbeat.. - -Producer: proc_pm_effective.C - -Consumer: proc_pm.scominit</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_FRAME_SIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number of data bits per individual SPIVID transaction (also referred to as frame) during chip select assertion - -Supported values: 0x20 (32d) - -Chip Select assertion duration is spi_frame_size + 2</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_IN_DELAY_FRAME1</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number of SPIVID clocks after chip select to wait before capturing MISO input in frame 1 - -Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_IN_DELAY_FRAME2</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number of SPI clocks after chip select to wait before capturing MISO input in frame 2 - -Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_CLOCK_POLARITY</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPVID Clock Polarity (CPOL=0 means that clk idle is deasserted, CPOL=1 means that clk idle is asserted)</description> - <valueType>uint8</valueType> - <enum>IDLELOW=0, IDLEHIGH = 1</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_CLOCK_PHASE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPI clock phase (CPHA=0 means to change/sample values of data signals on first edge, otherwise on 2nd)</description> - <valueType>uint8</valueType> - <enum>FIRSTEDGE=0, -SECONDEDGE=1</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_CLOCK_DIVIDER</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPIVID clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1 -For a 2.4GHz nest clock, this means that the SPI clk can be theoretically adjusted between 600MHz and 0.29MHz (cycle time 1.66ns...3.41us, in 1.66ns steps). However, a practical range is 0.5...25MHz.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay between command and status frames of a SPIVID WRITE operation (binary in nanoseconds) -Consumer: proc_pmc_init</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay between two frames of a Write command as measured from the end of the last bit of the first frame until the chip select of the second frame, which contains the status, is asserted. This delay allows for the checking and status data production in the SPIVID chip. - -Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time - -0x00000: Wait 1 SPI Clock -0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses - -For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay between command retry attempts. - -Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time - -0x0000: Wait 1 SPI Clock -0x0001 - 0xFFFF: value = number of ~100ns_hang_pulses - -For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_INTER_RETRY_DELAY</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay between SPIVID reture attempts when WRITE command status indicates an error (binary in nanoseconds) -Consumer: proc_pmc_init</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_CRC_GEN_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>EnableS CRC generation from processor to VRM device. This will produce an 8b CRC per the enabled polynomial. If CRC generation is disabled, the full 32 bits at the data input of the SPI master are transmitted.</description> - <valueType>uint8</valueType> - <enum>TRUE = 1, FALSE = 0</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_CRC_CHECK_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Enables CRC checking in the processor of frames from the VRM device.</description> - <valueType>uint8</valueType> - <enum>TRUE = 1, FALSE = 0</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>enables the a majority vote on the 3B of status payload on a frame received by the master as each of these have a 1 byte status field replicated three (3) times by the slave.</description> - <valueType>uint8</valueType> - <enum>TRUE = 1, FALSE = 0</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_MAX_RETRIES</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number retries upon detected errors. - -0x00: No retry -0x01 to 0x1F: 1 to 31 respectively</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>CRC8 Polynomial Enables - -An 8 bit mask vector to enable XORs in the CRC generation and checking LFSRs at the respective bit position. MSB (x^8) is omitted since it is always enabled, so the mask layout is (x^7,x^6,x^5,x^4,x^3,x^2,x^1,1) - -Planned CRC8 polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 -Value to enable planned polynomial: 0b1101_0101 (=0xD5)</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_OCC_HEARTBEAT_TIME</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Time within which the OCC firmware must access the PMC or the OCC will be considered faulty whereby FIRs and malfunction alerts will be produced . (binary in nanoseconds) -Consumer: OCC FW</description> - <valueType>uint32</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_SLEEP_WINKLE_REQUEST_TIMEOUT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Time (binary in ns) that will be the threshold value for the PMC PORE request timeout. - -Consumer: proc_pmc_init.C. Will be translated to a DYNAMIC ATTRIBUTE for use by proc_pm..scominit as a multiple of PM hang pulses.. Counter starts at 0, is increased with every tp_pmc_hang_pulse as long as PORE is busy and set the PMC local FIR bit 19 when count = threshold.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SLEEP_ENTRY</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Setting depends on di/dt charateristics of the system. - -Set Assisted if power off serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency - -Producer: MRWB - -Consumer: proc_pm_effective and proc_pcbs_init</description> - <valueType>uint8</valueType> - <enum>HARDWARE=0, ASSISTED=1</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SLEEP_EXIT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Setting depends on di/dt charateristics of the system and the setting of ATTR_PM_SLEEP_TYPE. - -Set to Assisted if power on serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency -Must be set to Assisted if ATTR_PM_SLEEP_TYPE=Deep as this necessary for restore. - -Setting to Hardware is a test mode for Fast only. - -Producer: MRWB - -Consumer: proc_pm_effective and proc_pcbs_init.</description> - <valueType>uint8</valueType> - <enum>HARDWARE=0, ASSISTED=1</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SLEEP_TYPE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Sleep Power Off Select: -Selects which voltage level to place the Core domain PFETs upon Sleep entry. 0 = Vret (Fast Sleep Mode), 1 = Voff (Deep Sleep Mode) - -Producer: MRWB - -Consumer: proc_pm_effective and proc_pcbs_init</description> - <valueType>uint8</valueType> - <enum>FAST=0, DEEP=1</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_WINKLE_TYPE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Winkle Power Off Select: -Selects which voltage level to place the Core and ECO domain PFETs upon Winkle entry. 0 = Vret (Fast Winkle Mode), 1 = Voff (Deep Winkle Mode)</description> - <valueType>uint8</valueType> - <enum>FAST=0, DEEP=1</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_CORE_DELAY0</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) after a step in the Core power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_CORE_DELAY1</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) after a step in the Core power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 0 between any step in the Core power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 1 between any step in the Core power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the sequence. Power up goes from 11, then 10, then 9,.... then 0. - -0 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY0; - -1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY0</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) between a step in the Core power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY1</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) between a step in the Core power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 0 between any step in the Core power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 1 between any step in the Core power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the sequence. Power up goes from 11, then 10, then 9,.... then 0. - -0 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY0; - -1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_ECO_DELAY0</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) after a step in the ECO power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_ECO_DELAY1</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) after a step in the ECO power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 0 between any step in the ECO power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 1 between any step in the ECO power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the sequence. Power up goes from 11, then 10, then 9,.... then 0. - -0 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY0; - -1 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY1</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY0</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) between a step in the ECO power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY1</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) between a step in the ECO power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 0 between any step in the ECO power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 1 between any step in the ECO power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the ECO power up sequence. Power up goes from 11, then 10, then 9,.... then 0. 0 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY0; 1 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY1</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PSTATE0_FREQUENCY</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Defines the center point of the Pstate space in the frequency domain. Binary in Khz. - -Producer: proc_build_gpstate.C - -Consumers: proc_pcbs_init.C, proc_pcbs_lpst_init.C, </description> - <valueType>uint32</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_IVRMS_ENABLED</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Indicates whether available internal voltage regulation macros (iVRMs) are to enabled. This indicates that module VPD has valid #M keywords available.</description> - <valueType>uint8</valueType> - <enum>TRUE = 1, FALSE = 0</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SAFE_PSTATE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Safe Pstate - -Valid Values:-128 thru 127 - -Producer: proc_pm_effective.C - -DYNAMIC_ATTRIBUTE - -Consumer: proc_pcbs_init.C - -Establishes the Pstate that the core chiplet will take on if: -psafe less-than-or-equal PMSR[global_actual_pstate] -AND any of the following conditions are true: -Loss of OCC Heartbeat if occ_heartbeat_en is set -PMGP0[force_safe_mode] is set - -If psafe greater-than PMSR[global_actual_pstate], the global_actual_pstate is forced. - -The value of Psafe needs to be at or below the nominal Pstate to make sure safe operation of all chiplets.</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_RESONANT_CLOCK_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Resonant Clock Enable</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_RESONANT_CLOCK_FULL_CSB_PSTATE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>FCSB Full Clock Sector Buffer (8b in terms of Pstate) -Defines the Pstate for the point at which clock sector buffers should be at full strength. This is to support Vmin operation. -</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_RESONANT_CLOCK_LFRLOW_PSTATE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>LFRLower Low Frequency Resonant Lower. Defines the Pstate for the lower end of the Low Frequency Resonant band</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_RESONANT_CLOCK_LFRUPPER_PSTATE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>LFRUpper Low Frequency Resonant Upper. Defines the Pstate for the upper end of the Low Frequency Resonant band</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_RESONANT_CLOCK_HFRLOW_PSTATE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>HFRLower High Frequency Resonant Low. Defines the Pstate for the lower end of the High Frequency Resonant band</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_RESONANT_CLOCK_HFRHIGH_PSTATE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>HFRUpper High Frequency Resonant Upper. Defines the Pstate for the upper end of the High Frequency Resonant band</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_FRAME_SIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number of data bits per individual SPIPSS transaction (also referred to as frame) during chip select assertion - -Supported values: 0x10 (16d), - -Chip Select assertion duration is spi_frame_size + 2</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_OUT_COUNT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number of bits sent out MOSI of the frame - -Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size are ignored.</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_IN_DELAY</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number of SPI clocks after chip select to wait before capturing MISO input - -Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_IN_COUNT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number of bits captured on MISO input - -Supported values: 0x000 to spi_frame_size. The actual number of bits captured is spi_frame_size - spi_in_delay</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_CLOCK_POLARITY</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPIPSS Clock Polarity (CPOL=0 means that clk idle is deasserted, CPOH=1 means that clk idle is asserted)</description> - <valueType>uint8</valueType> - <enum>CPOL=0, CPOH=1</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_CLOCK_PHASE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPIPSS clock phase (CPHA=0 means to change/sample values of data signals on first edge, otherwise on 2nd)</description> - <valueType>uint8</valueType> - <enum>FIRSTEDGE=0, SECONDEDGE=1</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_CLOCK_DIVIDER</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPI clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> -Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time - -0x00000: Wait 1 PSS Clock -0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses - -For values greater than 0x00000, the actual delay is 1 PSS Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 PSSI clock cycle. - -Producer: proc_pm_effective - -Consumer: proc_pss_init</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_INTER_FRAME_DELAY</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay between two frames of a P2S command as measured from the end of the last bit of the first frame until the chip select of the second frame. (binary in nanoseconds) - -Consumer: proc_pm_effective - -Produces ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PBAX_RCV_RESERV_TIMEOUT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>PBAX Data Timeout Divider -Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang pulses are received under the following conditions: - Data Hi packet accepted and timeout waiting for Data Lo packet. - Reservation aquired and timeout waiting for Data Hi packet. - -00000 Data Timeout is Disabled -00001 divided hang pulse = PBAX hang pulse -00010 divided hang pulse = PBAX hang pulse/2 -00011 divided hang pulse = PBAX hang pulse/3 -. . . -11111 divided hang pulse = PBAX hang pulse/31</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>PBAX Send Retry count overcommit -Mode bit to count overcommit retries for the send retry threshold when sending PBAX commands on the powerbus.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PBAX_SND_RETRY_THRESHOLD</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>PBAX Send Retry Threshold -Defines the maximum number of retry attempts by the Send Engine for any phase of the PBAX transaction set before the operation is dropped and status bit are set. This does not count PowerBus overcommit retries unless snd_retry_count_overcom bit is set. - -0x00 : No Timeout -0x01 : 1 attempt -0x02 : 2 attempts -.etc. -0xFF : 255 attempts</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PBAX_SND_RESERV_TIMEOUT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>PBAX Send Reservation Timeout Divider -Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang pulses are received after attempting to acquire a reservation with the PBAX Receive engine before declaring a Send Reservation Timeout error. - -00000 Send Reservation Timeout is Disabled -00001 divided hang pulse = PBAX hang pulse -00010 divided hang pulse = PBAX hang pulse/2 -00011 divided hang pulse = PBAX hang pulse/3 -. . . -11111 divided hang pulse = PBAX hang pulse/31</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_SPWUP_FSP</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Arbitration Attribute for FSP special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPWUP_OCC</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Arbitration Attribute for OCC special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPWUP_PHYP</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Arbitration Attribute for PHUP special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -</attributes> - +<!--
+ XML file specifying Power Management HWPF attributes.
+ These attributes are initialized to zero by the platform and set to a
+ meaningful value by a HWP
+-->
+<attributes>
+<!-- *********************************************************************** -->
+
+<attribute>
+ <id>ATTR_PM_POWER_PROXY_TRACE_TIMER</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+The Power Proxy Trace timer (binary in microseconds) defines the time between Power Proxy Trace records when no other event that would otherwise produce a record has occured. Values must be within a range of 32us to 64ms.
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PPT_TIMER_MATCH_VALUE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+The delay is 32us * ATTR_PM_PPT_TIMER_MATCH_VALUE
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PPT_TIMER_TICK</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Defines the Power Proxy Trace interval timer tick (0=25us, 1=0.5us, 2=1us, and 3=2us)
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_AISS_TIMEOUT</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Defines the timeout value for the Architected Idle State Sequencer (AISS).
+ </description>
+ <valueType>uint8</valueType>
+ <enum>1MS=0, 2MS=1, 4MS=2, 8MS=3, 16MS=4, 32MS=5, 64MS=6, 128MS=7, 256MS=8, 512MS=9</enum>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PSTATE_STEPSIZE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Unsigned 7 bit (baby-) stepsize for Pstate transitions between the Global Pstate Actual and the Global Pstate Target. Only non-zero values are supported for this dial.
+
+Used to setup the PMC voltage controller
+
+Producer: proc_build_pstate_tables.C
+
+Consumer: OCC pstate_init()
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Selects the resolution for the step delay count after a voltage change (decimal value N for this field divides the prv clock by 2^(N+3))
+
+A 4 bit field selects one of the the upper 16bit of a 19bit counter (16+3) incremented in the nest/4 domain
+
+Consumer: proc_pm.scominit
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Step delay after a voltage change in increments of vrm_stepdelay_range. Setting this dial to a value N causes a delay of N cycles of the divided nest clk (see dial vrm_stepdelay_range). The closed formula is as follows: Delay_seconds = vrm_stepdelay_value * ( 2^(3 + vrm_stepdelay_range) / (Nest_frequency_Hz/4))
+
+Consumer: proc_pm.scominit
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PMC_HANGPULSE_DIVIDER</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Divides the hang pulse to PMC to achieve XXXX. Note that this needs to be set according to the description of dial pmc_occ_heartbeat_time
+
+Producer: prc_pm_effective
+
+Consumer: proc_pm.scominit
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PVSAFE_PSTATE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+
+Pstate that is invoked in the PMC voltage controller upon the loss of the OCC Heartbeat..
+
+Producer: proc_pm_effective.C
+
+Consumer: proc_pm.scominit
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIVID_FRAME_SIZE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Number of data bits per individual SPIVID transaction (also referred to as frame) during chip select assertion
+
+Supported values: 0x20 (32d)
+
+Chip Select assertion duration is spi_frame_size + 2
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIVID_IN_DELAY_FRAME1</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Number of SPIVID clocks after chip select to wait before capturing MISO input in frame 1
+
+Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIVID_IN_DELAY_FRAME2</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Number of SPI clocks after chip select to wait before capturing MISO input in frame 2
+
+Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIVID_CLOCK_POLARITY</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+SPVID Clock Polarity (CPOL=0 means that clk idle is deasserted, CPOL=1 means that clk idle is asserted)
+ </description>
+ <valueType>uint8</valueType>
+ <enum>IDLELOW=0, IDLEHIGH = 1</enum>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIVID_CLOCK_PHASE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+SPI clock phase (CPHA=0 means to change/sample values of data signals on first edge, otherwise on 2nd)
+ </description>
+ <valueType>uint8</valueType>
+ <enum>FIRSTEDGE=0,
+SECONDEDGE=1</enum>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIVID_CLOCK_DIVIDER</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+SPIVID clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1
+For a 2.4GHz nest clock, this means that the SPI clk can be theoretically adjusted between 600MHz and 0.29MHz (cycle time 1.66ns...3.41us, in 1.66ns steps). However, a practical range is 0.5...25MHz.
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay between command and status frames of a SPIVID 'WRITE' operation (binary in nanoseconds)
+Consumer: proc_pmc_init
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay between two frames of a Write command as measured from the end of the last bit of the first frame until the chip select of the second frame, which contains the status, is asserted. This delay allows for the checking and status data production in the SPIVID chip.
+
+Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time
+
+0x00000: Wait 1 SPI Clock
+0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses
+
+For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle.
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay between command retry attempts.
+
+Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time
+
+0x0000: Wait 1 SPI Clock
+0x0001 - 0xFFFF: value = number of ~100ns_hang_pulses
+
+For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle.
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIVID_INTER_RETRY_DELAY</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay between SPIVID reture attempts when WRITE command status indicates an error (binary in nanoseconds)
+Consumer: proc_pmc_init
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIVID_CRC_GEN_ENABLE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+EnableS CRC generation from processor to VRM device. This will produce an 8b CRC per the enabled polynomial. If CRC generation is disabled, the full 32 bits at the data input of the SPI master are transmitted.
+ </description>
+ <valueType>uint8</valueType>
+ <enum>TRUE = 1, FALSE = 0</enum>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIVID_CRC_CHECK_ENABLE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Enables CRC checking in the processor of frames from the VRM device.
+ </description>
+ <valueType>uint8</valueType>
+ <enum>TRUE = 1, FALSE = 0</enum>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+enables the a majority vote on the 3B of status payload on a frame received by the master as each of these have a 1 byte status field replicated three (3) times by the slave.
+ </description>
+ <valueType>uint8</valueType>
+ <enum>TRUE = 1, FALSE = 0</enum>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIVID_MAX_RETRIES</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Number retries upon detected errors.
+
+0x00: No retry
+0x01 to 0x1F: 1 to 31 respectively
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+CRC8 Polynomial Enables
+
+An 8 bit mask vector to enable XORs in the CRC generation and checking LFSRs at the respective bit position. MSB (x^8) is omitted since it is always enabled, so the mask layout is (x^7,x^6,x^5,x^4,x^3,x^2,x^1,1)
+
+Planned CRC8 polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1
+Value to enable planned polynomial: 0b1101_0101 (=0xD5)
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_OCC_HEARTBEAT_TIME</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Time within which the OCC firmware must access the PMC or the OCC will be considered faulty whereby FIRs and malfunction alerts will be produced . (binary in nanoseconds)
+Consumer: OCC FW
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SLEEP_WINKLE_REQUEST_TIMEOUT</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Time (binary in ns) that will be the threshold value for the PMC PORE request timeout.
+
+Consumer: proc_pmc_init.C. Will be translated to a DYNAMIC ATTRIBUTE for use by proc_pm..scominit as a multiple of PM hang pulses.. Counter starts at 0, is increased with every tp_pmc_hang_pulse as long as PORE is busy and set the PMC local FIR bit 19 when count = threshold.
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERUP_CORE_DELAY0</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay (binary in nanoseconds) after a step in the Core power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERUP_CORE_DELAY1</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay (binary in nanoseconds) after a step in the Core power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay value 0 between any step in the Core power-up PFET sequence.
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay value 1 between any step in the Core power-up PFET sequence.
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the sequence. Power up goes from 11, then 10, then 9,.... then 0.
+
+0 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY0;
+
+1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY0</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay (binary in nanoseconds) between a step in the Core power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY1</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay (binary in nanoseconds) between a step in the Core power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay value 0 between any step in the Core power-up PFET sequence.
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay value 1 between any step in the Core power-up PFET sequence.
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the sequence. Power up goes from 11, then 10, then 9,.... then 0.
+
+0 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY0;
+
+1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERUP_ECO_DELAY0</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay (binary in nanoseconds) after a step in the ECO power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERUP_ECO_DELAY1</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay (binary in nanoseconds) after a step in the ECO power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay value 0 between any step in the ECO power-up PFET sequence.
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay value 1 between any step in the ECO power-up PFET sequence.
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the sequence. Power up goes from 11, then 10, then 9,.... then 0.
+
+0 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY0;
+
+1 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY1
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY0</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay (binary in nanoseconds) between a step in the ECO power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY1</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay (binary in nanoseconds) between a step in the ECO power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay value 0 between any step in the ECO power-up PFET sequence.
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay value 1 between any step in the ECO power-up PFET sequence.
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the ECO power up sequence. Power up goes from 11, then 10, then 9,.... then 0. 0 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY0; 1 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY1
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PSTATE0_FREQUENCY</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Defines the center point of the Pstate space in the frequency domain. Binary in Khz.
+
+Producer: proc_build_gpstate.C
+
+Consumers: proc_pcbs_init.C, proc_pcbs_lpst_init.C,
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_IVRMS_ENABLED</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Indicates whether available internal voltage regulation macros (iVRMs) are to enabled. This indicates that module VPD has valid #M keywords available.
+ </description>
+ <valueType>uint8</valueType>
+ <enum>TRUE = 1, FALSE = 0</enum>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SAFE_PSTATE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Safe Pstate
+
+Valid Values:-128 thru 127
+
+Producer: proc_pm_effective.C
+
+DYNAMIC_ATTRIBUTE
+
+Consumer: proc_pcbs_init.C
+
+Establishes the Pstate that the core chiplet will take on if:
+psafe less than or equal to PMSR[global_actual_pstate]
+AND any of the following conditions are true:
+Loss of OCC Heartbeat if occ_heartbeat_en is set
+PMGP0[force_safe_mode] is set
+
+If psafe > PMSR[global_actual_pstate], the global_actual_pstate is forced.
+
+The value of Psafe needs to be at or below the nominal Pstate to make sure safe operation of all chiplets.
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_RESONANT_CLOCK_ENABLE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Resonant Clock Enable
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_RESONANT_CLOCK_FULL_CSB_PSTATE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+FCSB = Full Clock Sector Buffer (8b in terms of Pstate)
+Defines the Pstate for the point at which clock sector buffers should be at full strength. This is to support Vmin operation.
+
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_RESONANT_CLOCK_LFRLOW_PSTATE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+LFRLower = Low Frequency Resonant Lower. Defines the Pstate for the lower end of the Low Frequency Resonant band
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_RESONANT_CLOCK_LFRUPPER_PSTATE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+LFRUpper = Low Frequency Resonant Upper. Defines the Pstate for the upper end of the Low Frequency Resonant band
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_RESONANT_CLOCK_HFRLOW_PSTATE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+HFRLower = High Frequency Resonant Low. Defines the Pstate for the lower end of the High Frequency Resonant band
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_RESONANT_CLOCK_HFRHIGH_PSTATE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+HFRUpper = High Frequency Resonant Upper. Defines the Pstate for the upper end of the High Frequency Resonant band
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIPSS_FRAME_SIZE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Number of data bits per individual SPIPSS transaction (also referred to as frame) during chip select assertion
+
+Supported values: 0x10 (16d),
+
+Chip Select assertion duration is spi_frame_size + 2
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIPSS_OUT_COUNT</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Number of bits sent out MOSI of the frame
+
+Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size are ignored.
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIPSS_IN_DELAY</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Number of SPI clocks after chip select to wait before capturing MISO input
+
+Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIPSS_IN_COUNT</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Number of bits captured on MISO input
+
+Supported values: 0x000 to spi_frame_size. The actual number of bits captured is spi_frame_size - spi_in_delay
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIPSS_CLOCK_POLARITY</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+SPIPSS Clock Polarity (CPOL=0 means that clk idle is deasserted, CPOH=1 means that clk idle is asserted)
+ </description>
+ <valueType>uint8</valueType>
+ <enum>CPOL=0, CPOH=1</enum>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIPSS_CLOCK_PHASE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+SPIPSS clock phase (CPHA=0 means to change/sample values of data signals on first edge, otherwise on 2nd)
+ </description>
+ <valueType>uint8</valueType>
+ <enum>FIRSTEDGE=0, SECONDEDGE=1</enum>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIPSS_CLOCK_DIVIDER</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+SPI clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+
+Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time
+
+0x00000: Wait 1 PSS Clock
+0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses
+
+For values greater than 0x00000, the actual delay is 1 PSS Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 PSSI clock cycle.
+
+Producer: proc_pm_effective
+
+Consumer: proc_pss_init
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPIPSS_INTER_FRAME_DELAY</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+Delay between two frames of a P2S command as measured from the end of the last bit of the first frame until the chip select of the second frame. (binary in nanoseconds)
+
+Consumer: proc_pm_effective
+
+Produces ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PBAX_RCV_RESERV_TIMEOUT</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+PBAX Data Timeout Divider
+Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang pulses are received under the following conditions:
+- Data Hi packet accepted and timeout waiting for Data Lo packet.
+- Reservation aquired and timeout waiting for Data Hi packet.
+
+00000 = Data Timeout is Disabled
+00001 = divided hang pulse = PBAX hang pulse
+00010 = divided hang pulse = PBAX hang pulse/2
+00011 = divided hang pulse = PBAX hang pulse/3
+. . .
+11111 = divided hang pulse = PBAX hang pulse/31
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+PBAX Send Retry count overcommit
+Mode bit to count overcommit retries for the send retry threshold when sending PBAX commands on the powerbus.
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PBAX_SND_RETRY_THRESHOLD</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+PBAX Send Retry Threshold
+Defines the maximum number of retry attempts by the Send Engine for any phase of the PBAX transaction set before the operation is dropped and status bit are set. This does not count PowerBus overcommit retries unless snd_retry_count_overcom bit is set.
+
+0x00 : No Timeout
+0x01 : 1 attempt
+0x02 : 2 attempts
+.etc.
+0xFF : 255 attempts
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_PBAX_SND_RESERV_TIMEOUT</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+PBAX Send Reservation Timeout Divider
+Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang pulses are received after attempting to acquire a reservation with the PBAX Receive engine before declaring a Send Reservation Timeout error.
+
+00000 = Send Reservation Timeout is Disabled
+00001 = divided hang pulse = PBAX hang pulse
+00010 = divided hang pulse = PBAX hang pulse/2
+00011 = divided hang pulse = PBAX hang pulse/3
+. . .
+11111 = divided hang pulse = PBAX hang pulse/31
+ </description>
+ <valueType>uint8</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPWUP_FSP</id>
+ <targetType>TARGET_TYPE_EX_CHIPLET</targetType>
+ <description>
+Arbitration Attribute for FSP special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0.
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPWUP_OCC</id>
+ <targetType>TARGET_TYPE_EX_CHIPLET</targetType>
+ <description>
+Arbitration Attribute for OCC special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0.
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+<attribute>
+ <id>ATTR_PM_SPWUP_PHYP</id>
+ <targetType>TARGET_TYPE_EX_CHIPLET</targetType>
+ <description>
+Arbitration Attribute for PHYP special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0.
+ </description>
+ <valueType>uint32</valueType>
+ <writeable/>
+</attribute>
+
+</attributes>
diff --git a/src/usr/hwpf/hwp/runtime_attributes/pm_attributes_all_plat.xml b/src/usr/hwpf/hwp/runtime_attributes/pm_attributes_all_plat.xml new file mode 100644 index 000000000..17f1952dd --- /dev/null +++ b/src/usr/hwpf/hwp/runtime_attributes/pm_attributes_all_plat.xml @@ -0,0 +1,453 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/runtime_attributes/pm_attributes_all_plat.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- + XML file specifying Power Management HWPF attributes. + These attributes are initialized by the platform. +--> + +<attributes> +<!-- *********************************************************************** --> + +<attribute> + <id>ATTR_PROC_DCM_INSTALLED</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +This attribute is set to 1 if the target processor is part of a Dual Chip Module (DCM). + +Used for enabling operations between the two chips for to voltage control based on 'interchip_mode' and the settings of PMIC0. + +Consumer: proc_pm.scominit + </description> + <valueType>uint8</valueType> + <enum>TRUE = 1, FALSE = 0</enum> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_EXTERNAL_VRM_STEPSIZE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Step size (binary in microvolts) to take upon external VRM voltage transitions. The value set here must take into account where internal VRMs are enabled or not as, when they are enabled, the step size must account for the tracking (eg PFET strength recalculation) for the step. + +MRWB after system characterization + +Consumer: proc_build_pstate_tables.C, proc_pmc_init.C -config + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_EXTERNAL_VRM_STEPDELAY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Step delay (binary in microseconds) after a voltage change + +Producer: MRWB after system characterization + + +Consumer: proc_pmc_init -config + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_SAFE_VOLTAGE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + +Voltage (binary in 5mv units) that is invoked upon the loss of the OCC Heartbeat. + +Used to determine the Pstate to load into the hardware for automatic reaction upon the loss of the OCC heartbeat . This value needs to be at or above that which supports the nominal frequency to make sure safe operation of all chiplets. + +The value is translated to the Pstate space. + +Consumer: proc_pm_effective.C + +DYNAMIC_ATTRIBUTE: ATTR_PM_SAFE_PSTATE + +Consumer: proc_pm.scominit + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Minimum frequency (binary in 5mv units) for which undervolting is allowed. Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value. + +Consumer: OCC FW; OCC Lab Tools + +Need to create a process for MRWB elements to get passed to OCC (FW or lab tools) + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Maximum frequency for which undervolting is allowed. Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value. + +Consumer: OCC FW; OCC Lab Tools + +Need to create a process for MRWB elements to get passed to OCC (FW or lab tools) + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_SPIVID_FREQUENCY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +SPI Clock Frequency (binary in MHz) +Consumer: proc_pm_effective + +Produces ATTR_PM_SPIVID_CLOCK_DIVIDER + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_SPIVID_PORT_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Defines the configuration of the SPIVID ports from the target. NONE means that no VRM is attached; PORTxNONRED means that the indicated port is used in a non-redundant configuration; REDUNDANT means that all three are connected and considered redundant. + </description> + <valueType>uint8</valueType> + <enum>NONE=0b000, PORT0NONRED=0b100, PORT1NONRED=0b010, PORT2NONRED=0b001,REDUNDANT=0b111</enum> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_SLEEP_ENTRY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Setting depends on di/dt charateristics of the system. + +Set Assisted if power off serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency + +Producer: MRWB + +Consumer: proc_pm_init -config and proc_pcbs_init + </description> + <valueType>uint8</valueType> + <enum>HARDWARE=0, ASSISTED=1</enum> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_SLEEP_EXIT</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Setting depends on di/dt charateristics of the system and the setting of ATTR_PM_SLEEP_TYPE. + +Set to Assisted if power on serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency +Must be set to Assisted if ATTR_PM_SLEEP_TYPE=Deep as this necessary for restore. + +Setting to Hardware is a test mode for Fast only. + +Producer: MRWB + +Consumer: proc_pm_init -config and proc_pcbs_init + </description> + <valueType>uint8</valueType> + <enum>HARDWARE=0, ASSISTED=1</enum> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_SLEEP_TYPE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Sleep Power Off Select: +Selects which voltage level to place the Core domain PFETs upon Sleep entry. 0 = Vret (Fast Sleep Mode), 1 = Voff (Deep Sleep Mode) + +Producer: MRWB + +Consumer: proc_pm_init -config and proc_pcbs_init + </description> + <valueType>uint8</valueType> + <enum>FAST=0, DEEP=1</enum> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_WINKLE_ENTRY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Setting depends on di/dt charateristics of the system. + +Set Assisted if power off serialization is needed and WINKE_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency + +Producer: MRWB + +Consumer: proc_pm_init -config and proc_pcbs_init + </description> + <valueType>uint8</valueType> + <enum>HARDWARE=0, ASSISTED=1</enum> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_WINKLE_EXIT</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Setting depends on di/dt charateristics of the system and the setting of ATTR_PM_WINKE_TYPE. + +Set to Assisted if power on serialization is needed and WINKE_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency +Must be set to Assisted if ATTR_PM_WINKE_TYPE=Deep as this necessary for restore. + +Setting to Hardware is a test mode for Fast only. + +Producer: MRWB + +Consumer: proc_pm_effective and proc_pcbs_init. + </description> + <valueType>uint8</valueType> + <enum>HARDWARE=0, ASSISTED=1</enum> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_WINKLE_TYPE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Winkle Power Off Select: +Selects which voltage level to place the Core and ECO domain PFETs upon Winkle entry. 0 = Vret (Fast Winkle Mode), 1 = Voff (Deep Winkle Mode) + +Producer: MRWB + +Consumer: proc_pm_init -config and proc_pcbs_init + </description> + <valueType>uint8</valueType> + <enum>FAST=0, DEEP=1</enum> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_SAFE_FREQUENCY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Safe Frequency (binary in MHz) + +Indicates the frequency that the cores will be moved to in the event of the loss of the OCC Heartbead. This value needs to be at or below the nominal frequency to make sure safe operation of all chiplets. + +The value is translated to the Pstate space. + +Consumer: proc_pm_effective.C + +DYNAMIC_ATTRIBUTE: ATTR_PM_SAFE_PSTATE + +Consumer: proc_pcbs_init.C + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Frequency (binary in MHz) for the point at which clock sector buffers should be at full strength. This is to support Vmin operation. Setting cannot overlap the Low or High bands. + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Frequency (binary in MHz)) for the lower end of the Low Frequency Resonant band + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Frequency (binary in MHz) for the upper end of the Low Frequency Resonant band + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Frequency (binary in MHz) for the lower end of the High Frequency Resonant band + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Frequency (binary in MHz)) for the upper end of the High Frequency Resonant band + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_SPIPSS_FREQUENCY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +SPIPSS Clock Frequency (binary in MHz) + +Valid range: 0.5MHz to 25MHz + +Consumer: proc_pmc_init + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_APSS_CHIP_SELECT</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Defines which of the PSS chip selects that the APSS is connected + </description> + <valueType>uint8</valueType> + <enum>NONE=0xFF, CS0=0x00, CS1=0x01</enum> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_PBAX_NODEID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Receive PBAX Nodeid +Value that indicates this PBA's PBAX Node affinity. This is matched to pbax_nodeid of the PMISC Address phase. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_PBAX_CHIPID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Receive PBAX Chipid +Value that indicates this PBA's PBAX Chipid within the PBAX node. Is matched to pbax_chipid of the Address phase if pbax_type=unicast. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PM_PBAX_BRDCST_ID_VECTOR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> +Receive PBAX Broadcast Group +Vector that is indexed when decoded PMISC pbax_type=broadcast with the decoded PMISC pbax_chipid value. If the bit in this vector at the decoded bit location is a 1, then this receive engine will participate in the broadcast operation. + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PROC_R_LOADLINE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> +Impedance (binary microOhms) of the load line from a processor VRM to the Processor Module pins. This value is applied to each processor instance. + +Producer: MRWB (via the power subsystem design per system) + +Consumers: proc_build_gpstate_table.C + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PROC_R_DISTLOSS</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> +Impedance (binary in microOhms) of the distribution loss the sense point to the circuit. This value is applied to each processor instance. + +Producer: MRWB (via the power subsystem design per system) + +Consumers: proc_build_gpstate_table.C + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PROC_VRM_VOFFSET</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> +Offset voltage (binary in microvolts) to apply to the VRM distribution to the processor module. This value is applied to each processor instance. + +Producer: MRWB (via the power subsystem design per system) + +Consumers: proc_build_gpstate_table.C + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PROC_DPLL_DIVIDER</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> +Feedback divider x forward divider setting for the DPLL + +Producer: MRWB + +Consumers: proc_build_gpstate_table.C + </description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_FREQ_CORE_MAX</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> +Maximum frequency (binary in MHz) that any processor in the system will run. Used to define the top end of the PState range in the frequency space. +From this, the ATTR_PROCPM_PSTATE0_FREQUENCY is computed using ATTR_SYSTEM_REFCLK_FREQUENCY to determine the step size. + +Producer: MRWB (system design) + +Consumers: proc_build_gpstate_table.C (among others) + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +</attributes> diff --git a/src/usr/hwpf/hwp/runtime_attributes/pm_plat_attributes.xml b/src/usr/hwpf/hwp/runtime_attributes/pm_plat_attributes.xml deleted file mode 100644 index 9d4c44c17..000000000 --- a/src/usr/hwpf/hwp/runtime_attributes/pm_plat_attributes.xml +++ /dev/null @@ -1,352 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/runtime_attributes/pm_plat_attributes.xml $ --> -<!-- --> -<!-- IBM CONFIDENTIAL --> -<!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> -<!-- --> -<!-- p1 --> -<!-- --> -<!-- Object Code Only (OCO) source materials --> -<!-- Licensed Internal Code Source Materials --> -<!-- IBM HostBoot Licensed Internal Code --> -<!-- --> -<!-- The source code for this program is not published or otherwise --> -<!-- divested of its trade secrets, irrespective of what has been --> -<!-- deposited with the U.S. Copyright Office. --> -<!-- --> -<!-- Origin: 30 --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- - XML file specifying Power Management HWPF attributes. - These attributes are initialized by the platform. ---> - -<attributes> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_EXTERNAL_VRM_STEPSIZE</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Step size (binary in microvolts) to take upon external VRM voltage - transitions. The value set here must take into account where internal - VRMs are enabled or not as, when they are enabled, the step size must - account for the tracking (eg PFET strength recalculation) for the step. - - Consumer: proc_build_pstate_tables.C, proc_pmc_init.C -config - - Provided by the Machine Readable Workbook after system characterization. - </description> - <valueType>uint8</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_EXTERNAL_VRM_STEPDELAY</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Step delay (binary in microseconds) after a voltage change - - Consumer: proc_pmc_init -config - - Provided by the Machine Readable Workbook after system characterization. - </description> - <valueType>uint32</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - Minimum frequency for which undervolting is allowed. Will be internally - rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value. - - Consumer: OCC FW; OCC Lab Tools - - Provided by the Machine Readable Workbook. - </description> - <valueType>uint8</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - Maximum frequency for which undervolting is allowed. Will be internally - rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value. - - Consumer: OCC FW; OCC Lab Tools - - Provided by the Machine Readable Workbook. - </description> - <valueType>uint8</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_SPIVID_FREQUENCY</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - SPI Clock Frequency (binary in MHz) - - Consumer: proc_pm_effective - - Produces ATTR_PM_SPIVID_CLOCK_DIVIDER - - Provided by the Machine Readable Workbook. - </description> - <valueType>uint32</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_SPIVID_PORT_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - Defines the configuration of the SPIVID ports from the target. - - NONE means that no VRM is attached. - - PORTxNONRED means that the indicated port is used in a non-redundant - configuration. - - REDUNDANT means that all three are connected and considered redundant. - - Provided by the Machine Readable Workbook. - </description> - <valueType>uint8</valueType> - <enum>NONE = 0x00, PORT0NONRED = 0x04, PORT1NONRED = 0x02, PORT2NONRED = 0x01, REDUNDANT = 0x07</enum> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_SAFE_FREQUENCY</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Indicates the frequency that the cores will be moved to in the event of - the loss of the OCC Heartbead. This value needs to be at or below the - nominal frequency to make sure safe operation of all chiplets. - - Valid Values:-128 thru 127 - - The value is translated to the Pstate space. - - Consumer: proc_pm_effective.C - - DYNAMIC_ATTRIBUTE: ATTR_PM_SAFE_PSTATE - - Consumer: proc_pcbs_init.C - - TODO: Dean said this may either be provided by the Machine Readable - Workbook or Todd R's power management def file. - </description> - <valueType>uint8</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Frequency (binary in MHz) for the point at which clock sector buffers - should be at full strength. This is to support Vmin operation. - Setting cannot overlap the Low or High bands. - - Provided by the Machine Readable Workbook after system characterization. - </description> - <valueType>uint32</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Frequency (binary in MHz)) for the lower end of the Low Frequency - Resonant band - - Provided by the Machine Readable Workbook after system characterization. - </description> - <valueType>uint32</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Frequency (binary in MHz) for the upper end of the Low Frequency - Resonant band - - Provided by the Machine Readable Workbook after system characterization. - </description> - <valueType>uint32</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Frequency (binary in MHz) for the lower end of the High Frequency - Resonant band - - Provided by the Machine Readable Workbook after system characterization. - </description> - <valueType>uint32</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Frequency (binary in MHz)) for the upper end of the High Frequency - Resonant band - - Provided by the Machine Readable Workbook after system characterization. - </description> - <valueType>uint32</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_SPIPSS_FREQUENCY</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - SPIPSS Clock Frequency (binary in MHz) - - Valid range: 0.5MHz to 25MHz - - Consumer: proc_pmc_init - - Provided by the Machine Readable Workbook. - </description> - <valueType>uint32</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_APSS_CHIP_SELECT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - Defines which of the PSS chip selects that the APSS is connected - - Provided by the Machine Readable Workbook. - </description> - <valueType>uint8</valueType> - <enum>NONE = 0xFF, CS0 = 0x00, CS1 = 0x01</enum> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_PBAX_NODEID</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - Receive PBAX Nodeid. Value that indicates this PBA's PBAX Node affinity. - This is matched to pbax_nodeid of the PMISC Address phase. - - Provided by the Machine Readable Workbook. - </description> - <valueType>uint8</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_PBAX_CHIPID</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - Receive PBAX Chipid. Value that indicates this PBA's PBAX Chipid within - the PBAX node. Is matched to pbax_chipid of the Address phase if - pbax_type=unicast. - - Provided by the Machine Readable Workbook. - </description> - <valueType>uint8</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PM_PBAX_BRDCST_ID_VECTOR</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - Receive PBAX Broadcast Group. Vector that is indexed when decoded PMISC - pbax_type=broadcast with the decoded PMISC pbax_chipid value. If the - bit in this vector at the decoded bit location is a 1, then this receive - engine will participate in the broadcast operation. - - Provided by the Machine Readable Workbook. - </description> - <valueType>uint8</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_R_LOADLINE</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Impedance (binary microOhms) of the load line from a processor VRM to the - Processor Module pins. This value is applied to each processor instance. - - Consumers: proc_build_gpstate_table.C - - Provided by the Machine Readable Workbook (via the power subsystem design - per system) - </description> - <valueType>uint32</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_R_DISTLOSS</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Impedance (binary in microOhms) of the distribution loss the sense point - to the circuit. This value is applied to each processor instance. - - Consumers: proc_build_gpstate_table.C - - Provided by the Machine Readable Workbook (via the power subsystem design - per system) - </description> - <valueType>uint32</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_VRM_VOFFSET</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Offset voltage (binary in microvolts) to apply to the VRM distribution to - the processor module. This value is applied to each processor instance. - - Consumers: proc_build_gpstate_table.C - - Provided by the Machine Readable Workbook (via the power subsystem design - per system) - </description> - <valueType>uint32</valueType> - <platInit/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_FREQ_CORE_MAX</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Maximum frequency (binary in MHz) that any processor in the system will - run. Used to define the top end of the PState range in the frequency space. - From this, the ATTR_PROCPM_PSTATE0_FREQUENCY is computed using - ATTR_SYSTEM_REFCLK_FREQUENCY to determine the step size. - - Consumers: proc_build_gpstate_table.C (among others) - - TODO: Dean's proposal is that each platform will iterate over all chips, - reading the super-turbo frequency from MVPD #V and set this attribute - to the lowest value. - </description> - <valueType>uint32</valueType> - <platInit/> - </attribute> -</attributes> diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index 17fca2812..a48b4df62 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -73,8 +73,8 @@ HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \ hwp/dram_initialization/proc_setup_bars/proc_setup_bars_l3_attributes.xml \ hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml \ hwp/activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml \ - hwp/runtime_attributes/pm_plat_attributes.xml \ - hwp/runtime_attributes/pm_hwp_attributes.xml + hwp/runtime_attributes/pm_attributes_all_plat.xml \ + hwp/runtime_attributes/pm_attributes_all_hwp.xml #------------------------------------------------------------------------------ # Initfiles diff --git a/src/usr/hwpf/plat/fapiPlatAttributeService.C b/src/usr/hwpf/plat/fapiPlatAttributeService.C index 22e325ce6..0d72fbd44 100644 --- a/src/usr/hwpf/plat/fapiPlatAttributeService.C +++ b/src/usr/hwpf/plat/fapiPlatAttributeService.C @@ -55,23 +55,6 @@ namespace fapi namespace platAttrSvc { -//@fixme begin RTC:42293 -fapi::ReturnCode return0_uint8( uint8_t &o_data ) { - fapi::ReturnCode l_rc; - o_data = 0; - return l_rc; -} -fapi::ReturnCode return0_uint32( uint32_t &o_data ) { - fapi::ReturnCode l_rc; - o_data = 0; - return l_rc; -} -fapi::ReturnCode set_ignore( void ) { - fapi::ReturnCode l_rc; - return l_rc; -} -//@fixme end - //****************************************************************************** // fapi::platAttrSvc::getHostbootTarget //****************************************************************************** diff --git a/src/usr/runtime/common/create_hsvc_data.pl b/src/usr/runtime/common/create_hsvc_data.pl new file mode 100755 index 000000000..ce29a52f0 --- /dev/null +++ b/src/usr/runtime/common/create_hsvc_data.pl @@ -0,0 +1,350 @@ +#!/usr/bin/perl +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/runtime/common/create_hsvc_data.pl $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + +# This script will parse a set of attribute xml files and HWP +# source files in order to discover the list of required +# attributes to push up to the Host Services code from Hostboot. +# The ouput is a set of 3 data files that are used by the code +# that populates mainstore. +# +# Note that this implementation is currently incomplete, it will +# be finished as part of RTC:50411 + +use strict; + +my $debug = 0; +my $warning = 0; +my @input_files; + +for (my $i=0; $i < $#ARGV + 1; $i++) +{ + if ($ARGV[$i] =~ /-h/) + { + print_usage(); + exit; + } + elsif ($ARGV[$i] =~ /-d/) + { + $debug = 1; + print "Debug Mode\n"; + } + elsif ($ARGV[$i] =~ /-w/) + { + $warning = 1; + print "Warnings enabled\n"; + } + else + { + # must be the input filename + push @input_files, $ARGV[$i]; + } +} + +my $date = chopit(`date`); +my $user = chopit(`whoami`); + +## Open up all of the output files +if( -e "hsvc_sysdata.C" ) { + die("hsvc_sysdata.C file already exists\n"); +} +open SYS_FILE, ">hsvc_sysdata.C", or die("Could not create hsvc_sysdata.C\n"); +print SYS_FILE "// Generated on $date by $user from \n"; + +if( -e "hsvc_procdata.C" ) { + die("hsvc_procdata.C file already exists\n"); +} +open PROC_FILE, ">hsvc_procdata.C", or die("Could not create hsvc_procdata.C\n"); +print PROC_FILE "// Generated on $date by $user from \n"; + +if( -e "hsvc_exdata.C" ) { + die("hsvc_exdata.C file already exists\n"); +} +open EX_FILE, ">hsvc_exdata.C", or die("Could not create hsvc_exdata.C\n"); +print EX_FILE "// Generated on $date by $user from \n"; + +# Keep a list for each type of attribute ever to find dupes +my @sys_all; +my @proc_all;; +my @ex_all; + +## Loop through all of the XML input files +foreach my $ifile (@input_files) +{ + # Skip any non-XML files in this loop + if( !($ifile =~ /xml/) ) + { + next; + } + + # Open the file + print "Processing: $ifile\n"; + open IN_FILE, $ifile or die("Cannot open $ifile\n"); + + # Keep a list for each type of attribute in this file + my @sys; + my @proc; + my @ex; + + # Loop through the files and print out each line based on timestamp + my $linenum = 0; + my $id = ""; + my $target = ""; + while(my $curline = <IN_FILE>) + { + $linenum++; + if( $curline =~ /<attribute>/ ) + { + + } + elsif( $curline =~ /<id>/ ) + { + # <id>ATTR_PM_POWER_PROXY_TRACE_TIMER</id> + my @divide = split( /[<>]/, $curline ); + #print "xx:$divide[0],$divide[1],$divide[2],$divide[3]:xx\n"; + $id = $divide[2]; + if($debug){print "id=$id.\n";} + } + elsif( $curline =~ /<targetType>/ ) + { + # <targetType>TARGET_TYPE_PROC_CHIP</targetType> + my @divide = split( /[<>]/, $curline ); + #print "xx:$divide[0],$divide[1],$divide[2],$divide[3]:xx\n"; + $target = $divide[2]; + if($debug){print "target=$target.\n";} + } + elsif( $curline =~ /<\/attribute>/ ) + { + # MVPD attributes are read live by HostServices code + if( $id =~ /MVPD/ ) + { + if($debug){print "Skipping MVPD: %id\n";} + } + elsif( $target =~ /TARGET_TYPE_PROC_CHIP/ ) + { + if($debug){print "PROC_CHIP: $id.\n";} + if( check_for_dupe($id,\@proc_all) ) + { + if( $warning ) { + print "Duplicate attribute found for PROC '$id' in $ifile\n"; + } + } + else + { + push @proc, $id; + push @proc_all, $id; + } + } + elsif( $target =~ /TARGET_TYPE_SYSTEM/ ) + { + if($debug){print "SYSTEM: $id.\n";} + push @sys, $id; + push @sys_all, $id; + } + elsif( $target =~ /TARGET_TYPE_EX_CHIPLET/ ) + { + if($debug){print "EX_CHIPLET: $id.\n";} + push @ex, $id; + push @ex_all, $id; + } + else + { + die("UNKNOWN targetType : $target\n"); + } + } + + } + + close IN_FILE; + + # Now print out the 3 files + + # sysdata + print SYS_FILE "// -- Input: $ifile --\n"; + if( $#sys > 0 ) + { + @sys = sort(@sys); + foreach my $attr (@sys) + { + # HSVC_LOAD_ATTR( ATTR_FREQ_PB ); + print SYS_FILE "HSVC_LOAD_ATTR( $attr );\n"; + } + } + else + { + print SYS_FILE "// No attributes found\n"; + } + + # procdata + print PROC_FILE "// -- Input: $ifile --\n"; + if( $#proc > 0 ) + { + @sys = sort(@proc); + foreach my $attr (@proc) + { + # HSVC_LOAD_ATTR( ATTR_FREQ_PB ); + print PROC_FILE "HSVC_LOAD_ATTR( $attr );\n"; + } + } + else + { + print PROC_FILE "// No attributes found\n"; + } + + # exdata + print EX_FILE "// -- Input: $ifile --\n"; + if( $#ex > 0 ) + { + @sys = sort(@ex); + foreach my $attr (@ex) + { + # HSVC_LOAD_ATTR( ATTR_FREQ_PB ); + print EX_FILE "HSVC_LOAD_ATTR( $attr );\n"; + } + } + else + { + print EX_FILE "// No attributes found\n"; + } + +} + + +## Loop through all of the HWP input files +foreach my $ifile (@input_files) +{ + # Skip any XML files in this loop + if( $ifile =~ /xml/ ) + { + next; + } + + # Open the file + print "Processing: $ifile\n"; + open IN_FILE, $ifile or die("Cannot open $ifile\n"); + + # Keep a list for each type of attribute in this file + my @missing; + + # Loop through the files and print out each line based on timestamp + my $linenum = 0; + while(my $curline = <IN_FILE>) + { + $linenum++; + + if( substr($curline,0,2) eq "//" ) + { + next; + } + #@todo - Ignore calls inside block comments RTC:48350 + + my $startnum = index( $curline, "FAPI_ATTR_" ); + if( $startnum == -1 ) + { + next; + } + + my $attrstart = index( $curline, "ATTR_", $startnum+10 ); + if( $attrstart == -1 ) + { + if($debug) { + print "Something is odd with the procedure call\n"; + print " ".$linenum.":".$curline; + } + next; + } + my $attrstop = index( $curline, ",", $attrstart ); + my $id = chopit( substr( $curline, $attrstart, $attrstop-$attrstart ) ); + #print "id=$id.\n"; + + # MVPD attributes are read live by HostServices code + if( $id =~ /MVPD/ ) + { + if($debug){print "Skipping MVPD: %id\n";} + } + else + { + if( check_for_dupe($id,\@proc_all) + || check_for_dupe($id,\@ex_all) + || check_for_dupe($id,\@sys_all) ) + { + push @missing, $id; + } + else + { + if( !check_for_dupe($id,\@missing) ) + { + print "Missing attribute: $id.\n"; + } + if($debug){print " ".$linenum.":".$curline;} + } + } + + } + + close IN_FILE; +} + + +close SYS_FILE; +close PROC_FILE; +close EX_FILE; + +exit; + +################################################## + +# remove all leading and trailing whitespace +sub chopit +{ + my $temp = shift(@_); + $temp =~ s/^\s+//; + $temp =~ s/\s+$//; + return $temp; +} + +# look for duplicate attributes +sub check_for_dupe +{ + my $attr = shift(@_); + my @list = @{shift(@_)}; + + foreach my $entry (@list) + { + if( $entry eq $attr ) + { + return 1; + } + } + return 0; +} + +# print usage help +sub print_usage +{ + print "Generate the hscv_xxxdata.C files for Hostboot\n"; + print "Usage: create_hsvc_data.pl [-d] [-w] [filename1] [filename2] ...\n"; + print " -d : Enable debug tracing\n"; + print " -w : Enable tracing of warning messages, e.g. duplicate attributes\n"; + print " filenameX : 1 or more input attribute xml files\n"; +} diff --git a/src/usr/runtime/common/extra_runtime_attributes.xml b/src/usr/runtime/common/extra_runtime_attributes.xml new file mode 100644 index 000000000..0c3356302 --- /dev/null +++ b/src/usr/runtime/common/extra_runtime_attributes.xml @@ -0,0 +1,55 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/runtime/common/extra_runtime_attributes.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- +Contains FAPI attributes that we want to send up to HostServices +that may not be specifically defined in the various HWP attribute +xml files and procedures + +Parser only requires attribute, id and targetType tags. +--> + +<attribute> + <id>ATTR_CHIP_ID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> +</attribute> + +<attribute> + <id>ATTR_FUNCTIONAL</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> +</attribute> + +<attribute> + <id>ATTR_CHIP_UNIT_POS</id> + <targetType>TARGET_TYPE_EX_CHIPLET</targetType> +</attribute> + +<attribute> + <id>ATTR_FUNCTIONAL</id> + <targetType>TARGET_TYPE_EX_CHIPLET</targetType> +</attribute> + +<attribute> + <id>ATTR_FREQ_PB</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> +</attribute> + diff --git a/src/usr/runtime/common/hsvc_exdata.C b/src/usr/runtime/common/hsvc_exdata.C index ce9b042c1..f60531a75 100644 --- a/src/usr/runtime/common/hsvc_exdata.C +++ b/src/usr/runtime/common/hsvc_exdata.C @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/runtime/hsvc_exdata.C $ */ +/* $Source: src/usr/runtime/common/hsvc_exdata.C $ */ /* */ /* IBM CONFIDENTIAL */ /* */ @@ -20,8 +20,13 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -//@todo - This file will be autogenerated by the HostServices build RTC:48350 -// This file was generated on MM/DD/YYYY by username from build xxxxx - -HSVC_LOAD_ATTR( ATTR_CHIP_UNIT_POS ); +// Generated on Wed Oct 17 08:41:32 CDT 2012 by dcrowell from +// -- Input: src/usr/runtime/common/extra_runtime_attributes.xml -- +HSVC_LOAD_ATTR( ATTR_CHIP_UNIT_POS ); HSVC_LOAD_ATTR( ATTR_FUNCTIONAL ); +// -- Input: src/usr/hwpf/hwp/runtime_attributes/pm_attributes_all_plat.xml -- +// No attributes found +// -- Input: src/usr/hwpf/hwp/runtime_attributes/pm_attributes_all_hwp.xml -- +HSVC_LOAD_ATTR( ATTR_PM_SPWUP_FSP ); +HSVC_LOAD_ATTR( ATTR_PM_SPWUP_OCC ); +HSVC_LOAD_ATTR( ATTR_PM_SPWUP_PHYP ); diff --git a/src/usr/runtime/common/hsvc_procdata.C b/src/usr/runtime/common/hsvc_procdata.C index 21f24af68..a3547192e 100644 --- a/src/usr/runtime/common/hsvc_procdata.C +++ b/src/usr/runtime/common/hsvc_procdata.C @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/runtime/hsvc_procdata.C $ */ +/* $Source: src/usr/runtime/common/hsvc_procdata.C $ */ /* */ /* IBM CONFIDENTIAL */ /* */ @@ -20,79 +20,102 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -//@todo - This file will be autogenerated by the HostServices build RTC:48350 -// This file was generated on MM/DD/YYYY by username from build xxxxx - -HSVC_LOAD_ATTR( ATTR_CHIP_ID ); -HSVC_LOAD_ATTR( ATTR_FUNCTIONAL ); -HSVC_LOAD_ATTR_P( ATTR_EC ); -HSVC_LOAD_ATTR( ATTR_PM_AISS_TIMEOUT ); -HSVC_LOAD_ATTR( ATTR_PM_APSS_CHIP_SELECT ); -HSVC_LOAD_ATTR( ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE ); -HSVC_LOAD_ATTR( ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE ); -HSVC_LOAD_ATTR( ATTR_PM_IVRMS_ENABLED ); -HSVC_LOAD_ATTR( ATTR_PM_OCC_HEARTBEAT_TIME ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_CORE_DELAY0 ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_CORE_DELAY1 ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_ECO_DELAY0 ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_ECO_DELAY1 ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_CORE_DELAY0 ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_CORE_DELAY1 ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_ECO_DELAY0 ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_ECO_DELAY1 ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE ); -HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT ); -HSVC_LOAD_ATTR( ATTR_PM_PMC_HANGPULSE_DIVIDER ); +// Generated on Wed Oct 17 08:41:32 CDT 2012 by dcrowell from +// -- Input: src/usr/runtime/common/extra_runtime_attributes.xml -- +HSVC_LOAD_ATTR( ATTR_CHIP_ID ); +HSVC_LOAD_ATTR( ATTR_FUNCTIONAL ); +// -- Input: src/usr/hwpf/hwp/runtime_attributes/pm_attributes_all_plat.xml -- +HSVC_LOAD_ATTR( ATTR_PROC_DCM_INSTALLED ); +HSVC_LOAD_ATTR( ATTR_PM_EXTERNAL_VRM_STEPSIZE ); +HSVC_LOAD_ATTR( ATTR_PM_EXTERNAL_VRM_STEPDELAY ); +HSVC_LOAD_ATTR( ATTR_PM_SAFE_VOLTAGE ); +HSVC_LOAD_ATTR( ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM ); +HSVC_LOAD_ATTR( ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_FREQUENCY ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_PORT_ENABLE ); +HSVC_LOAD_ATTR( ATTR_PM_SLEEP_ENTRY ); +HSVC_LOAD_ATTR( ATTR_PM_SLEEP_EXIT ); +HSVC_LOAD_ATTR( ATTR_PM_SLEEP_TYPE ); +HSVC_LOAD_ATTR( ATTR_PM_WINKLE_ENTRY ); +HSVC_LOAD_ATTR( ATTR_PM_WINKLE_EXIT ); +HSVC_LOAD_ATTR( ATTR_PM_WINKLE_TYPE ); +HSVC_LOAD_ATTR( ATTR_PM_SAFE_FREQUENCY ); +HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY ); +HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY ); +HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY ); +HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY ); +HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY ); +HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_FREQUENCY ); +HSVC_LOAD_ATTR( ATTR_PM_APSS_CHIP_SELECT ); +HSVC_LOAD_ATTR( ATTR_PM_PBAX_NODEID ); +HSVC_LOAD_ATTR( ATTR_PM_PBAX_CHIPID ); +HSVC_LOAD_ATTR( ATTR_PM_PBAX_BRDCST_ID_VECTOR ); +// -- Input: src/usr/hwpf/hwp/runtime_attributes/pm_attributes_all_hwp.xml -- HSVC_LOAD_ATTR( ATTR_PM_POWER_PROXY_TRACE_TIMER ); -HSVC_LOAD_ATTR( ATTR_PM_PPT_TIMER_MATCH_VALUE ); +HSVC_LOAD_ATTR( ATTR_PM_PPT_TIMER_MATCH_VALUE ); HSVC_LOAD_ATTR( ATTR_PM_PPT_TIMER_TICK ); -HSVC_LOAD_ATTR( ATTR_PM_PSTATE_STEPSIZE ); -HSVC_LOAD_ATTR( ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM ); -HSVC_LOAD_ATTR( ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM ); -HSVC_LOAD_ATTR( ATTR_PM_PVSAFE_PSTATE ); -HSVC_LOAD_ATTR( ATTR_PM_SAFE_PSTATE ); -HSVC_LOAD_ATTR( ATTR_PM_SLEEP_ENTRY ); -HSVC_LOAD_ATTR( ATTR_PM_SLEEP_EXIT ); -HSVC_LOAD_ATTR( ATTR_PM_SLEEP_TYPE ); -HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_CLOCK_DIVIDER ); -HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_CLOCK_PHASE ); -HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_CLOCK_POLARITY ); -HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_FRAME_SIZE ); -HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_FREQUENCY ); -HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_IN_COUNT ); -HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_IN_DELAY ); -HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_INTER_FRAME_DELAY ); -//HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_INTER_FRAME_DELAY_WRITE_SETTNG ); -//HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_INTERFRAME_DELAY_WRITE_STATUS_VALUE ); -HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_OUT_COUNT ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CLOCK_DIVIDER ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CLOCK_PHASE ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CLOCK_POLARITY ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CRC_CHECK_ENABLE ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CRC_GEN_ENABLE ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_FRAME_SIZE ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_IN_DELAY_FRAME1 ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_IN_DELAY_FRAME2 ); -//HSVC_LOAD_ATTR( ATTR_PM_SPIVID_INTER_FRAME_DELAY ); -//HSVC_LOAD_ATTR( ATTR_PM_SPIVID_INTER_FRAME_DELAY_WRITE_STATUS ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_INTER_RETRY_DELAY ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_MAX_RETRIES ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_PORT_ENABLE ); -//"HSVC_LOAD_ATTR( ATTR_PM_WINKLE_ENTRY" ); -//"HSVC_LOAD_ATTR( ATTR_PM_WINKLE_EXIT" ); -HSVC_LOAD_ATTR( ATTR_PM_WINKLE_TYPE ); +HSVC_LOAD_ATTR( ATTR_PM_AISS_TIMEOUT ); +HSVC_LOAD_ATTR( ATTR_PM_PSTATE_STEPSIZE ); +HSVC_LOAD_ATTR( ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE ); +HSVC_LOAD_ATTR( ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE ); +HSVC_LOAD_ATTR( ATTR_PM_PMC_HANGPULSE_DIVIDER ); +HSVC_LOAD_ATTR( ATTR_PM_PVSAFE_PSTATE ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_FRAME_SIZE ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_IN_DELAY_FRAME1 ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_IN_DELAY_FRAME2 ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CLOCK_POLARITY ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CLOCK_PHASE ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CLOCK_DIVIDER ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_INTER_RETRY_DELAY ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CRC_GEN_ENABLE ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CRC_CHECK_ENABLE ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_MAX_RETRIES ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES ); +HSVC_LOAD_ATTR( ATTR_PM_OCC_HEARTBEAT_TIME ); +HSVC_LOAD_ATTR( ATTR_PM_SLEEP_WINKLE_REQUEST_TIMEOUT ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_CORE_DELAY0 ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_CORE_DELAY1 ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_CORE_DELAY0 ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_CORE_DELAY1 ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_ECO_DELAY0 ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_ECO_DELAY1 ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_ECO_DELAY0 ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_ECO_DELAY1 ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE ); +HSVC_LOAD_ATTR( ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT ); +HSVC_LOAD_ATTR( ATTR_PM_PSTATE0_FREQUENCY ); +HSVC_LOAD_ATTR( ATTR_PM_IVRMS_ENABLED ); +HSVC_LOAD_ATTR( ATTR_PM_SAFE_PSTATE ); +HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_ENABLE ); +HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_FULL_CSB_PSTATE ); +HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_LFRLOW_PSTATE ); +HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_LFRUPPER_PSTATE ); +HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_HFRLOW_PSTATE ); +HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_HFRHIGH_PSTATE ); +HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_FRAME_SIZE ); +HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_OUT_COUNT ); +HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_IN_DELAY ); +HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_IN_COUNT ); +HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_CLOCK_POLARITY ); +HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_CLOCK_PHASE ); +HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_CLOCK_DIVIDER ); +HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING ); +HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_INTER_FRAME_DELAY ); +HSVC_LOAD_ATTR( ATTR_PM_PBAX_RCV_RESERV_TIMEOUT ); +HSVC_LOAD_ATTR( ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE ); +HSVC_LOAD_ATTR( ATTR_PM_PBAX_SND_RETRY_THRESHOLD ); +HSVC_LOAD_ATTR( ATTR_PM_PBAX_SND_RESERV_TIMEOUT ); diff --git a/src/usr/runtime/common/hsvc_sysdata.C b/src/usr/runtime/common/hsvc_sysdata.C index 590c5fb3c..ab9a341cf 100644 --- a/src/usr/runtime/common/hsvc_sysdata.C +++ b/src/usr/runtime/common/hsvc_sysdata.C @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/runtime/hsvc_sysdata.C $ */ +/* $Source: src/usr/runtime/common/hsvc_sysdata.C $ */ /* */ /* IBM CONFIDENTIAL */ /* */ @@ -20,19 +20,14 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -//@todo - This file will be autogenerated by the HostServices build RTC:48350 -// This file was generated on MM/DD/YYYY by username from build xxxxx - -HSVC_LOAD_ATTR( ATTR_FREQ_PB ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_FREQUENCY ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CLOCK_POLARITY ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CLOCK_PHASE ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_PORT_ENABLE ); -//HSVC_LOAD_ATTR( ATTR_PM_SPIVID_INTER_FRAME_DELAY_WRITE_STATUS ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_INTER_RETRY_DELAY ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CRC_GEN_ENABLE ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CRC_CHECK_ENABLE ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_MAX_RETRIES ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_IN_DELAY_FRAME1 ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_IN_DELAY_FRAME2 ); +// Generated on Wed Oct 17 08:41:32 CDT 2012 by dcrowell from +// -- Input: src/usr/runtime/common/extra_runtime_attributes.xml -- +// No attributes found +// -- Input: src/usr/hwpf/hwp/runtime_attributes/pm_attributes_all_plat.xml -- +HSVC_LOAD_ATTR( ATTR_FREQ_CORE_MAX ); +HSVC_LOAD_ATTR( ATTR_PROC_DPLL_DIVIDER ); +HSVC_LOAD_ATTR( ATTR_PROC_R_DISTLOSS ); +HSVC_LOAD_ATTR( ATTR_PROC_R_LOADLINE ); +HSVC_LOAD_ATTR( ATTR_PROC_VRM_VOFFSET ); +// -- Input: src/usr/hwpf/hwp/runtime_attributes/pm_attributes_all_hwp.xml -- +// No attributes found diff --git a/src/usr/runtime/populate_attributes.C b/src/usr/runtime/populate_attributes.C index ed100dd9b..51b96668a 100644 --- a/src/usr/runtime/populate_attributes.C +++ b/src/usr/runtime/populate_attributes.C @@ -49,7 +49,7 @@ TRAC_INIT(&g_trac_runtime, "RUNTIME", 4096); fapi::__fid##_Type result_##__fid; \ _rc = FAPI_ATTR_GET( __fid, _target, result_##__fid ); \ if( _rc ) { \ - TRACFCOMP( g_trac_runtime, "Error reading %d, rc=0x%X", fapi::__fid, _rc ); \ + TRACFCOMP( g_trac_runtime, "Error reading 0x%X, rc=0x%X", fapi::__fid, _rc ); \ _failed_attribute = fapi::__fid; \ break; \ } \ @@ -69,7 +69,7 @@ TRAC_INIT(&g_trac_runtime, "RUNTIME", 4096); fapi::__fid##_Type result_##__fid; \ _rc = FAPI_ATTR_GET_PRIVILEGED( __fid, _target, result_##__fid ); \ if( _rc ) { \ - TRACFCOMP( g_trac_runtime, "Error reading %d, rc=0x%X", fapi::__fid, _rc ); \ + TRACFCOMP( g_trac_runtime, "Error reading 0x%X, rc=0x%X", fapi::__fid, _rc ); \ _failed_attribute = fapi::__fid; \ break; \ } \ @@ -188,7 +188,8 @@ errlHndl_t populate_system_attributes( void ) TRACFCOMP( g_trac_runtime, "-SYSTEM-" ); // allocate memory and fill it with some junk data - system_data_t* sys_data = reinterpret_cast<system_data_t*>(SYSTEM_DATA_POINTER); + system_data_t* sys_data = + reinterpret_cast<system_data_t*>(SYSTEM_DATA_POINTER); memset( sys_data, 'A', sizeof(system_data_t) ); // These variables are used by the HSVC_LOAD_ATTR macros directly @@ -212,7 +213,8 @@ errlHndl_t populate_system_attributes( void ) TARGETING::targetService().getTopLevelTarget(sys); // Fill in the metadata - sys_data->hsvc.offset = reinterpret_cast<uint64_t>(sys_data->attrHeaders) + sys_data->hsvc.offset = + reinterpret_cast<uint64_t>(sys_data->attrHeaders) - reinterpret_cast<uint64_t>(sys_data); sys_data->hsvc.nodePresent = 0x8000000000000000; sys_data->hsvc.numAttr = 0; @@ -268,7 +270,8 @@ errlHndl_t populate_node_attributes( uint64_t i_nodeNum ) TRACFCOMP( g_trac_runtime, "-NODE-" ); // allocate memory and fill it with some junk data - node_data_t* node_data = reinterpret_cast<node_data_t*>(NODE_DATA_POINTER); + node_data_t* node_data = + reinterpret_cast<node_data_t*>(NODE_DATA_POINTER); memset( node_data, 'A', sizeof(node_data) ); // These variables are used by the HSVC_LOAD_ATTR macros directly @@ -290,7 +293,9 @@ errlHndl_t populate_node_attributes( uint64_t i_nodeNum ) // Fill in the metadat node_data->hsvc.numTargets = 0; - node_data->hsvc.procOffset = reinterpret_cast<uint64_t>(node_data->procs) - reinterpret_cast<uint64_t>(node_data); + node_data->hsvc.procOffset = + reinterpret_cast<uint64_t>(node_data->procs) + - reinterpret_cast<uint64_t>(node_data); // Get the list of processors TARGETING::TargetHandleList all_procs; @@ -314,7 +319,9 @@ errlHndl_t populate_node_attributes( uint64_t i_nodeNum ) // Fill in the metadata node_data->procs[p].procid = procid; - node_data->procs[p].offset = reinterpret_cast<uint64_t>(&(node_data->procAttrHeaders[p][0])) - reinterpret_cast<uint64_t>(node_data); + node_data->procs[p].offset = + reinterpret_cast<uint64_t>(&(node_data->procAttrHeaders[p][0])) + - reinterpret_cast<uint64_t>(node_data); node_data->procs[p].numAttr = 0; (node_data->hsvc.numTargets)++; @@ -326,6 +333,7 @@ errlHndl_t populate_node_attributes( uint64_t i_nodeNum ) // Fill up the attributes ADD_HUID( (all_procs[p]) ); // for debug ADD_PHYS_PATH( (all_procs[p]) ); + HSVC_LOAD_ATTR_P( ATTR_EC ); // Use a generated file for the list of attributes to load #include "common/hsvc_procdata.C" @@ -339,15 +347,21 @@ errlHndl_t populate_node_attributes( uint64_t i_nodeNum ) TARGETING::TYPE_EX, false ); for( size_t e = 0; e < all_ex.size(); e++ ) { - uint32_t chiplet = all_ex[e]->getAttr<TARGETING::ATTR_CHIP_UNIT>(); + uint32_t chiplet = + all_ex[e]->getAttr<TARGETING::ATTR_CHIP_UNIT>(); TRACFCOMP( g_trac_runtime, "EX:p%d c%d(%.8X)", procid, chiplet, get_huid(all_ex[e]) ); // Fill in the metadata (node_data->hsvc.numTargets)++; node_data->ex[next_ex].parent_procid = procid; node_data->ex[next_ex].chiplet = chiplet; - node_data->ex[next_ex].offset = reinterpret_cast<uint64_t>(&(node_data->exAttrHeaders[next_ex][0])) - reinterpret_cast<uint64_t>(node_data); - node_data->hsvc.exOffset = reinterpret_cast<uint64_t>(node_data->ex) - reinterpret_cast<uint64_t>(node_data); + node_data->ex[next_ex].offset = + reinterpret_cast<uint64_t>( + &(node_data->exAttrHeaders[next_ex][0])) + - reinterpret_cast<uint64_t>(node_data); + node_data->hsvc.exOffset = + reinterpret_cast<uint64_t>(node_data->ex) + - reinterpret_cast<uint64_t>(node_data); node_data->ex[next_ex].numAttr = 0; // Cast to a FAPI type of target. diff --git a/src/usr/runtime/test/runtimeattrstest.H b/src/usr/runtime/test/runtimeattrstest.H index e9e508c2e..037c779e3 100644 --- a/src/usr/runtime/test/runtimeattrstest.H +++ b/src/usr/runtime/test/runtimeattrstest.H @@ -87,11 +87,11 @@ class RuntimeTest: public CxxTest::TestSuite TS_FAIL("Error getting fapi::ATTR_FREQ_PB"); } - fapi::ATTR_PM_SPIVID_CRC_GEN_ENABLE_Type crc_gen_enable = 0; - l_rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_GEN_ENABLE,NULL,crc_gen_enable); + fapi::ATTR_PROC_R_LOADLINE_Type spivid = 0; + l_rc = FAPI_ATTR_GET(ATTR_PROC_R_LOADLINE,NULL,spivid); if( l_rc ) { - TS_FAIL("Error getting fapi::ATTR_PM_SPIVID_CRC_GEN_ENABLE"); + TS_FAIL("Error getting fapi::ATTR_PROC_R_LOADLINE"); } uint64_t attr = 0; @@ -117,23 +117,23 @@ class RuntimeTest: public CxxTest::TestSuite } } } - else if( headers[attr].id == fapi::ATTR_PM_SPIVID_CRC_GEN_ENABLE ) + else if( headers[attr].id == fapi::ATTR_PROC_R_LOADLINE ) { if( headers[attr].sizeBytes != - sizeof(fapi::ATTR_PM_SPIVID_CRC_GEN_ENABLE_Type) ) + sizeof(fapi::ATTR_PROC_R_LOADLINE_Type) ) { TRACFCOMP( g_trac_runtime, "size=%.16X", headers[attr].sizeBytes ); - TS_FAIL("Size of fapi::ATTR_PM_SPIVID_CRC_GEN_ENABLE data is wrong"); + TS_FAIL("Size of fapi::ATTR_PROC_R_LOADLINE data is wrong"); } else { - fapi::ATTR_PM_SPIVID_CRC_GEN_ENABLE_Type* crc_gen_enable_act = - reinterpret_cast<fapi::ATTR_PM_SPIVID_CRC_GEN_ENABLE_Type*> + fapi::ATTR_PROC_R_LOADLINE_Type* spivid_act = + reinterpret_cast<fapi::ATTR_PROC_R_LOADLINE_Type*> (beginning+headers[attr].offset); - if( *crc_gen_enable_act != crc_gen_enable ) + if( *spivid_act != spivid ) { - TRACFCOMP( g_trac_runtime, "Expected=%X, Actual=%X", crc_gen_enable, *crc_gen_enable_act ); - TS_FAIL("fapi::ATTR_PM_SPIVID_CRC_GEN_ENABLE data is wrong"); + TRACFCOMP( g_trac_runtime, "Expected=%X, Actual=%X", spivid, *spivid_act ); + TS_FAIL("fapi::ATTR_PROC_R_LOADLINE data is wrong"); } } } diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index a52b34232..8723c13db 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -2948,6 +2948,7 @@ <uint8_t></uint8_t> </simpleType> <persistency>non-volatile</persistency> + <hasStringConversion/> <readable/> <hwpfToHbAttrMap> <id>ATTR_PROC_EPS_TABLE_TYPE</id> @@ -2981,6 +2982,7 @@ <uint8_t></uint8_t> </simpleType> <persistency>non-volatile</persistency> + <hasStringConversion/> <readable/> <hwpfToHbAttrMap> <id>ATTR_PROC_FABRIC_PUMP_MODE</id> @@ -3012,6 +3014,7 @@ <uint8_t></uint8_t> </simpleType> <persistency>non-volatile</persistency> + <hasStringConversion/> <readable/> <hwpfToHbAttrMap> <id>ATTR_PROC_X_BUS_WIDTH</id> @@ -4741,4 +4744,2088 @@ bits6:7 will be consumed together to form COARSE_LVL. </description> </enumerator> </enumerationType> +<!-- Support for pm_attributes_all_hwp.xml --> + +<attribute> + <id>PM_POWER_PROXY_TRACE_TIMER</id> + <description> + PROC_CHIP Attribute + The Power Proxy Trace timer (binary in microseconds) defines the time between Power Proxy Trace records when no other event that would otherwise produce a record has occured. Values must be within a range of 32us to 64ms. + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_POWER_PROXY_TRACE_TIMER</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PPT_TIMER_MATCH_VALUE</id> + <description> + PROC_CHIP Attribute + The delay is 32us * ATTR_PM_PPT_TIMER_MATCH_VALUE + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PPT_TIMER_MATCH_VALUE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PPT_TIMER_TICK</id> + <description> + PROC_CHIP Attribute + Defines the Power Proxy Trace interval timer tick (0=25us, 1=0.5us, 2=1us, and 3=2us) + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PPT_TIMER_TICK</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_AISS_TIMEOUT</id> + <description> + PROC_CHIP Attribute + Defines the timeout value for the Architected Idle State Sequencer (AISS). + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_AISS_TIMEOUT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PSTATE_STEPSIZE</id> + <description> + PROC_CHIP Attribute + Unsigned 7 bit (baby-) stepsize for Pstate transitions between the Global Pstate Actual and the Global Pstate Target. Only non-zero values are supported for this dial. + +Used to setup the PMC voltage controller + +Producer: proc_build_pstate_tables.C + +Consumer: OCC pstate_init() + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PSTATE_STEPSIZE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_EXTERNAL_VRM_STEPDELAY_RANGE</id> + <description> + PROC_CHIP Attribute + Selects the resolution for the step delay count after a voltage change (decimal value N for this field divides the prv clock by 2^(N+3)) + +A 4 bit field selects one of the the upper 16bit of a 19bit counter (16+3) incremented in the nest/4 domain + +Consumer: proc_pm.scominit + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_EXTERNAL_VRM_STEPDELAY_VALUE</id> + <description> + PROC_CHIP Attribute + Step delay after a voltage change in increments of vrm_stepdelay_range. Setting this dial to a value N causes a delay of N cycles of the divided nest clk (see dial vrm_stepdelay_range). The closed formula is as follows: Delay_seconds = vrm_stepdelay_value * ( 2^(3 + vrm_stepdelay_range) / (Nest_frequency_Hz/4)) + +Consumer: proc_pm.scominit + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PMC_HANGPULSE_DIVIDER</id> + <description> + PROC_CHIP Attribute + Divides the hang pulse to PMC to achieve XXXX. Note that this needs to be set according to the description of dial pmc_occ_heartbeat_time + +Producer: prc_pm_effective + +Consumer: proc_pm.scominit + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PMC_HANGPULSE_DIVIDER</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PVSAFE_PSTATE</id> + <description> + PROC_CHIP Attribute + +Pstate that is invoked in the PMC voltage controller upon the loss of the OCC Heartbeat.. + +Producer: proc_pm_effective.C + +Consumer: proc_pm.scominit + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PVSAFE_PSTATE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_FRAME_SIZE</id> + <description> + PROC_CHIP Attribute + Number of data bits per individual SPIVID transaction (also referred to as frame) during chip select assertion + +Supported values: 0x20 (32d) + +Chip Select assertion duration is spi_frame_size + 2 + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_FRAME_SIZE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_IN_DELAY_FRAME1</id> + <description> + PROC_CHIP Attribute + Number of SPIVID clocks after chip select to wait before capturing MISO input in frame 1 + +Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_IN_DELAY_FRAME1</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_IN_DELAY_FRAME2</id> + <description> + PROC_CHIP Attribute + Number of SPI clocks after chip select to wait before capturing MISO input in frame 2 + +Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_IN_DELAY_FRAME2</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_CLOCK_POLARITY</id> + <description> + PROC_CHIP Attribute + SPVID Clock Polarity (CPOL=0 means that clk idle is deasserted, CPOL=1 means that clk idle is asserted) + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_CLOCK_POLARITY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_CLOCK_PHASE</id> + <description> + PROC_CHIP Attribute + SPI clock phase (CPHA=0 means to change/sample values of data signals on first edge, otherwise on 2nd) + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_CLOCK_PHASE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_CLOCK_DIVIDER</id> + <description> + PROC_CHIP Attribute + SPIVID clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1 +For a 2.4GHz nest clock, this means that the SPI clk can be theoretically adjusted between 600MHz and 0.29MHz (cycle time 1.66ns...3.41us, in 1.66ns steps). However, a practical range is 0.5...25MHz. + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_CLOCK_DIVIDER</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS</id> + <description> + PROC_CHIP Attribute + Delay between command and status frames of a SPIVID 'WRITE' operation (binary in nanoseconds) +Consumer: proc_pmc_init + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE</id> + <description> + PROC_CHIP Attribute + Delay between two frames of a Write command as measured from the end of the last bit of the first frame until the chip select of the second frame, which contains the status, is asserted. This delay allows for the checking and status data production in the SPIVID chip. + +Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time + +0x00000: Wait 1 SPI Clock +0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses + +For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle. + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_INTER_RETRY_DELAY_VALUE</id> + <description> + PROC_CHIP Attribute + Delay between command retry attempts. + +Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time + +0x0000: Wait 1 SPI Clock +0x0001 - 0xFFFF: value = number of ~100ns_hang_pulses + +For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle. + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_INTER_RETRY_DELAY</id> + <description> + PROC_CHIP Attribute + Delay between SPIVID reture attempts when WRITE command status indicates an error (binary in nanoseconds) +Consumer: proc_pmc_init + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_INTER_RETRY_DELAY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_CRC_GEN_ENABLE</id> + <description> + PROC_CHIP Attribute + EnableS CRC generation from processor to VRM device. This will produce an 8b CRC per the enabled polynomial. If CRC generation is disabled, the full 32 bits at the data input of the SPI master are transmitted. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_CRC_GEN_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_CRC_CHECK_ENABLE</id> + <description> + PROC_CHIP Attribute + Enables CRC checking in the processor of frames from the VRM device. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_CRC_CHECK_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_MAJORITY_VOTE_ENABLE</id> + <description> + PROC_CHIP Attribute + enables the a majority vote on the 3B of status payload on a frame received by the master as each of these have a 1 byte status field replicated three (3) times by the slave. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_MAX_RETRIES</id> + <description> + PROC_CHIP Attribute + Number retries upon detected errors. + +0x00: No retry +0x01 to 0x1F: 1 to 31 respectively + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_MAX_RETRIES</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_CRC_POLYNOMIAL_ENABLES</id> + <description> + PROC_CHIP Attribute + CRC8 Polynomial Enables + +An 8 bit mask vector to enable XORs in the CRC generation and checking LFSRs at the respective bit position. MSB (x^8) is omitted since it is always enabled, so the mask layout is (x^7,x^6,x^5,x^4,x^3,x^2,x^1,1) + +Planned CRC8 polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 +Value to enable planned polynomial: 0b1101_0101 (=0xD5) + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_OCC_HEARTBEAT_TIME</id> + <description> + PROC_CHIP Attribute + Time within which the OCC firmware must access the PMC or the OCC will be considered faulty whereby FIRs and malfunction alerts will be produced . (binary in nanoseconds) +Consumer: OCC FW + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_OCC_HEARTBEAT_TIME</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SLEEP_WINKLE_REQUEST_TIMEOUT</id> + <description> + PROC_CHIP Attribute + Time (binary in ns) that will be the threshold value for the PMC PORE request timeout. + +Consumer: proc_pmc_init.C. Will be translated to a DYNAMIC ATTRIBUTE for use by proc_pm..scominit as a multiple of PM hang pulses.. Counter starts at 0, is increased with every tp_pmc_hang_pulse as long as PORE is busy and set the PMC local FIR bit 19 when count = threshold. + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SLEEP_WINKLE_REQUEST_TIMEOUT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERUP_CORE_DELAY0</id> + <description> + PROC_CHIP Attribute + Delay (binary in nanoseconds) after a step in the Core power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERUP_CORE_DELAY0</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERUP_CORE_DELAY1</id> + <description> + PROC_CHIP Attribute + Delay (binary in nanoseconds) after a step in the Core power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERUP_CORE_DELAY1</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERUP_CORE_DELAY0_VALUE</id> + <description> + PROC_CHIP Attribute + Delay value 0 between any step in the Core power-up PFET sequence. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERUP_CORE_DELAY1_VALUE</id> + <description> + PROC_CHIP Attribute + Delay value 1 between any step in the Core power-up PFET sequence. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT</id> + <description> + PROC_CHIP Attribute + Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the sequence. Power up goes from 11, then 10, then 9,.... then 0. + +0 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY0; + +1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1 + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERDOWN_CORE_DELAY0</id> + <description> + PROC_CHIP Attribute + Delay (binary in nanoseconds) between a step in the Core power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY0</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERDOWN_CORE_DELAY1</id> + <description> + PROC_CHIP Attribute + Delay (binary in nanoseconds) between a step in the Core power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY1</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERDOWN_CORE_DELAY0_VALUE</id> + <description> + PROC_CHIP Attribute + Delay value 0 between any step in the Core power-up PFET sequence. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERDOWN_CORE_DELAY1_VALUE</id> + <description> + PROC_CHIP Attribute + Delay value 1 between any step in the Core power-up PFET sequence. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT</id> + <description> + PROC_CHIP Attribute + Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the sequence. Power up goes from 11, then 10, then 9,.... then 0. + +0 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY0; + +1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1 + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERUP_ECO_DELAY0</id> + <description> + PROC_CHIP Attribute + Delay (binary in nanoseconds) after a step in the ECO power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERUP_ECO_DELAY0</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERUP_ECO_DELAY1</id> + <description> + PROC_CHIP Attribute + Delay (binary in nanoseconds) after a step in the ECO power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERUP_ECO_DELAY1</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERUP_ECO_DELAY0_VALUE</id> + <description> + PROC_CHIP Attribute + Delay value 0 between any step in the ECO power-up PFET sequence. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERUP_ECO_DELAY1_VALUE</id> + <description> + PROC_CHIP Attribute + Delay value 1 between any step in the ECO power-up PFET sequence. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT</id> + <description> + PROC_CHIP Attribute + Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the sequence. Power up goes from 11, then 10, then 9,.... then 0. + +0 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY0; + +1 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY1 + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERDOWN_ECO_DELAY0</id> + <description> + PROC_CHIP Attribute + Delay (binary in nanoseconds) between a step in the ECO power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY0</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERDOWN_ECO_DELAY1</id> + <description> + PROC_CHIP Attribute + Delay (binary in nanoseconds) between a step in the ECO power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY1</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERDOWN_ECO_DELAY0_VALUE</id> + <description> + PROC_CHIP Attribute + Delay value 0 between any step in the ECO power-up PFET sequence. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERDOWN_ECO_DELAY1_VALUE</id> + <description> + PROC_CHIP Attribute + Delay value 1 between any step in the ECO power-up PFET sequence. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</id> + <description> + PROC_CHIP Attribute + Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the ECO power up sequence. Power up goes from 11, then 10, then 9,.... then 0. 0 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY0; 1 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY1 + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PSTATE0_FREQUENCY</id> + <description> + PROC_CHIP Attribute + Defines the center point of the Pstate space in the frequency domain. Binary in Khz. + +Producer: proc_build_gpstate.C + +Consumers: proc_pcbs_init.C, proc_pcbs_lpst_init.C, + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PSTATE0_FREQUENCY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_IVRMS_ENABLED</id> + <description> + PROC_CHIP Attribute + Indicates whether available internal voltage regulation macros (iVRMs) are to enabled. This indicates that module VPD has valid #M keywords available. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_IVRMS_ENABLED</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SAFE_PSTATE</id> + <description> + PROC_CHIP Attribute + Safe Pstate + +Valid Values:-128 thru 127 + +Producer: proc_pm_effective.C + +DYNAMIC_ATTRIBUTE + +Consumer: proc_pcbs_init.C + +Establishes the Pstate that the core chiplet will take on if: +psafe less than or equal to PMSR[global_actual_pstate] +AND any of the following conditions are true: +Loss of OCC Heartbeat if occ_heartbeat_en is set +PMGP0[force_safe_mode] is set + +If psafe > PMSR[global_actual_pstate], the global_actual_pstate is forced. + +The value of Psafe needs to be at or below the nominal Pstate to make sure safe operation of all chiplets. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SAFE_PSTATE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_RESONANT_CLOCK_ENABLE</id> + <description> + PROC_CHIP Attribute + Resonant Clock Enable + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_RESONANT_CLOCK_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_RESONANT_CLOCK_FULL_CSB_PSTATE</id> + <description> + PROC_CHIP Attribute + FCSB = Full Clock Sector Buffer (8b in terms of Pstate) +Defines the Pstate for the point at which clock sector buffers should be at full strength. This is to support Vmin operation. + + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_RESONANT_CLOCK_FULL_CSB_PSTATE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_RESONANT_CLOCK_LFRLOW_PSTATE</id> + <description> + PROC_CHIP Attribute + LFRLower = Low Frequency Resonant Lower. Defines the Pstate for the lower end of the Low Frequency Resonant band + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_RESONANT_CLOCK_LFRLOW_PSTATE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_RESONANT_CLOCK_LFRUPPER_PSTATE</id> + <description> + PROC_CHIP Attribute + LFRUpper = Low Frequency Resonant Upper. Defines the Pstate for the upper end of the Low Frequency Resonant band + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_RESONANT_CLOCK_LFRUPPER_PSTATE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_RESONANT_CLOCK_HFRLOW_PSTATE</id> + <description> + PROC_CHIP Attribute + HFRLower = High Frequency Resonant Low. Defines the Pstate for the lower end of the High Frequency Resonant band + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_RESONANT_CLOCK_HFRLOW_PSTATE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_RESONANT_CLOCK_HFRHIGH_PSTATE</id> + <description> + PROC_CHIP Attribute + HFRUpper = High Frequency Resonant Upper. Defines the Pstate for the upper end of the High Frequency Resonant band + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_RESONANT_CLOCK_HFRHIGH_PSTATE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIPSS_FRAME_SIZE</id> + <description> + PROC_CHIP Attribute + Number of data bits per individual SPIPSS transaction (also referred to as frame) during chip select assertion + +Supported values: 0x10 (16d), + +Chip Select assertion duration is spi_frame_size + 2 + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIPSS_FRAME_SIZE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIPSS_OUT_COUNT</id> + <description> + PROC_CHIP Attribute + Number of bits sent out MOSI of the frame + +Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size are ignored. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIPSS_OUT_COUNT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIPSS_IN_DELAY</id> + <description> + PROC_CHIP Attribute + Number of SPI clocks after chip select to wait before capturing MISO input + +Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIPSS_IN_DELAY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIPSS_IN_COUNT</id> + <description> + PROC_CHIP Attribute + Number of bits captured on MISO input + +Supported values: 0x000 to spi_frame_size. The actual number of bits captured is spi_frame_size - spi_in_delay + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIPSS_IN_COUNT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIPSS_CLOCK_POLARITY</id> + <description> + PROC_CHIP Attribute + SPIPSS Clock Polarity (CPOL=0 means that clk idle is deasserted, CPOH=1 means that clk idle is asserted) + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIPSS_CLOCK_POLARITY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIPSS_CLOCK_PHASE</id> + <description> + PROC_CHIP Attribute + SPIPSS clock phase (CPHA=0 means to change/sample values of data signals on first edge, otherwise on 2nd) + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIPSS_CLOCK_PHASE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIPSS_CLOCK_DIVIDER</id> + <description> + PROC_CHIP Attribute + SPI clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1 + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIPSS_CLOCK_DIVIDER</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIPSS_INTER_FRAME_DELAY_SETTING</id> + <description> + PROC_CHIP Attribute + +Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time + +0x00000: Wait 1 PSS Clock +0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses + +For values greater than 0x00000, the actual delay is 1 PSS Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 PSSI clock cycle. + +Producer: proc_pm_effective + +Consumer: proc_pss_init + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIPSS_INTER_FRAME_DELAY</id> + <description> + PROC_CHIP Attribute + Delay between two frames of a P2S command as measured from the end of the last bit of the first frame until the chip select of the second frame. (binary in nanoseconds) + +Consumer: proc_pm_effective + +Produces ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIPSS_INTER_FRAME_DELAY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PBAX_RCV_RESERV_TIMEOUT</id> + <description> + PROC_CHIP Attribute + PBAX Data Timeout Divider +Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang pulses are received under the following conditions: +- Data Hi packet accepted and timeout waiting for Data Lo packet. +- Reservation aquired and timeout waiting for Data Hi packet. + +00000 = Data Timeout is Disabled +00001 = divided hang pulse = PBAX hang pulse +00010 = divided hang pulse = PBAX hang pulse/2 +00011 = divided hang pulse = PBAX hang pulse/3 +. . . +11111 = divided hang pulse = PBAX hang pulse/31 + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PBAX_RCV_RESERV_TIMEOUT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE</id> + <description> + PROC_CHIP Attribute + PBAX Send Retry count overcommit +Mode bit to count overcommit retries for the send retry threshold when sending PBAX commands on the powerbus. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PBAX_SND_RETRY_THRESHOLD</id> + <description> + PROC_CHIP Attribute + PBAX Send Retry Threshold +Defines the maximum number of retry attempts by the Send Engine for any phase of the PBAX transaction set before the operation is dropped and status bit are set. This does not count PowerBus overcommit retries unless snd_retry_count_overcom bit is set. + +0x00 : No Timeout +0x01 : 1 attempt +0x02 : 2 attempts +.etc. +0xFF : 255 attempts + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PBAX_SND_RETRY_THRESHOLD</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PBAX_SND_RESERV_TIMEOUT</id> + <description> + PROC_CHIP Attribute + PBAX Send Reservation Timeout Divider +Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang pulses are received after attempting to acquire a reservation with the PBAX Receive engine before declaring a Send Reservation Timeout error. + +00000 = Send Reservation Timeout is Disabled +00001 = divided hang pulse = PBAX hang pulse +00010 = divided hang pulse = PBAX hang pulse/2 +00011 = divided hang pulse = PBAX hang pulse/3 +. . . +11111 = divided hang pulse = PBAX hang pulse/31 + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PBAX_SND_RESERV_TIMEOUT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPWUP_FSP</id> + <description> + EX_CHIPLET Attribute + PBAX Send Reservation Timeout Divider +Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang pulses are received after attempting to acquire a reservation with the PBAX Receive engine before declaring a Send Reservation Timeout error. + +00000 = Send Reservation Timeout is Disabled +00001 = divided hang pulse = PBAX hang pulse +00010 = divided hang pulse = PBAX hang pulse/2 +00011 = divided hang pulse = PBAX hang pulse/3 +. . . +11111 = divided hang pulse = PBAX hang pulse/31 + Arbitration Attribute for FSP special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0. + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPWUP_FSP</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPWUP_OCC</id> + <description> + EX_CHIPLET Attribute + PBAX Send Reservation Timeout Divider +Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang pulses are received after attempting to acquire a reservation with the PBAX Receive engine before declaring a Send Reservation Timeout error. + +00000 = Send Reservation Timeout is Disabled +00001 = divided hang pulse = PBAX hang pulse +00010 = divided hang pulse = PBAX hang pulse/2 +00011 = divided hang pulse = PBAX hang pulse/3 +. . . +11111 = divided hang pulse = PBAX hang pulse/31 + Arbitration Attribute for FSP special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0. + Arbitration Attribute for OCC special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0. + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPWUP_OCC</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPWUP_PHYP</id> + <description> + EX_CHIPLET Attribute + PBAX Send Reservation Timeout Divider +Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang pulses are received after attempting to acquire a reservation with the PBAX Receive engine before declaring a Send Reservation Timeout error. + +00000 = Send Reservation Timeout is Disabled +00001 = divided hang pulse = PBAX hang pulse +00010 = divided hang pulse = PBAX hang pulse/2 +00011 = divided hang pulse = PBAX hang pulse/3 +. . . +11111 = divided hang pulse = PBAX hang pulse/31 + Arbitration Attribute for FSP special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0. + Arbitration Attribute for OCC special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0. + Arbitration Attribute for PHYP special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0. + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPWUP_PHYP</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<!-- End pm_attributes_all_hwp.xml --> + + +<!-- Support for pm_attributes_all_plat.xml --> + +<attribute> + <id>PROC_DCM_INSTALLED</id> + <description> + PROC_CHIP Attribute +This attribute is set to 1 if the target processor is part of a Dual Chip Module (DCM). + +Used for enabling operations between the two chips for to voltage control based on 'interchip_mode' and the settings of PMIC0. + +Consumer: proc_pm.scominit + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_DCM_INSTALLED</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_EXTERNAL_VRM_STEPSIZE</id> + <description> + PROC_CHIP Attribute +Step size (binary in microvolts) to take upon external VRM voltage transitions. The value set here must take into account where internal VRMs are enabled or not as, when they are enabled, the step size must account for the tracking (eg PFET strength recalculation) for the step. + +MRWB after system characterization + +Consumer: proc_build_pstate_tables.C, proc_pmc_init.C -config + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_EXTERNAL_VRM_STEPSIZE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_EXTERNAL_VRM_STEPDELAY</id> + <description> + PROC_CHIP Attribute +Step delay (binary in microseconds) after a voltage change + +Producer: MRWB after system characterization + + +Consumer: proc_pmc_init -config + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_EXTERNAL_VRM_STEPDELAY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SAFE_VOLTAGE</id> + <description> + PROC_CHIP Attribute + +Voltage (binary in 5mv units) that is invoked upon the loss of the OCC Heartbeat. + +Used to determine the Pstate to load into the hardware for automatic reaction upon the loss of the OCC heartbeat . This value needs to be at or above that which supports the nominal frequency to make sure safe operation of all chiplets. + +The value is translated to the Pstate space. + +Consumer: proc_pm_effective.C + +DYNAMIC_ATTRIBUTE: ATTR_PM_SAFE_PSTATE + +Consumer: proc_pm.scominit + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SAFE_VOLTAGE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <description> + PROC_CHIP Attribute +Minimum frequency (binary in 5mv units) for which undervolting is allowed. Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value. + +Consumer: OCC FW; OCC Lab Tools + +Need to create a process for MRWB elements to get passed to OCC (FW or lab tools) + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <description> + PROC_CHIP Attribute +Maximum frequency for which undervolting is allowed. Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value. + +Consumer: OCC FW; OCC Lab Tools + +Need to create a process for MRWB elements to get passed to OCC (FW or lab tools) + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_FREQUENCY</id> + <description> + PROC_CHIP Attribute +SPI Clock Frequency (binary in MHz) +Consumer: proc_pm_effective + +Produces ATTR_PM_SPIVID_CLOCK_DIVIDER + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_FREQUENCY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIVID_PORT_ENABLE</id> + <description> + PROC_CHIP Attribute +Defines the configuration of the SPIVID ports from the target. NONE means that no VRM is attached; PORTxNONRED means that the indicated port is used in a non-redundant configuration; REDUNDANT means that all three are connected and considered redundant. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIVID_PORT_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SLEEP_ENTRY</id> + <description> + PROC_CHIP Attribute +Setting depends on di/dt charateristics of the system. + +Set Assisted if power off serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency + +Producer: MRWB + +Consumer: proc_pm_init -config and proc_pcbs_init + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SLEEP_ENTRY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SLEEP_EXIT</id> + <description> + PROC_CHIP Attribute +Setting depends on di/dt charateristics of the system and the setting of ATTR_PM_SLEEP_TYPE. + +Set to Assisted if power on serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency +Must be set to Assisted if ATTR_PM_SLEEP_TYPE=Deep as this necessary for restore. + +Setting to Hardware is a test mode for Fast only. + +Producer: MRWB + +Consumer: proc_pm_init -config and proc_pcbs_init + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SLEEP_EXIT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SLEEP_TYPE</id> + <description> + PROC_CHIP Attribute +Sleep Power Off Select: +Selects which voltage level to place the Core domain PFETs upon Sleep entry. 0 = Vret (Fast Sleep Mode), 1 = Voff (Deep Sleep Mode) + +Producer: MRWB + +Consumer: proc_pm_init -config and proc_pcbs_init + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SLEEP_TYPE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_WINKLE_ENTRY</id> + <description> + PROC_CHIP Attribute +Setting depends on di/dt charateristics of the system. + +Set Assisted if power off serialization is needed and WINKE_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency + +Producer: MRWB + +Consumer: proc_pm_init -config and proc_pcbs_init + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_WINKLE_ENTRY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_WINKLE_EXIT</id> + <description> + PROC_CHIP Attribute +Setting depends on di/dt charateristics of the system and the setting of ATTR_PM_WINKE_TYPE. + +Set to Assisted if power on serialization is needed and WINKE_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency +Must be set to Assisted if ATTR_PM_WINKE_TYPE=Deep as this necessary for restore. + +Setting to Hardware is a test mode for Fast only. + +Producer: MRWB + +Consumer: proc_pm_effective and proc_pcbs_init. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_WINKLE_EXIT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_WINKLE_TYPE</id> + <description> + PROC_CHIP Attribute +Winkle Power Off Select: +Selects which voltage level to place the Core and ECO domain PFETs upon Winkle entry. 0 = Vret (Fast Winkle Mode), 1 = Voff (Deep Winkle Mode) + +Producer: MRWB + +Consumer: proc_pm_init -config and proc_pcbs_init + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_WINKLE_TYPE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SAFE_FREQUENCY</id> + <description> + PROC_CHIP Attribute +Safe Frequency (binary in MHz) + +Indicates the frequency that the cores will be moved to in the event of the loss of the OCC Heartbead. This value needs to be at or below the nominal frequency to make sure safe operation of all chiplets. + +The value is translated to the Pstate space. + +Consumer: proc_pm_effective.C + +DYNAMIC_ATTRIBUTE: ATTR_PM_SAFE_PSTATE + +Consumer: proc_pcbs_init.C + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SAFE_FREQUENCY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <description> + PROC_CHIP Attribute +Frequency (binary in MHz) for the point at which clock sector buffers should be at full strength. This is to support Vmin operation. Setting cannot overlap the Low or High bands. + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <description> + PROC_CHIP Attribute +Frequency (binary in MHz)) for the lower end of the Low Frequency Resonant band + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <description> + PROC_CHIP Attribute +Frequency (binary in MHz) for the upper end of the Low Frequency Resonant band + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <description> + PROC_CHIP Attribute +Frequency (binary in MHz) for the lower end of the High Frequency Resonant band + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <description> + PROC_CHIP Attribute +Frequency (binary in MHz)) for the upper end of the High Frequency Resonant band + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPIPSS_FREQUENCY</id> + <description> + PROC_CHIP Attribute +SPIPSS Clock Frequency (binary in MHz) + +Valid range: 0.5MHz to 25MHz + +Consumer: proc_pmc_init + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPIPSS_FREQUENCY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_APSS_CHIP_SELECT</id> + <description> + PROC_CHIP Attribute +Defines which of the PSS chip selects that the APSS is connected + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_APSS_CHIP_SELECT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PBAX_NODEID</id> + <description> + PROC_CHIP Attribute +Receive PBAX Nodeid +Value that indicates this PBA's PBAX Node affinity. This is matched to pbax_nodeid of the PMISC Address phase. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PBAX_NODEID</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PBAX_CHIPID</id> + <description> + PROC_CHIP Attribute +Receive PBAX Chipid +Value that indicates this PBA's PBAX Chipid within the PBAX node. Is matched to pbax_chipid of the Address phase if pbax_type=unicast. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PBAX_CHIPID</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_PBAX_BRDCST_ID_VECTOR</id> + <description> + PROC_CHIP Attribute +Receive PBAX Broadcast Group +Vector that is indexed when decoded PMISC pbax_type=broadcast with the decoded PMISC pbax_chipid value. If the bit in this vector at the decoded bit location is a 1, then this receive engine will participate in the broadcast operation. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_PBAX_BRDCST_ID_VECTOR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_R_LOADLINE</id> + <description> + SYSTEM Attribute +Impedance (binary microOhms) of the load line from a processor VRM to the Processor Module pins. This value is applied to each processor instance. + +Producer: MRWB (via the power subsystem design per system) + +Consumers: proc_build_gpstate_table.C + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_R_LOADLINE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_R_DISTLOSS</id> + <description> + SYSTEM Attribute +Impedance (binary in microOhms) of the distribution loss the sense point to the circuit. This value is applied to each processor instance. + +Producer: MRWB (via the power subsystem design per system) + +Consumers: proc_build_gpstate_table.C + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_R_DISTLOSS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_VRM_VOFFSET</id> + <description> + SYSTEM Attribute +Offset voltage (binary in microvolts) to apply to the VRM distribution to the processor module. This value is applied to each processor instance. + +Producer: MRWB (via the power subsystem design per system) + +Consumers: proc_build_gpstate_table.C + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_VRM_VOFFSET</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_DPLL_DIVIDER</id> + <description> + SYSTEM Attribute +Feedback divider x forward divider setting for the DPLL + +Producer: MRWB + +Consumers: proc_build_gpstate_table.C + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_DPLL_DIVIDER</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>FREQ_CORE_MAX</id> + <description> + SYSTEM Attribute +Maximum frequency (binary in MHz) that any processor in the system will run. Used to define the top end of the PState range in the frequency space. +From this, the ATTR_PROCPM_PSTATE0_FREQUENCY is computed using ATTR_SYSTEM_REFCLK_FREQUENCY to determine the step size. + +Producer: MRWB (system design) + +Consumers: proc_build_gpstate_table.C (among others) + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_FREQ_CORE_MAX</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<!-- End pm_attributes_all_plat.xml --> + + </attributes> diff --git a/src/usr/targeting/common/xmltohb/common.mk b/src/usr/targeting/common/xmltohb/common.mk index 6a6cb8395..5493824be 100644 --- a/src/usr/targeting/common/xmltohb/common.mk +++ b/src/usr/targeting/common/xmltohb/common.mk @@ -69,7 +69,9 @@ FAPI_ATTR_SOURCES = \ dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml \ dram_initialization/proc_setup_bars/proc_setup_bars_l3_attributes.xml \ dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml \ - activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml + activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml \ + runtime_attributes/pm_attributes_all_hwp.xml \ + runtime_attributes/pm_attributes_all_plat.xml XMLTOHB_GENERIC_XML = generic.xml diff --git a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml index 343b0e319..f154fb129 100644 --- a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml @@ -35,6 +35,9 @@ * each Centaur membuf chip has 2 MBA chiplets * each MBA chiplet has 2 ports * each MBA port connects to 2 logical dimms + + Values for pm_attributes_all_plat.xml attributes was provided by + Greg Still on 10/17/1012. ================================================================= --> <!-- System --> @@ -149,6 +152,23 @@ <id>MSS_CLEANER_ENABLE</id> <default>1</default> </attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_R_LOADLINE</id> + <default>890</default> + </attribute> + <attribute><id>PROC_R_DISTLOSS</id> + <default>100</default> + </attribute> + <attribute><id>PROC_VRM_VOFFSET</id> + <default>1000</default> + </attribute> + <attribute><id>FREQ_CORE_MAX</id> + <default>4000</default> + </attribute> + <attribute><id>PROC_DPLL_DIVIDER</id> + <default>10</default> + </attribute> + <!-- End pm_attributes_all_plat.xml --> </targetInstance> <!-- System node 0 --> @@ -229,6 +249,83 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40000000</default> </attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_DCM_INSTALLED</id> + <default>1</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id> + <default>2500</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SAFE_VOLTAGE</id> + <default>1100</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <default>900</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <default>1250</default> + </attribute> + <attribute><id>PM_SPIVID_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SPIVID_PORT_ENABLE</id> + <default>0b100</default><!-- PORT0NONRED --> + </attribute> + <attribute><id>PM_SLEEP_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_WINKLE_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_SAFE_FREQUENCY</id> + <default>3200</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <default>2000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <default>2300</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <default>3000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <default>3050</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <default>4800</default> + </attribute> + <attribute><id>PM_SPIPSS_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_APSS_CHIP_SELECT</id> + <default>0x00</default><!-- CS0 --> + </attribute> + <attribute><id>PM_PBAX_NODEID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_CHIPID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_BRDCST_ID_VECTOR</id> + <default>0</default> + </attribute> + <!-- End pm_attributes_all_plat.xml --> </targetInstance> <!-- Murano n0p0 EX units --> @@ -753,6 +850,83 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40001000</default> </attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_DCM_INSTALLED</id> + <default>1</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id> + <default>0</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id> + <default>0</default> + </attribute> + <attribute><id>PM_SAFE_VOLTAGE</id> + <default>1100</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <default>900</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <default>1250</default> + </attribute> + <attribute><id>PM_SPIVID_FREQUENCY</id> + <default>0</default> + </attribute> + <attribute><id>PM_SPIVID_PORT_ENABLE</id> + <default>0b000</default><!-- NONE --> + </attribute> + <attribute><id>PM_SLEEP_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_WINKLE_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_SAFE_FREQUENCY</id> + <default>3200</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <default>2000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <default>2300</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <default>3000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <default>3050</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <default>4800</default> + </attribute> + <attribute><id>PM_SPIPSS_FREQUENCY</id> + <default>0</default> + </attribute> + <attribute><id>PM_APSS_CHIP_SELECT</id> + <default>0xFF</default><!-- NONE --> + </attribute> + <attribute><id>PM_PBAX_NODEID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_CHIPID</id> + <default>1</default> + </attribute> + <attribute><id>PM_PBAX_BRDCST_ID_VECTOR</id> + <default>0</default> + </attribute> + <!-- End pm_attributes_all_plat.xml --> </targetInstance> <!-- Murano n0p1 EX units --> @@ -1278,6 +1452,83 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40002000</default> </attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_DCM_INSTALLED</id> + <default>1</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id> + <default>2500</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SAFE_VOLTAGE</id> + <default>1100</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <default>900</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <default>1250</default> + </attribute> + <attribute><id>PM_SPIVID_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SPIVID_PORT_ENABLE</id> + <default>0b100</default><!-- PORT0NONRED --> + </attribute> + <attribute><id>PM_SLEEP_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_WINKLE_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_SAFE_FREQUENCY</id> + <default>3200</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <default>2000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <default>2300</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <default>3000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <default>3050</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <default>4800</default> + </attribute> + <attribute><id>PM_SPIPSS_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_APSS_CHIP_SELECT</id> + <default>0xFF</default><!-- NONE --> + </attribute> + <attribute><id>PM_PBAX_NODEID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_CHIPID</id> + <default>2</default> + </attribute> + <attribute><id>PM_PBAX_BRDCST_ID_VECTOR</id> + <default>0</default> + </attribute> + <!-- End pm_attributes_all_plat.xml --> </targetInstance> <!-- Murano n0p2 EX units --> @@ -1804,6 +2055,83 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40003000</default> </attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_DCM_INSTALLED</id> + <default>1</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id> + <default>0</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id> + <default>0</default> + </attribute> + <attribute><id>PM_SAFE_VOLTAGE</id> + <default>1100</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <default>900</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <default>1250</default> + </attribute> + <attribute><id>PM_SPIVID_FREQUENCY</id> + <default>0</default> + </attribute> + <attribute><id>PM_SPIVID_PORT_ENABLE</id> + <default>0b000</default><!-- NONE --> + </attribute> + <attribute><id>PM_SLEEP_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_WINKLE_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_SAFE_FREQUENCY</id> + <default>3200</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <default>2000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <default>2300</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <default>3000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <default>3050</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <default>4800</default> + </attribute> + <attribute><id>PM_SPIPSS_FREQUENCY</id> + <default>0</default> + </attribute> + <attribute><id>PM_APSS_CHIP_SELECT</id> + <default>0xFF</default><!-- NONE --> + </attribute> + <attribute><id>PM_PBAX_NODEID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_CHIPID</id> + <default>3</default> + </attribute> + <attribute><id>PM_PBAX_BRDCST_ID_VECTOR</id> + <default>0</default> + </attribute> + <!-- End pm_attributes_all_plat.xml --> </targetInstance> <!-- Murano n0p3 EX units --> diff --git a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml index e34ed07b8..32bab9ce8 100644 --- a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml @@ -40,6 +40,8 @@ relationship to the FSI ports: cMFSI Port 0-7 = Logical MCS Port 4,5,6,7,0,1,2,3 + Values for pm_attributes_all_plat.xml attributes was provided by + Greg Still on 10/17/1012. ================================================================= --> <!-- System --> @@ -126,6 +128,23 @@ <id>MSS_CLEANER_ENABLE</id> <default>1</default> </attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_R_LOADLINE</id> + <default>890</default> + </attribute> + <attribute><id>PROC_R_DISTLOSS</id> + <default>100</default> + </attribute> + <attribute><id>PROC_VRM_VOFFSET</id> + <default>1000</default> + </attribute> + <attribute><id>FREQ_CORE_MAX</id> + <default>4000</default> + </attribute> + <attribute><id>PROC_DPLL_DIVIDER</id> + <default>10</default> + </attribute> + <!-- End pm_attributes_all_plat.xml --> </targetInstance> <!-- System node 0 --> @@ -206,6 +225,83 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40000000</default> </attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_DCM_INSTALLED</id> + <default>0</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id> + <default>2500</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SAFE_VOLTAGE</id> + <default>1100</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <default>900</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <default>1250</default> + </attribute> + <attribute><id>PM_SPIVID_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SPIVID_PORT_ENABLE</id> + <default>0b111</default><!-- REDUNDANT --> + </attribute> + <attribute><id>PM_SLEEP_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_WINKLE_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_SAFE_FREQUENCY</id> + <default>3200</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <default>2000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <default>2300</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <default>3000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <default>3050</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <default>4800</default> + </attribute> + <attribute><id>PM_SPIPSS_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_APSS_CHIP_SELECT</id> + <default>0x00</default><!-- CS0 --> + </attribute> + <attribute><id>PM_PBAX_NODEID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_CHIPID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_BRDCST_ID_VECTOR</id> + <default>0</default> + </attribute> + <!-- End pm_attributes_all_plat.xml --> </targetInstance> <!-- Venice n0p0 EX units --> @@ -1065,6 +1161,83 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40001000</default> </attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_DCM_INSTALLED</id> + <default>0</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id> + <default>2500</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SAFE_VOLTAGE</id> + <default>1100</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <default>900</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <default>1250</default> + </attribute> + <attribute><id>PM_SPIVID_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SPIVID_PORT_ENABLE</id> + <default>0b111</default><!-- REDUNDANT --> + </attribute> + <attribute><id>PM_SLEEP_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_WINKLE_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_SAFE_FREQUENCY</id> + <default>3200</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <default>2000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <default>2300</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <default>3000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <default>3050</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <default>4800</default> + </attribute> + <attribute><id>PM_SPIPSS_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_APSS_CHIP_SELECT</id> + <default>0x00</default><!-- CS0 --> + </attribute> + <attribute><id>PM_PBAX_NODEID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_CHIPID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_BRDCST_ID_VECTOR</id> + <default>0</default> + </attribute> + <!-- End pm_attributes_all_plat.xml --> </targetInstance> <!-- Venice n0p1 EX units --> @@ -1924,6 +2097,83 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40002000</default> </attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_DCM_INSTALLED</id> + <default>0</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id> + <default>2500</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SAFE_VOLTAGE</id> + <default>1100</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <default>900</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <default>1250</default> + </attribute> + <attribute><id>PM_SPIVID_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SPIVID_PORT_ENABLE</id> + <default>0b111</default><!-- REDUNDANT --> + </attribute> + <attribute><id>PM_SLEEP_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_WINKLE_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_SAFE_FREQUENCY</id> + <default>3200</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <default>2000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <default>2300</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <default>3000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <default>3050</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <default>4800</default> + </attribute> + <attribute><id>PM_SPIPSS_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_APSS_CHIP_SELECT</id> + <default>0x00</default><!-- CS0 --> + </attribute> + <attribute><id>PM_PBAX_NODEID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_CHIPID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_BRDCST_ID_VECTOR</id> + <default>0</default> + </attribute> + <!-- End pm_attributes_all_plat.xml --> </targetInstance> <!-- Venice n0p2 EX units --> @@ -2783,6 +3033,83 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40003000</default> </attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_DCM_INSTALLED</id> + <default>0</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id> + <default>2500</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SAFE_VOLTAGE</id> + <default>1100</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <default>900</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <default>1250</default> + </attribute> + <attribute><id>PM_SPIVID_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SPIVID_PORT_ENABLE</id> + <default>0b111</default><!-- REDUNDANT --> + </attribute> + <attribute><id>PM_SLEEP_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_WINKLE_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_SAFE_FREQUENCY</id> + <default>3200</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <default>2000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <default>2300</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <default>3000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <default>3050</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <default>4800</default> + </attribute> + <attribute><id>PM_SPIPSS_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_APSS_CHIP_SELECT</id> + <default>0x00</default><!-- CS0 --> + </attribute> + <attribute><id>PM_PBAX_NODEID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_CHIPID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_BRDCST_ID_VECTOR</id> + <default>0</default> + </attribute> + <!-- End pm_attributes_all_plat.xml --> </targetInstance> <!-- Venice n0p3 EX units --> @@ -3640,6 +3967,83 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40004000</default> </attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_DCM_INSTALLED</id> + <default>0</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id> + <default>2500</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SAFE_VOLTAGE</id> + <default>1100</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <default>900</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <default>1250</default> + </attribute> + <attribute><id>PM_SPIVID_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SPIVID_PORT_ENABLE</id> + <default>0b111</default><!-- REDUNDANT --> + </attribute> + <attribute><id>PM_SLEEP_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_WINKLE_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_SAFE_FREQUENCY</id> + <default>3200</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <default>2000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <default>2300</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <default>3000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <default>3050</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <default>4800</default> + </attribute> + <attribute><id>PM_SPIPSS_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_APSS_CHIP_SELECT</id> + <default>0x00</default><!-- CS0 --> + </attribute> + <attribute><id>PM_PBAX_NODEID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_CHIPID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_BRDCST_ID_VECTOR</id> + <default>0</default> + </attribute> + <!-- End pm_attributes_all_plat.xml --> </targetInstance> <!-- Venice n0p4 EX units --> @@ -4499,6 +4903,83 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40005000</default> </attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_DCM_INSTALLED</id> + <default>0</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id> + <default>2500</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SAFE_VOLTAGE</id> + <default>1100</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <default>900</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <default>1250</default> + </attribute> + <attribute><id>PM_SPIVID_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SPIVID_PORT_ENABLE</id> + <default>0b111</default><!-- REDUNDANT --> + </attribute> + <attribute><id>PM_SLEEP_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_WINKLE_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_SAFE_FREQUENCY</id> + <default>3200</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <default>2000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <default>2300</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <default>3000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <default>3050</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <default>4800</default> + </attribute> + <attribute><id>PM_SPIPSS_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_APSS_CHIP_SELECT</id> + <default>0x00</default><!-- CS0 --> + </attribute> + <attribute><id>PM_PBAX_NODEID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_CHIPID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_BRDCST_ID_VECTOR</id> + <default>0</default> + </attribute> + <!-- End pm_attributes_all_plat.xml --> </targetInstance> <!-- Venice n0p5 EX units --> @@ -5356,6 +5837,83 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40006000</default> </attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_DCM_INSTALLED</id> + <default>0</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id> + <default>2500</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SAFE_VOLTAGE</id> + <default>1100</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <default>900</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <default>1250</default> + </attribute> + <attribute><id>PM_SPIVID_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SPIVID_PORT_ENABLE</id> + <default>0b111</default><!-- REDUNDANT --> + </attribute> + <attribute><id>PM_SLEEP_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_WINKLE_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_SAFE_FREQUENCY</id> + <default>3200</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <default>2000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <default>2300</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <default>3000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <default>3050</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <default>4800</default> + </attribute> + <attribute><id>PM_SPIPSS_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_APSS_CHIP_SELECT</id> + <default>0x00</default><!-- CS0 --> + </attribute> + <attribute><id>PM_PBAX_NODEID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_CHIPID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_BRDCST_ID_VECTOR</id> + <default>0</default> + </attribute> + <!-- End pm_attributes_all_plat.xml --> </targetInstance> <!-- Venice n0p6 EX units --> @@ -6214,6 +6772,83 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40007000</default> </attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_DCM_INSTALLED</id> + <default>0</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id> + <default>2500</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SAFE_VOLTAGE</id> + <default>1100</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <default>900</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <default>1250</default> + </attribute> + <attribute><id>PM_SPIVID_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SPIVID_PORT_ENABLE</id> + <default>0b111</default><!-- REDUNDANT --> + </attribute> + <attribute><id>PM_SLEEP_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_WINKLE_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_SAFE_FREQUENCY</id> + <default>3200</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <default>2000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <default>2300</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <default>3000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <default>3050</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <default>4800</default> + </attribute> + <attribute><id>PM_SPIPSS_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_APSS_CHIP_SELECT</id> + <default>0x00</default><!-- CS0 --> + </attribute> + <attribute><id>PM_PBAX_NODEID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_CHIPID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_BRDCST_ID_VECTOR</id> + <default>0</default> + </attribute> + <!-- End pm_attributes_all_plat.xml --> </targetInstance> <!-- Venice n0p7 EX units --> @@ -13285,6 +13920,83 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40000000</default> </attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_DCM_INSTALLED</id> + <default>0</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id> + <default>2500</default> + </attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SAFE_VOLTAGE</id> + <default>1100</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id> + <default>900</default> + </attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id> + <default>1250</default> + </attribute> + <attribute><id>PM_SPIVID_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_SPIVID_PORT_ENABLE</id> + <default>0b111</default><!-- REDUNDANT --> + </attribute> + <attribute><id>PM_SLEEP_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_SLEEP_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_WINKLE_ENTRY</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_EXIT</id> + <default>1</default><!-- ASSISTED --> + </attribute> + <attribute><id>PM_WINKLE_TYPE</id> + <default>1</default><!-- DEEP --> + </attribute> + <attribute><id>PM_SAFE_FREQUENCY</id> + <default>3200</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <default>2000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + <default>2300</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + <default>3000</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + <default>3050</default> + </attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + <default>4800</default> + </attribute> + <attribute><id>PM_SPIPSS_FREQUENCY</id> + <default>10</default> + </attribute> + <attribute><id>PM_APSS_CHIP_SELECT</id> + <default>0x00</default><!-- CS0 --> + </attribute> + <attribute><id>PM_PBAX_NODEID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_CHIPID</id> + <default>0</default> + </attribute> + <attribute><id>PM_PBAX_BRDCST_ID_VECTOR</id> + <default>0</default> + </attribute> + <!-- End pm_attributes_all_plat.xml --> </targetInstance> diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 3ce48084a..a64bc44d9 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -124,6 +124,13 @@ <attribute><id>L3_W_EPS</id></attribute> <attribute><id>NOMINAL_FREQ_MHZ</id></attribute> <attribute><id>MNFG_FLAGS</id></attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_R_LOADLINE</id></attribute> + <attribute><id>PROC_R_DISTLOSS</id></attribute> + <attribute><id>PROC_VRM_VOFFSET</id></attribute> + <attribute><id>FREQ_CORE_MAX</id></attribute> + <attribute><id>PROC_DPLL_DIVIDER</id></attribute> + <!-- End pm_attributes_all_plat.xml --> </targetType> <targetType> @@ -227,6 +234,103 @@ <attribute><id>SLW_IMAGE_SIZE</id></attribute> <attribute><id>MSS_INTERLEAVE_ENABLE</id></attribute> <attribute><id>MSS_MCS_GROUP_32</id></attribute> + <!-- Start pm_attributes_all_plat.xml --> + <attribute><id>PROC_DCM_INSTALLED</id></attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id></attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id></attribute> + <attribute><id>PM_SAFE_VOLTAGE</id></attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id></attribute> + <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id></attribute> + <attribute><id>PM_SPIVID_FREQUENCY</id></attribute> + <attribute><id>PM_SPIVID_PORT_ENABLE</id></attribute> + <attribute><id>PM_SLEEP_ENTRY</id></attribute> + <attribute><id>PM_SLEEP_EXIT</id></attribute> + <attribute><id>PM_SLEEP_TYPE</id></attribute> + <attribute><id>PM_WINKLE_ENTRY</id></attribute> + <attribute><id>PM_WINKLE_EXIT</id></attribute> + <attribute><id>PM_WINKLE_TYPE</id></attribute> + <attribute><id>PM_SAFE_FREQUENCY</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id></attribute> + <attribute><id>PM_SPIPSS_FREQUENCY</id></attribute> + <attribute><id>PM_APSS_CHIP_SELECT</id></attribute> + <attribute><id>PM_PBAX_NODEID</id></attribute> + <attribute><id>PM_PBAX_CHIPID</id></attribute> + <attribute><id>PM_PBAX_BRDCST_ID_VECTOR</id></attribute> + <!-- End pm_attributes_all_plat.xml --> + <!-- Start pm_attributes_all_hwp.xml --> + <attribute><id>PM_POWER_PROXY_TRACE_TIMER</id></attribute> + <attribute><id>PM_PPT_TIMER_MATCH_VALUE</id></attribute> + <attribute><id>PM_PPT_TIMER_TICK</id></attribute> + <attribute><id>PM_AISS_TIMEOUT</id></attribute> + <attribute><id>PM_PSTATE_STEPSIZE</id></attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY_RANGE</id></attribute> + <attribute><id>PM_EXTERNAL_VRM_STEPDELAY_VALUE</id></attribute> + <attribute><id>PM_PMC_HANGPULSE_DIVIDER</id></attribute> + <attribute><id>PM_PVSAFE_PSTATE</id></attribute> + <attribute><id>PM_SPIVID_FRAME_SIZE</id></attribute> + <attribute><id>PM_SPIVID_IN_DELAY_FRAME1</id></attribute> + <attribute><id>PM_SPIVID_IN_DELAY_FRAME2</id></attribute> + <attribute><id>PM_SPIVID_CLOCK_POLARITY</id></attribute> + <attribute><id>PM_SPIVID_CLOCK_PHASE</id></attribute> + <attribute><id>PM_SPIVID_CLOCK_DIVIDER</id></attribute> + <attribute><id>PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS</id></attribute> + <attribute><id>PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE</id></attribute> + <attribute><id>PM_SPIVID_INTER_RETRY_DELAY_VALUE</id></attribute> + <attribute><id>PM_SPIVID_INTER_RETRY_DELAY</id></attribute> + <attribute><id>PM_SPIVID_CRC_GEN_ENABLE</id></attribute> + <attribute><id>PM_SPIVID_CRC_CHECK_ENABLE</id></attribute> + <attribute><id>PM_SPIVID_MAJORITY_VOTE_ENABLE</id></attribute> + <attribute><id>PM_SPIVID_MAX_RETRIES</id></attribute> + <attribute><id>PM_SPIVID_CRC_POLYNOMIAL_ENABLES</id></attribute> + <attribute><id>PM_OCC_HEARTBEAT_TIME</id></attribute> + <attribute><id>PM_SLEEP_WINKLE_REQUEST_TIMEOUT</id></attribute> + <attribute><id>PM_PFET_POWERUP_CORE_DELAY0</id></attribute> + <attribute><id>PM_PFET_POWERUP_CORE_DELAY1</id></attribute> + <attribute><id>PM_PFET_POWERUP_CORE_DELAY0_VALUE</id></attribute> + <attribute><id>PM_PFET_POWERUP_CORE_DELAY1_VALUE</id></attribute> + <attribute><id>PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT</id></attribute> + <attribute><id>PM_PFET_POWERDOWN_CORE_DELAY0</id></attribute> + <attribute><id>PM_PFET_POWERDOWN_CORE_DELAY1</id></attribute> + <attribute><id>PM_PFET_POWERDOWN_CORE_DELAY0_VALUE</id></attribute> + <attribute><id>PM_PFET_POWERDOWN_CORE_DELAY1_VALUE</id></attribute> + <attribute><id>PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT</id></attribute> + <attribute><id>PM_PFET_POWERUP_ECO_DELAY0</id></attribute> + <attribute><id>PM_PFET_POWERUP_ECO_DELAY1</id></attribute> + <attribute><id>PM_PFET_POWERUP_ECO_DELAY0_VALUE</id></attribute> + <attribute><id>PM_PFET_POWERUP_ECO_DELAY1_VALUE</id></attribute> + <attribute><id>PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT</id></attribute> + <attribute><id>PM_PFET_POWERDOWN_ECO_DELAY0</id></attribute> + <attribute><id>PM_PFET_POWERDOWN_ECO_DELAY1</id></attribute> + <attribute><id>PM_PFET_POWERDOWN_ECO_DELAY0_VALUE</id></attribute> + <attribute><id>PM_PFET_POWERDOWN_ECO_DELAY1_VALUE</id></attribute> + <attribute><id>PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</id></attribute> + <attribute><id>PM_PSTATE0_FREQUENCY</id></attribute> + <attribute><id>PM_IVRMS_ENABLED</id></attribute> + <attribute><id>PM_SAFE_PSTATE</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_ENABLE</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CSB_PSTATE</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_LFRLOW_PSTATE</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_LFRUPPER_PSTATE</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_HFRLOW_PSTATE</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_HFRHIGH_PSTATE</id></attribute> + <attribute><id>PM_SPIPSS_FRAME_SIZE</id></attribute> + <attribute><id>PM_SPIPSS_OUT_COUNT</id></attribute> + <attribute><id>PM_SPIPSS_IN_DELAY</id></attribute> + <attribute><id>PM_SPIPSS_IN_COUNT</id></attribute> + <attribute><id>PM_SPIPSS_CLOCK_POLARITY</id></attribute> + <attribute><id>PM_SPIPSS_CLOCK_PHASE</id></attribute> + <attribute><id>PM_SPIPSS_CLOCK_DIVIDER</id></attribute> + <attribute><id>PM_SPIPSS_INTER_FRAME_DELAY_SETTING</id></attribute> + <attribute><id>PM_SPIPSS_INTER_FRAME_DELAY</id></attribute> + <attribute><id>PM_PBAX_RCV_RESERV_TIMEOUT</id></attribute> + <attribute><id>PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE</id></attribute> + <attribute><id>PM_PBAX_SND_RETRY_THRESHOLD</id></attribute> + <attribute><id>PM_PBAX_SND_RESERV_TIMEOUT</id></attribute> + <!-- End pm_attributes_all_hwp.xml --> </targetType> <targetType> @@ -323,6 +427,11 @@ <id>TYPE</id> <default>EX</default> </attribute> + <!-- Start pm_attributes_all_hwp.xml --> + <attribute><id>PM_SPWUP_FSP</id></attribute> + <attribute><id>PM_SPWUP_OCC</id></attribute> + <attribute><id>PM_SPWUP_PHYP</id></attribute> + <!-- End pm_attributes_all_hwp.xml --> </targetType> <targetType> diff --git a/src/usr/targeting/common/xmltohb/xmltohb.pl b/src/usr/targeting/common/xmltohb/xmltohb.pl index 3ea0493d9..f09d6c5d7 100755 --- a/src/usr/targeting/common/xmltohb/xmltohb.pl +++ b/src/usr/targeting/common/xmltohb/xmltohb.pl @@ -275,6 +275,7 @@ sub validateSubElements { if($mustBeHash && (ref($element) ne "HASH")) { + print "name=$name, mustBeHash=$mustBeHash, element=$element, criteria=$criteria \n"; fatal("$name must be in the form of a hash."); } @@ -285,7 +286,7 @@ sub validateSubElements { if(!exists $criteria->{$subElementName}) { fatal("$name element cannot have child element of type " - . "\"$subElementName\"."); + . "\"$subElementName\"."); } } @@ -295,15 +296,15 @@ sub validateSubElements { && (!exists $element->{$subElementName})) { fatal("$name element missing required child element " - . "\"$subElementName\"."); + . "\"$subElementName\"."); } if(exists $element->{$subElementName} - && ($criteria->{$subElementName}{isscalar} == 1) - && (ref ($element->{$subElementName}) eq "HASH")) + && ($criteria->{$subElementName}{isscalar} == 1) + && (ref ($element->{$subElementName}) eq "HASH")) { fatal("$name element child element \"$subElementName\" should be " - . "scalar, but is a hash."); + . "scalar, but is a hash."); } } } |
