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| author | Matt Ploetz <maploetz@us.ibm.com> | 2013-11-21 14:17:02 -0600 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-12-05 13:58:10 -0600 |
| commit | 19e7d1f341072a158c3c30f8fe726cdbb1c7ed65 (patch) | |
| tree | 63120481fb9698a97bee277533d4dee7a1b6fc34 /src/usr | |
| parent | 957f80f13030fb90f6c9f31777d5daf1fed5f050 (diff) | |
| download | talos-hostboot-19e7d1f341072a158c3c30f8fe726cdbb1c7ed65.tar.gz talos-hostboot-19e7d1f341072a158c3c30f8fe726cdbb1c7ed65.zip | |
INITPROC: Hostboot - SW234032 HWP ABUS/DMI/Centaur custom scom initfile
Change-Id: Ibebe737e1fa1536d3183350ea0bd36836c24898e
CMVC-Coreq: 907696
CQ: SW234032
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/7380
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr')
3 files changed, 40 insertions, 12 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile index a15860f49..1a4396b12 100644 --- a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile @@ -1,8 +1,9 @@ -#-- $Id: cen.dmi.custom.scom.initfile,v 1.15 2013/09/24 20:22:33 jgrell Exp $ +#-- $Id: cen.dmi.custom.scom.initfile,v 1.16 2013/10/28 21:59:47 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.16|jgrell |10/28/13|Re-enabled recal bits for DD2+ hw #-- 1.15|jgrell |09/24/13|Changed "1" expression to "any" #-- 1.13|jgrell |09/17/13|Added DD2 specific inits #-- 1.11|jgrell |09/12/13|Re-added "Override" scoms @@ -323,9 +324,9 @@ scom_data; scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { bits, scom_data, expr; -rx_rc_enable_dfe_h1_cal, 0b0, any; #ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE==0 || ATTR_DMI_DFE_OVERRIDE==1; -rx_rc_enable_ddc, 0b0, any; #ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0; -rx_rc_enable_ctle_cal, 0b0, any; #ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0; +rx_rc_enable_dfe_h1_cal, 0b0, ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE==0 || ATTR_DMI_DFE_OVERRIDE==1; +rx_rc_enable_ddc, 0b0, ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0; +rx_rc_enable_ctle_cal, 0b0, ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0; rx_rc_enable_h1ap_tweak, 0b0, ATTR_DMI_DFE_OVERRIDE==1; } @@ -373,6 +374,17 @@ scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { rx_ds_timeout_sel_dd2, 0b110, ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1; } +#--************************************************************************************************************** +#---------------------------------------------------------------------------------------------------------------- +# Power Down Unused Lanes +#---------------------------------------------------------------------------------------------------------------- +#--************************************************************************************************************** + +scom 0x800.0b(rx_mode_pl)(rx_grp0)(lane_17).0x(cn_gcr_addr) { +bits, scom_data; +rx_lane_pdwn, 0b1; +} + ############################################################################################ # END OF FILE ############################################################################################ diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile index d1eaecabd..09415992d 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile @@ -1,8 +1,9 @@ -#-- $Id: p8.abus.custom.scom.initfile,v 1.8 2013/09/24 20:20:19 jgrell Exp $ +#-- $Id: p8.abus.custom.scom.initfile,v 1.9 2013/10/28 21:59:13 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.9 |jgrell |10/28/13|Re-enabled recal bits for DD2+ hw #-- 1.8 |jgrell |09/24/13|Changed "1" expression to "any" #-- 1.6 |jgrell |09/17/13|Added DD2 specific inits #-- 1.4 |jgrell |06/18/13|Added Venice specific PRBS tap IDs due to common initfile @@ -302,12 +303,26 @@ scom 0x800.0b(tx_mode_pg)(tx_grp0)(lane_na).0x(abus_gcr_addr) { scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) { bits, scom_data, expr; -rx_rc_enable_dfe_h1_cal, 0b0, any; #temp for DD2 testing. Previously --> TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE==0; -rx_rc_enable_ddc, 0b0, any; #temp for DD2 testing. Previously --> TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0; -rx_rc_enable_ctle_cal, 0b0, any; #temp for DD2 testing. Previously --> TGT1.ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0; +rx_rc_enable_dfe_h1_cal, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE==0; +rx_rc_enable_ddc, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0; +rx_rc_enable_ctle_cal, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0; } +#--************************************************************************************************************** +#---------------------------------------------------------------------------------------------------------------- +# Power Down Unused Lanes +#---------------------------------------------------------------------------------------------------------------- +#--************************************************************************************************************** +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_23).0x(abus_gcr_addr) { +bits, scom_data; +tx_lane_pdwn, 0b1; +} + +scom 0x800.0b(rx_mode_pl)(rx_grp0)(lane_23).0x(abus_gcr_addr) { +bits, scom_data; +rx_lane_pdwn, 0b1; +} #--************************************************************************************************************** #---------------------------------------------------------------------------------------------------------------- diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile index b4bf58914..78f620bdb 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile @@ -1,8 +1,9 @@ -#-- $Id: p8.dmi.custom.scom.initfile,v 1.17 2013/09/24 20:20:35 jgrell Exp $ +#-- $Id: p8.dmi.custom.scom.initfile,v 1.18 2013/10/28 21:59:13 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.18|jgrell |10/28/13|Re-enabled recal bits for DD2+ hw #-- 1.17|jgrell |09/24/13|Changed "1" expression to "any" #-- 1.15|jgrell |09/17/13|Added DD2 specific inits #-- 1.13|jgrell |09/12/13|Re-added "Override" settings @@ -266,9 +267,9 @@ scom 0x800.0b(tx_mode_pg)(tx_grp3)(lane_na).0x(dmi0_gcr_addr) { scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { bits, scom_data, expr; -rx_rc_enable_dfe_h1_cal, 0b0, any; #temp for DD2 testing. Previously --> TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE==0 || ATTR_DMI_DFE_OVERRIDE==1; -rx_rc_enable_ddc, 0b0, any; #temp for DD2 testing. Previously --> TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0; -rx_rc_enable_ctle_cal, 0b0, any; #temp for DD2 testing. Previously --> TGT1.ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0; +rx_rc_enable_dfe_h1_cal, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE==0 || ATTR_DMI_DFE_OVERRIDE==1; +rx_rc_enable_ddc, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0; +rx_rc_enable_ctle_cal, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0; rx_rc_enable_h1ap_tweak, 0b0, ATTR_DMI_DFE_OVERRIDE==1; } |
