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| author | Dan Crowell <dcrowell@us.ibm.com> | 2018-12-06 19:24:50 -0600 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2019-04-02 16:45:23 -0500 |
| commit | 54178321414bc23e827940c120e6759265d33385 (patch) | |
| tree | c2b1dfdaa1b13076cadeb01001feaddc5c1cc1e3 /src/usr/vpd | |
| parent | 9882fe3c773b6843668fa5bc468d2a54252a420d (diff) | |
| download | talos-hostboot-54178321414bc23e827940c120e6759265d33385.tar.gz talos-hostboot-54178321414bc23e827940c120e6759265d33385.zip | |
Constants for future DIMMs
Just adding a few constants to indentify future DIMMs.
Change-Id: Ib3bdf01c918162f0753458236c0c45a4b6e55274
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70075
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Matthew Raybuck <matthew.raybuck@ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/usr/vpd')
| -rwxr-xr-x | src/usr/vpd/spd.H | 2 | ||||
| -rwxr-xr-x | src/usr/vpd/spdDDR4.H | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/usr/vpd/spd.H b/src/usr/vpd/spd.H index a1d1d12cc..edf7d74c7 100755 --- a/src/usr/vpd/spd.H +++ b/src/usr/vpd/spd.H @@ -82,6 +82,7 @@ enum MOD_TYPE_DDR4_MINI_UDIMM = 0x06, MOD_TYPE_DDR4_SO_RDIMM = 0x08, MOD_TYPE_DDR4_SO_UDIMM = 0x09, + MOD_TYPE_DDIMM = 0x0A, DIMM_SPD_SECTION_SIZE = 0x200, // Size each DIMM SPD section DIMM_SPD_MAX_SECTIONS = 512, // Maximum number of sections @@ -98,6 +99,7 @@ typedef enum RMM = 0x02, // Registered Memory Modules CMM = 0x04, // Clocked Memory Modules LRMM = 0x08, // Load Reduction Memory Modules + DDIMM = 0x0A, ALL = 0xFFFF, } modSpecTypes_t; diff --git a/src/usr/vpd/spdDDR4.H b/src/usr/vpd/spdDDR4.H index 8e03a0f0d..0d732fa92 100755 --- a/src/usr/vpd/spdDDR4.H +++ b/src/usr/vpd/spdDDR4.H @@ -103,6 +103,7 @@ const KeywordData ddr4Data[] = { TRCDMIN_FINE_OFFSET, 0x7a, 0x01, 0x00, 0x00, false, false, NA }, { TRPMIN_FINE_OFFSET, 0x79, 0x01, 0x00, 0x00, false, false, NA }, { TRCMIN_FINE_OFFSET, 0x78, 0x01, 0x00, 0x00, false, false, NA }, + // Note - All data below 128 is common across all DDR4 DIMMs, even DDIMM { MODULE_TYPE_SPECIFIC_SECTION, 0x80, 0x80, 0x00, 0x00, false, false, NA }, { MODULE_MANUFACTURER_ID, 0x141, 0x02, 0x00, 0x00, true, false, NA }, { MODULE_MANUFACTURING_LOCATION, 0x142, 0x01, 0x00, 0x00, false, false, NA }, |
