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| author | Mike Jones <mjjones@us.ibm.com> | 2013-07-13 20:38:58 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-07-24 11:16:47 -0500 |
| commit | 3f55e4bc9de4a652958a319747c546a6ee752dba (patch) | |
| tree | 5c2eeb3ce6d9173e9b8bbd0e42ff19f2c362dd47 /src/usr/vpd/spdDDR3.H | |
| parent | a2ce42447c1d70dc7090643055d0e28c411c8314 (diff) | |
| download | talos-hostboot-3f55e4bc9de4a652958a319747c546a6ee752dba.tar.gz talos-hostboot-3f55e4bc9de4a652958a319747c546a6ee752dba.zip | |
Minor SPD Parser fixes
Brent Wieman spotted some differences between the DDR3 parser output
after DDR4 support was added. Investigation led to these fixes. None
of these errors have any functional effect right now because the
fields in question are not currently used.
Change-Id: I93894eeb19d4bd748ed7ba6131bdd54fb201fa02
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5397
Tested-by: Jenkins Server
Reviewed-by: William H. Schwartz <whs@us.ibm.com>
Reviewed-by: Donald E. Dahle <dedahle@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/vpd/spdDDR3.H')
| -rw-r--r-- | src/usr/vpd/spdDDR3.H | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/usr/vpd/spdDDR3.H b/src/usr/vpd/spdDDR3.H index e7c701ca8..a8919109a 100644 --- a/src/usr/vpd/spdDDR3.H +++ b/src/usr/vpd/spdDDR3.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2013 */ /* */ /* p1 */ /* */ @@ -108,7 +108,6 @@ const KeywordData ddr3Data[] = { MODULE_MANUFACTURING_DATE, 0x78, 0x02, 0x00, 0x00, false, false, NA }, { MODULE_SERIAL_NUMBER, 0x7a, 0x04, 0x00, 0x00, false, false, NA }, { MODULE_PART_NUMBER, 0x80, 0x12, 0x00, 0x00, false, false, NA }, - { MODULE_REVISION_CODE, 0x92, 0x02, 0x00, 0x00, true, false, NA }, { DRAM_MANUFACTURER_ID, 0x95, 0x02, 0x00, 0x00, true, false, NA }, { MANUFACTURER_SPECIFIC_DATA, 0x96, 0x1a, 0x00, 0x00, false, false, NA }, { DIMM_BAD_DQ_DATA, 0xb0, 0x50, 0x00, 0x00, false, true, NA }, @@ -133,7 +132,8 @@ const KeywordData ddr3Data[] = { ASR, 0x1f, 0x01, 0x04, 0x02, false, false, NA }, { ETR_1X, 0x1f, 0x01, 0x02, 0x01, false, false, NA }, { ETR, 0x1f, 0x01, 0x01, 0x00, false, false, NA }, - { MODULE_CRC, 0x7e, 0x02, 0x00, 0x00, true, false, NA }, + { MODULE_CRC, 0x7f, 0x02, 0x00, 0x00, true, false, NA }, + { MODULE_REVISION_CODE, 0x93, 0x02, 0x00, 0x00, true, false, NA }, // Module Specific fields supported on both DDR3 and DDR4 { MODSPEC_COM_NOM_HEIGHT_MAX, 0x3c, 0x01, 0x1f, 0x00, false, false, ALL }, { MODSPEC_COM_MAX_THICK_BACK, 0x3d, 0x01, 0xf0, 0x04, false, false, ALL }, @@ -173,10 +173,10 @@ const KeywordData ddr3Data[] = { RMM_RC14, 0x4c, 0x01, 0x0f, 0x00, false, false, RMM }, { LRMM_RANK_NUMBERING, 0x3f, 0x01, 0x20, 0x05, false, false, LRMM }, { LRMM_MEMBUF_ORIEN, 0x3f, 0x01, 0x10, 0x04, false, false, LRMM }, - { LRMM_F0RC3_FORC2, 0x43, 0x01, 0x00, 0x00, false, false, LRMM }, + { LRMM_F0RC3_F0RC2, 0x43, 0x01, 0x00, 0x00, false, false, LRMM }, { LRMM_F0RC3, 0x43, 0x01, 0xf0, 0x04, false, false, LRMM }, { LRMM_F0RC2, 0x43, 0x01, 0x0f, 0x00, false, false, LRMM }, - { LRMM_F0RC5_FORC4, 0x44, 0x01, 0x00, 0x00, false, false, LRMM }, + { LRMM_F0RC5_F0RC4, 0x44, 0x01, 0x00, 0x00, false, false, LRMM }, { LRMM_F0RC5, 0x44, 0x01, 0xf0, 0x04, false, false, LRMM }, { LRMM_F0RC4, 0x44, 0x01, 0x0f, 0x00, false, false, LRMM }, { LRMM_F1RC11_F1RC8, 0x45, 0x01, 0x00, 0x00, false, false, LRMM }, |
