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authorMike Baiocchi <mbaiocch@us.ibm.com>2017-12-06 07:08:01 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-12-12 17:05:15 -0500
commit8fcdfa14a7d3e8615f08c398bec2ee0b7a8d119e (patch)
tree6e451e32e74b77daa524512213d7d0bd94a18655 /src/usr/util
parenta6d6b5da3da48be85bedacfb2732a3760b35445c (diff)
downloadtalos-hostboot-8fcdfa14a7d3e8615f08c398bec2ee0b7a8d119e.tar.gz
talos-hostboot-8fcdfa14a7d3e8615f08c398bec2ee0b7a8d119e.zip
Support Verifying and Moving PAYLOAD and HDAT when TCEs are Enabled
This commit makes changes in istep 16 to set up temporary memory regions that the FSP will use to DMA-via-TCEs the PAYLOAD and HDAT sections into memory in istep 20. Then in istep 21 Hostboot will verify and move these sections to the final memory locations. Change-Id: I3c9e026a8e2c3c40008364c4229915b4a661d0fe RTC:181900 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50624 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com> Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/util')
-rw-r--r--src/usr/util/utillidmgr.C53
-rw-r--r--src/usr/util/utilmclmgr.C7
-rw-r--r--src/usr/util/utiltcemgr.C153
-rw-r--r--src/usr/util/utiltcemgr.H56
4 files changed, 204 insertions, 65 deletions
diff --git a/src/usr/util/utillidmgr.C b/src/usr/util/utillidmgr.C
index 7f94c50ed..d69d02d0b 100644
--- a/src/usr/util/utillidmgr.C
+++ b/src/usr/util/utillidmgr.C
@@ -35,6 +35,7 @@
#include "utilbase.H"
#include <initservice/initserviceif.H>
#include <sys/mm.h>
+#include <util/align.H>
#include <config.h>
#ifdef CONFIG_SECUREBOOT
@@ -112,7 +113,6 @@ errlHndl_t UtilLidMgr::getLidSize(size_t& o_lidSize)
//ask the FSP for it.
//Send message to FSP asking for info on the current LID.
-
// allocate message buffer
// buffer will be initialized to zero by msg_allocate()
if (iv_spBaseServicesEnabled)
@@ -353,8 +353,12 @@ errlHndl_t UtilLidMgr::getLid(void* i_dest, size_t i_destSize)
uint8_t* dataPtr = nullptr;
void* copyOffset = nullptr;
bool img_in_pnor = false;
+ bool use_tces = 0;
bool tces_allocated = false;
uint32_t tceToken = 0;
+ uint32_t dmaAddr = 0;
+ void* tceStartAddr = nullptr;
+ uint64_t tceSize = 0;
do{
//////////////////////////////////////////////////
@@ -371,12 +375,34 @@ errlHndl_t UtilLidMgr::getLid(void* i_dest, size_t i_destSize)
//Image not in PNOR, request from FSP.
if(iv_spBaseServicesEnabled)
{
+ use_tces = TCE::utilUseTcesForDmas();
+
// If using TCEs, setup TCE Table for FSP to use
- if (TCE::utilUseTcesForDmas())
+ if (use_tces)
{
- // Use Preverification Location and Size
- errl = TCE::utilAllocateTces(MCL_TMP_ADDR,
- MCL_TMP_SIZE,
+ // Assume caller passed in Virtual Address that was already
+ // backed to Physical Memory
+ UTIL_FT("getLid: requesting TCEs for i_dest=0x%.16llX, i_destSize=0x%X (lidId=0x%X)", i_dest, i_destSize, iv_lidId);
+
+ // Need to Allocate TCEs on Page-Aligned Memory
+ size_t i_dest_remainder = reinterpret_cast<uint64_t>(i_dest)
+ % PAGESIZE;
+
+ if (i_dest_remainder != 0)
+ {
+ tceStartAddr = reinterpret_cast<void*>(
+ ALIGN_PAGE_DOWN(reinterpret_cast<uint64_t>(i_dest)));
+ tceSize = i_destSize + i_dest_remainder;
+ UTIL_DT("getLid: requesting non-page-aligned i_dest (%p): adjusted TCE tceStartAddr = %p, tceSize=0x%X", i_dest, tceStartAddr, tceSize);
+ }
+ else
+ {
+ tceStartAddr = i_dest;
+ tceSize = i_destSize;
+ }
+
+ errl = TCE::utilAllocateTces(mm_virt_to_phys(tceStartAddr),
+ tceSize,
tceToken);
if(errl)
{
@@ -384,6 +410,10 @@ errlHndl_t UtilLidMgr::getLid(void* i_dest, size_t i_destSize)
break;
}
tces_allocated = true;
+
+ // Update dmaAddr that FSP needs to use, if necessary
+ dmaAddr = tceToken + i_dest_remainder;
+ UTIL_DT("getLid: got back tceToken=0x%.16llX. DMA_Addr=0x%.16llX", tceToken, dmaAddr);
}
errl = createMsgQueue();
@@ -402,7 +432,7 @@ errlHndl_t UtilLidMgr::getLid(void* i_dest, size_t i_destSize)
UTILLID_ADD_LID_ID( iv_lidId, l_pMsg->data[0] );
UTILLID_ADD_HEADER_FLAG( 0 , l_pMsg->data[0] );
- UTILLID_ADD_TCE_TOKEN( tceToken , l_pMsg->data[1] );
+ UTILLID_ADD_TCE_TOKEN( dmaAddr , l_pMsg->data[1] );
errl = sendMboxMessage( SYNCHRONOUS, l_pMsg );
if(errl)
@@ -444,6 +474,13 @@ errlHndl_t UtilLidMgr::getLid(void* i_dest, size_t i_destSize)
break;
}
+ // In TCE Mode FSP DMAs the entire LID before returning synchronus
+ // message above with the SEND_TO_HB message type
+ if (use_tces && (l_pMsg->type == UTILLID::SEND_TO_HB))
+ {
+ UTIL_DT("getLid: Using TCEs and got back UTILLID::SEND_TO_HB: transfer complete");
+ break;
+ }
//Now wait for FSP to send the LID page-by-page.
do{
@@ -563,7 +600,6 @@ errlHndl_t UtilLidMgr::getLid(void* i_dest, size_t i_destSize)
}
}while(transferred_data < iv_lidSize);
-
}
if(errl)
{
@@ -576,7 +612,7 @@ errlHndl_t UtilLidMgr::getLid(void* i_dest, size_t i_destSize)
{
// Use Preverification Location and Size
auto tce_errl = TCE::utilDeallocateTces(tceToken,
- MCL_TMP_SIZE);
+ tceSize);
if(tce_errl)
{
@@ -592,6 +628,7 @@ errlHndl_t UtilLidMgr::getLid(void* i_dest, size_t i_destSize)
{
// Set errl to tce_errl
errl = tce_errl;
+ tce_errl = nullptr;
}
}
}
diff --git a/src/usr/util/utilmclmgr.C b/src/usr/util/utilmclmgr.C
index 66c3b1a29..81e1c8cff 100644
--- a/src/usr/util/utilmclmgr.C
+++ b/src/usr/util/utilmclmgr.C
@@ -328,7 +328,6 @@ void MasterContainerLidMgr::printCompInfoCache()
errlHndl_t MasterContainerLidMgr::processComponents()
{
errlHndl_t l_errl = nullptr;
-
for (auto & compInfoPair : iv_compInfoCache)
{
// Skip the MCL itself as it's already been processed
@@ -377,7 +376,11 @@ errlHndl_t MasterContainerLidMgr::processComponent(const ComponentID& i_compId,
{
// Skip loading, but still process POWERVM (PHYP) component
l_skipLoad = true;
- UTIL_FT("MasterContainerLidMgr::processComponent skip load but processing POWERVM component");
+
+ // @TODO RTC 168745 - Handle POWERVM Correctly
+ // UTIL_FT("MasterContainerLidMgr::processComponent skip load but processing POWERVM component");
+ UTIL_FT("MasterContainerLidMgr::processComponent - skip loading and processing of POWERVM component");
+ break;
}
else
{
diff --git a/src/usr/util/utiltcemgr.C b/src/usr/util/utiltcemgr.C
index 01f2bf7e6..2424ee686 100644
--- a/src/usr/util/utiltcemgr.C
+++ b/src/usr/util/utiltcemgr.C
@@ -54,6 +54,7 @@ TRAC_INIT(&g_trac_tce, UTILTCE_TRACE_NAME, 4*KILOBYTE);
// ------------------------
// Macros for unit testing - leave extra trace enabled for now
+// @TODO RTC 168745 - Disable TRACUCOMP as the default
#define TRACUCOMP(args...) TRACFCOMP(args)
//#define TRACUCOMP(args...)
@@ -64,13 +65,10 @@ namespace TCE
/************************************************************************/
// Defines
/************************************************************************/
-// @TODO RTC 168745 Currently hardcoded to 128MB when the original plan was
-// to use PNOR payloadInfo.size, but that only was 19MB
-#define TCE_PAYLOAD_SIZE (128*MEGABYTE)
-
// TCE Table Address must be 4MB Aligned
#define TCE_TABLE_ADDRESS_ALIGNMENT (4*MEGABYTE)
+
/************************************************************************/
// External Interface:
// NAME: utilAllocateTces
@@ -123,22 +121,6 @@ UtilTceMgr& getTceManager(void)
return Singleton<UtilTceMgr>::instance();
};
-/***********************************************************************************/
-/* Local function to get PAYLOAD base address and size */
-/***********************************************************************************/
-errlHndl_t getPayloadAddrAndSize(uint64_t& o_addr, size_t& o_size)
-{
- errlHndl_t errl = nullptr;
-
- // Move PAYLOAD to Preverification Location
- o_addr = MCL_TMP_ADDR;
- o_size = MCL_TMP_SIZE;
-
- TRACFCOMP( g_trac_tce,EXIT_MRK"getPayloadAddrAndSize(): o_addr=0x%.16llX, o_size=0x%.16llX", o_addr, o_size);
-
- return errl;
-}
-
errlHndl_t utilSetupPayloadTces(void)
{
errlHndl_t errl = nullptr;
@@ -149,24 +131,24 @@ errlHndl_t utilSetupPayloadTces(void)
do{
- TRACFCOMP(g_trac_tce,ENTER_MRK"utilSetupPayloadTces(): get Address and Size");
+ TRACFCOMP(g_trac_tce,ENTER_MRK"utilSetupPayloadTces()");
- errl = getPayloadAddrAndSize(addr, size);
+ // Allocate TCEs for PAYLOAD to Temporary Space
+ addr = MCL_TMP_ADDR;
+ size = MCL_TMP_SIZE;
+ errl = utilAllocateTces(addr, size, token);
if (errl)
{
- TRACFCOMP(g_trac_tce,"utilSetupPayloadTces(): ERROR back from getPayloadAddrAndSize()");
+ TRACFCOMP(g_trac_tce,"utilSetupPayloadTces(): ERROR back from utilAllocateTces() for PAYLOAD using addr=0x%.16llX, size=0x%llX", addr, size);
break;
}
-
- errl = utilAllocateTces(addr, size, token);
- if (errl)
+ else
{
- TRACFCOMP(g_trac_tce,"utilSetupPayloadTces(): ERROR back from utilAllocateTces() using addr=0x%.16llX, size=0x%llX", addr, size);
- break;
+ TRACUCOMP(g_trac_tce,"utilSetupPayloadTces(): utilAllocateTces() for PAYLOAD: addr=0x%.16llX, size=0x%llX, token=0x%X", addr, size, token);
}
- // Set attribute to tell FSP that Payload has been setup at the start of the TCE Table
- // Get Target Service and the system target to set TCE_START_TOKEN_FOR_PAYLOAD
+ // Set attribute to tell FSP what the PAYLOAD token is
+ // Get Target Service and the system target to set attributes
TARGETING::TargetService& tS = TARGETING::targetService();
TARGETING::Target* sys = nullptr;
(void) tS.getTopLevelTarget( sys );
@@ -174,9 +156,34 @@ errlHndl_t utilSetupPayloadTces(void)
sys->setAttr<TARGETING::ATTR_TCE_START_TOKEN_FOR_PAYLOAD>(token);
+ // Save for internal use since we can't trust FSP won't change the attribute
+ Singleton<UtilTceMgr>::instance().setToken(UtilTceMgr::PAYLOAD_TOKEN,
+ token);
+
+ // Allocate TCEs for HDAT
+ addr = HDAT_TMP_ADDR;
+ size = HDAT_TMP_SIZE;
+ errl = utilAllocateTces(addr, size, token);
+ if (errl)
+ {
+ TRACFCOMP(g_trac_tce,"utilSetupPayloadTces(): ERROR back from utilAllocateTces() for HDAT using addr=0x%.16llX, size=0x%llX", HDAT_TMP_ADDR, HDAT_TMP_SIZE);
+ break;
+ }
+ else
+ {
+ TRACUCOMP(g_trac_tce,"utilSetupPayloadTces(): utilAllocateTces() for HDAT: addr=0x%.16llX, size=0x%llX, token=0x%X", addr, size, token);
+ }
+
+ // Set attribute to tell FSP what the HDAT token is
+ sys->setAttr<TARGETING::ATTR_TCE_START_TOKEN_FOR_HDAT>(token);
+
+ // Save for internal use since we can't trust FSP won't change the attribute
+ Singleton<UtilTceMgr>::instance().setToken(UtilTceMgr::HDAT_TOKEN,
+ token);
+
} while(0);
- TRACFCOMP(g_trac_tce,EXIT_MRK"utilSetupPayloadTces(): Address=0x%.16llX, size=0x%X, token=0x%.8X, errl_rc=0x%X", addr, size, token, ERRL_GETRC_SAFE(errl));
+ TRACFCOMP(g_trac_tce,EXIT_MRK"utilSetupPayloadTces(): errl_rc=0x%X", ERRL_GETRC_SAFE(errl));
return errl;
}
@@ -185,31 +192,26 @@ errlHndl_t utilClosePayloadTces(void)
{
errlHndl_t errl = nullptr;
- uint64_t addr=0x0;
size_t size=0x0;
uint32_t token=0x0;
do{
- TRACFCOMP(g_trac_tce,ENTER_MRK"utilClosePayloadTces(): get Address and Size");
+ TRACFCOMP(g_trac_tce,ENTER_MRK"utilClosePayloadTces()");
- // Get Payload Address and Size
- errl = getPayloadAddrAndSize(addr, size);
+ // size is a constant for PAYLOAD
+ size = MCL_TMP_SIZE;
+ token = Singleton<UtilTceMgr>::instance().getToken(UtilTceMgr::PAYLOAD_TOKEN);
+ errl = utilDeallocateTces(token, size);
if (errl)
{
- TRACFCOMP(g_trac_tce,"utilClosePayloadTces(): ERROR back from getPayloadAddrAndSize()");
+ TRACFCOMP(g_trac_tce,"utilClosePayloadTces(): ERROR back from utilDeallocateTces() using token=0x%.8X, size=0x%llX", token, size);
break;
}
- // Get Starting Payload Token
- // Get Target Service and the system target to set TCE_START_TOKEN_FOR_PAYLOAD
- TARGETING::TargetService& tS = TARGETING::targetService();
- TARGETING::Target* sys = nullptr;
- (void) tS.getTopLevelTarget( sys );
- assert(sys, "utilSetupPayloadTces() system target is NULL");
-
- token = sys->getAttr<TARGETING::ATTR_TCE_START_TOKEN_FOR_PAYLOAD>();
-
+ // size is a constant for HDAT
+ size = HDAT_TMP_SIZE;
+ token = Singleton<UtilTceMgr>::instance().getToken(UtilTceMgr::HDAT_TOKEN);
errl = utilDeallocateTces(token, size);
if (errl)
{
@@ -217,9 +219,10 @@ errlHndl_t utilClosePayloadTces(void)
break;
}
+
} while(0);
- TRACFCOMP(g_trac_tce,EXIT_MRK"utilClosePayloadTces(): token=0x%.8X, size=0x%X, errl_rc=0x%X", token, size, ERRL_GETRC_SAFE(errl));
+ TRACFCOMP(g_trac_tce,EXIT_MRK"utilClosePayloadTces(): errl_rc=0x%X", ERRL_GETRC_SAFE(errl));
return errl;
}
@@ -238,6 +241,8 @@ UtilTceMgr::UtilTceMgr(const uint64_t i_tableAddr, const size_t i_tableSize)
,iv_tceTablePhysAddr(i_tableAddr)
,iv_tceEntryCount(0)
,iv_tceTableSize(i_tableSize)
+ ,iv_payloadToken(INVALID_TOKEN_VALUE)
+ ,iv_hdatToken(INVALID_TOKEN_VALUE)
{
// Table Address must be 4MB Aligned and default input is TCE_TABLE_ADDR
static_assert( TCE_TABLE_ADDR % TCE_TABLE_ADDRESS_ALIGNMENT == 0,"TCE Table must align on 4 MB boundary");
@@ -767,9 +772,12 @@ errlHndl_t UtilTceMgr::allocateTces(const uint64_t i_startingAddress,
TRACDCOMP(g_trac_tce,INFO_MRK"UtilTceMgr::allocateTces: TCE Entry/Token[%d] (hex) = %llX", index, tablePtr[index]);
}
- iv_allocatedAddrs[startingIndex].start_addr = i_startingAddress;
- iv_allocatedAddrs[startingIndex].size = i_size;
- o_startingToken = startingIndex;
+ // Save And Return Information about Allocated TCEs
+ // Key to this map is the token, which is a DMA address that =
+ // (Starting Index in TCE Table) * PAGESIZE
+ o_startingToken = startingIndex*PAGESIZE;
+ iv_allocatedAddrs[o_startingToken].start_addr = i_startingAddress;
+ iv_allocatedAddrs[o_startingToken].size = i_size;
TRACFCOMP(g_trac_tce,"UtilTceMgr::allocateTces: SUCCESSFUL: addr = 0x%.16llX, size = 0x%llX, starting entry=0x%X",i_startingAddress, i_size, startingIndex);
}
@@ -802,7 +810,7 @@ errlHndl_t UtilTceMgr::allocateTces(const uint64_t i_startingAddress,
}
}while(0);
- TRACFCOMP(g_trac_tce, EXIT_MRK"UtilTceMgr::allocateTces: END: addr = 0x%.16llX and size = 0x%X, numTcesNeeded=0x%X", i_startingAddress, i_size, numTcesNeeded);
+ TRACFCOMP(g_trac_tce, EXIT_MRK"UtilTceMgr::allocateTces: END: addr = 0x%.16llX and size = 0x%X, numTcesNeeded=0x%X. returning o_startingToken=0x%.8X", i_startingAddress, i_size, numTcesNeeded, o_startingToken);
printIvMap(); //Debug
return errl;
@@ -830,6 +838,9 @@ errlHndl_t UtilTceMgr::deallocateTces(const uint32_t i_startingToken,
do
{
+ // Assert if i_startingToken is not aligned on PAGESIZE
+ assert((i_startingToken % PAGESIZE) == 0, "UtilTceMgr::deallocateTces: i_startingToken (0x%.8X) is not page aligned", i_startingToken);
+
// Assert if i_size is not greater than zero
assert(i_size > 0, "UtilTceMgr::deallocateTces: i_size = %d, not greater than zero", i_size);
@@ -847,7 +858,7 @@ errlHndl_t UtilTceMgr::deallocateTces(const uint32_t i_startingToken,
}
else
{
- startingIndex = map_itr->first;
+ startingIndex = (map_itr->first) / PAGESIZE;
startingAddress = map_itr->second.start_addr;
}
TRACUCOMP(g_trac_tce,"UtilTceMgr::deallocateTces: numTcesNeeded=0x%X, startingAddress = 0x%X", numTcesNeeded, startingAddress);
@@ -1258,6 +1269,45 @@ errlHndl_t UtilTceMgr::unmapPsiHostBridge(void *& io_psihb_ptr) const
return errl;
}
+/**************************************************************************/
+//
+// NAME: getToken:
+// Returns one of two internally stored tokens
+//
+/**************************************************************************/
+
+uint32_t UtilTceMgr::getToken(const tokenLabels i_tokenLabel)
+{
+ assert((i_tokenLabel==UtilTceMgr::PAYLOAD_TOKEN)||(i_tokenLabel==UtilTceMgr::HDAT_TOKEN),"UtilTceMgr::getToken bad input parm: 0x%X", i_tokenLabel);
+
+ return (i_tokenLabel==UtilTceMgr::PAYLOAD_TOKEN)
+ ? iv_payloadToken : iv_hdatToken;
+
+}
+
+/**************************************************************************/
+//
+// NAME: setToken:
+// Sets one of two internally stored tokens
+//
+/**************************************************************************/
+void UtilTceMgr::setToken(const tokenLabels i_tokenLabel,
+ const uint32_t i_tokenValue)
+{
+ assert((i_tokenLabel==UtilTceMgr::PAYLOAD_TOKEN)||(i_tokenLabel==UtilTceMgr::HDAT_TOKEN),"UtilTceMgr::setToken bad input parm: 0x%X", i_tokenLabel);
+
+ if (i_tokenLabel==UtilTceMgr::PAYLOAD_TOKEN)
+ {
+ iv_payloadToken = i_tokenValue;
+ }
+ else
+ {
+ iv_hdatToken = i_tokenValue;
+ }
+
+ return;
+}
+
/******************************************************/
/* Miscellaneous Functions */
@@ -1290,6 +1340,7 @@ errlHndl_t utilEnableTcesWithoutTceTable(void)
{
errlHndl_t errl = nullptr;
+ // @TODO RTC 168745 - Update to use Singleton UtilTceMgr
// Create local UtilTceMgr with default TCE table address but with a size
// of zero so that all entries are invalid
// NOTE: memory at TCE Table Address is initialized to 0 as part of IPL and
diff --git a/src/usr/util/utiltcemgr.H b/src/usr/util/utiltcemgr.H
index a4689235c..aabf99d5a 100644
--- a/src/usr/util/utiltcemgr.H
+++ b/src/usr/util/utiltcemgr.H
@@ -120,8 +120,12 @@ class UtilTceMgr
/** size of the Tce Table */
size_t iv_tceTableSize;
+ /** Tokens for PAYLOAD and HDAT entries in the TCE Table */
+ uint32_t iv_payloadToken;
+ uint32_t iv_hdatToken;
+
/* Cache of starting addresses of allocated TCEs and their
- * tokens (starting entry in the TCE Table) and size
+ * tokens ((starting entry in the TCE Table) * PAGESIZE) and size
* Indexed by token - the position of the first entry of the TCE Table
* Returns the starting address and size of the memory allocated by the
* entries in the TCE Table
@@ -146,6 +150,12 @@ class UtilTceMgr
PHBSECURE_TCE_ENABLE = 0x2000000000000000,
};
+ /** Values related to tokens */
+ enum tokenValues : uint32_t
+ {
+ INVALID_TOKEN_VALUE = 0xFFFFFFFF,
+ };
+
/**
* @brief Responsible for initalizing the TCE Table and mapping the
* TCE Table into memory
@@ -240,9 +250,11 @@ class UtilTceMgr
* Size must be less than (512K * PAGESIZE) or will fail
* Assert if not greater than zero
* @param[out] o_startingToken - Starting Entry into the table.
- * (This is an offset into the array based on
- * the TCE index * PAGESIZE. Each TCE entry
- * maps to a pagesize of memory)
+ * @param[out] o_startingToken - Key to the Starting Entry into the table.
+ * This is an offset into the array based on the
+ * TCE Index * PAGESIZE.
+ * FSP uses the token as a DMA Address.
+ * Each TCE entry maps to a pagesize of memory.
*
* Note: First time this is called will cause TCE table to be created and
* the Processors to be setup to point at the TCE table
@@ -287,6 +299,42 @@ class UtilTceMgr
*/
errlHndl_t initTceInHdw();
+
+ /** Values related to tokens */
+ enum tokenLabels
+ {
+ PAYLOAD_TOKEN = 0x0,
+ HDAT_TOKEN = 0x1,
+ };
+
+ /**
+ * @brief Returns one of two internally stored tokens
+ *
+ * @param[in] i_tokenLabel - Specifies which token to return
+ * Assert if neither PAYLOAD_TOKEN nor
+ * HDAT_TOKEN
+ *
+ * @return uint32_t - Return specified token
+ *
+ */
+ uint32_t getToken(tokenLabels i_tokenLabel);
+
+ /**
+ * @brief Sets one of two internally stored tokens
+ *
+ * @param[in] i_tokenLabel - Specifies which token to set
+ * Assert if neither PAYLOAD_TOKEN nor
+ * HDAT_TOKEN
+ *
+ * @param[in] i_tokenValue - Value to be set
+ *
+ * @return uint32_t - Set specified token
+ *
+ */
+ void setToken(tokenLabels i_tokenLabel,
+ uint32_t i_tokenValue);
+
+
}; // class UtilTceMgr
/**
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