Add Functionality To Allow FSP to Enable TCEs For Testing

This commit adds an attribute that the FSP team can use to tell
Hostboot to enable the TCE path for DMAs.  When the FSP sets this
attribute, the hostboot code will initialize the TCE settings.

Change-Id: I24c71f31264645cac5840caad1b59b90fe465fb4
RTC:168745
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48036
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

1 files changed, 9 insertions, 9 deletions

diff --git a/src/usr/util/utiltcemgr.H b/src/usr/util/utiltcemgr.H
index 3f8d2b95c..b77f45023 100644
--- a/src/usr/util/utiltcemgr.H
+++ b/src/usr/util/utiltcemgr.H
@@ -148,15 +148,6 @@ class UtilTceMgr
 
 
     /**
-     * @brief Responsible for setting up the Processors to point to the TCE
-     *         Table
-     *
-     * @return errlHndl_t - Return error log if unsuccessful
-     *
-     */
-    errlHndl_t initTceInHdw();
-
-    /**
      * @brief Helper function to Memory Map PSI Host Bridge
      *
      * @param[in]  i_tgt       Pointer to Processor Target that is associated
@@ -275,6 +266,15 @@ class UtilTceMgr
      */
     errlHndl_t disableTces(void);
 
+    /**
+     * @brief Responsible for setting up the Processors to point to the TCE
+     *         Table
+     *
+     * @return errlHndl_t - Return error log if unsuccessful
+     *
+     */
+    errlHndl_t initTceInHdw();
+
 }; // class UtilTceMgr
 
     /**