Setup INTP bars correctly when memory is swapped on master proc

In the event that no memory is detected behind proc0. We will attempt
to use the memory behind a slave proc instead. When this occurs we
must adjust the interrupt bars to account for this swap

Change-Id: Ib37a190b7a7a2c655440ffd2bad56c351b4d4fa2
RTC: 173527
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40820
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

1 files changed, 67 insertions, 0 deletions

diff --git a/src/usr/targeting/targetservicestart.C b/src/usr/targeting/targetservicestart.C
index 1faae4cee..e1bab1a5a 100755
--- a/src/usr/targeting/targetservicestart.C
+++ b/src/usr/targeting/targetservicestart.C
@@ -497,6 +497,63 @@ static void adjustMemoryMap( TargetService& i_targetService )
             TARG_ASSERT(false,"Mismatch between LPC and XSCOM BARs");
         }
 
+        //Setup Interrupt Related Bars
+        ATTR_PSI_BRIDGE_BASE_ADDR_type l_psiBridgeBAR =
+            computeMemoryMapOffset(MMIO_GROUP0_CHIP0_PSI_BRIDGE_BASE_ADDR,
+                                  l_groupId,
+                                  l_chipId);
+        TARG_INF( " PSI_BRIDGE_BAR =%.16llX", l_psiBridgeBAR );
+        l_procChip->setAttr<ATTR_PSI_BRIDGE_BASE_ADDR>(l_psiBridgeBAR);
+        if( l_swapVictim == l_procChip)
+        {
+            l_swapAttrs[ATTR_PSI_BRIDGE_BASE_ADDR] = l_psiBridgeBAR;
+        }
+
+        ATTR_XIVE_CONTROLLER_BAR_ADDR_type l_xiveCtrlBAR =
+            computeMemoryMapOffset(MMIO_GROUP0_CHIP0_XIVE_CONTROLLER_BASE_ADDR,
+                                   l_groupId,
+                                   l_chipId);
+        TARG_INF( " XIVE_CONTROLLER_BAR =%.16llX", l_xiveCtrlBAR );
+        l_procChip->setAttr<ATTR_XIVE_CONTROLLER_BAR_ADDR>(l_xiveCtrlBAR);
+        if( l_swapVictim == l_procChip)
+        {
+            l_swapAttrs[ATTR_XIVE_CONTROLLER_BAR_ADDR] = l_xiveCtrlBAR;
+        }
+
+        ATTR_XIVE_THREAD_MGMT1_BAR_ADDR_type l_xiveThreadMgmtBAR =
+            computeMemoryMapOffset(MMIO_GROUP0_CHIP0_XIVE_THREAD_MGMT1_BASE_ADDR,
+                                   l_groupId,
+                                   l_chipId);
+        TARG_INF( " XIVE_THREAD_MGMT1_BAR =%.16llX", l_xiveThreadMgmtBAR );
+        l_procChip->setAttr<ATTR_XIVE_THREAD_MGMT1_BAR_ADDR>(l_xiveThreadMgmtBAR);
+        if( l_swapVictim == l_procChip)
+        {
+            l_swapAttrs[ATTR_XIVE_THREAD_MGMT1_BAR_ADDR] = l_xiveThreadMgmtBAR;
+        }
+
+        ATTR_PSI_HB_ESB_ADDR_type l_psiHbEsbBAR =
+            computeMemoryMapOffset(MMIO_GROUP0_CHIP0_PSI_HB_ESB_BASE_ADDR,
+                                   l_groupId,
+                                   l_chipId);
+        TARG_INF( " PSI_HB_ESB_BAR =%.16llX", l_psiHbEsbBAR );
+        l_procChip->setAttr<ATTR_PSI_HB_ESB_ADDR>(l_psiHbEsbBAR);
+        if( l_swapVictim == l_procChip)
+        {
+            l_swapAttrs[ATTR_PSI_HB_ESB_ADDR] = l_psiHbEsbBAR;
+        }
+
+        ATTR_INTP_BASE_ADDR_type l_intpBAR =
+            computeMemoryMapOffset(MMIO_GROUP0_CHIP0_INTP_BASE_ADDR,
+                                   l_groupId,
+                                   l_chipId);
+        TARG_INF( " INTP_BAR =%.16llX", l_intpBAR );
+        l_procChip->setAttr<ATTR_INTP_BASE_ADDR>(l_intpBAR);
+        if( l_swapVictim == l_procChip)
+        {
+            l_swapAttrs[ATTR_INTP_BASE_ADDR] = l_intpBAR;
+        }
+        //finished setting up interrupt bars
+
         // Set the rest of the BARs...
     }
 
@@ -515,6 +572,16 @@ static void adjustMemoryMap( TargetService& i_targetService )
                         l_swapVictim, l_swapAttrs );
         SWAP_ATTRIBUTE( ATTR_LPC_BUS_ADDR, l_pMasterProcChip,
                         l_swapVictim, l_swapAttrs );
+        SWAP_ATTRIBUTE( ATTR_PSI_BRIDGE_BASE_ADDR, l_pMasterProcChip,
+                        l_swapVictim, l_swapAttrs );
+        SWAP_ATTRIBUTE( ATTR_XIVE_CONTROLLER_BAR_ADDR, l_pMasterProcChip,
+                        l_swapVictim, l_swapAttrs );
+        SWAP_ATTRIBUTE( ATTR_XIVE_THREAD_MGMT1_BAR_ADDR, l_pMasterProcChip,
+                        l_swapVictim, l_swapAttrs );
+        SWAP_ATTRIBUTE( ATTR_PSI_HB_ESB_ADDR, l_pMasterProcChip,
+                        l_swapVictim, l_swapAttrs );
+        SWAP_ATTRIBUTE( ATTR_INTP_BASE_ADDR, l_pMasterProcChip,
+                        l_swapVictim, l_swapAttrs );
         // Handle the rest of the BARs...
     }