INITPROC: Hostboot - from defect SW224356 - PSTATE procedures

Change-Id: I5358dab2f24f26054fb004ff980c9fe4638cff6c
CMVC-Coreq:896229
CQ:SW224356
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6446
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

7 files changed, 532 insertions, 261 deletions

diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl
index bb4e89b65..33948af89 100755
--- a/src/usr/targeting/common/genHwsvMrwXml.pl
+++ b/src/usr/targeting/common/genHwsvMrwXml.pl
@@ -1495,15 +1495,6 @@ sub generate_sys
     #todo-RTC:52835
     print "
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PROC_R_LOADLINE</id>
-        <default>890</default>
-    </attribute>
-    <attribute><id>PROC_R_DISTLOSS</id>
-        <default>100</default>
-    </attribute>
-    <attribute><id>PROC_VRM_VOFFSET</id>
-        <default>1000</default>
-    </attribute>
     <attribute><id>FREQ_CORE_MAX</id>
         <default>4000</default>
     </attribute>
@@ -1929,12 +1920,6 @@ sub generate_proc
     #@todo-RTC:52835
     print "
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SLEEP_TYPE</id>
         <default>1</default><!-- DEEP -->
     </attribute>
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 80885d816..7aba1e146 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -4353,52 +4353,6 @@ Divider for the 1us PBAX hang pulse.  A hang is detected after two divided hang
 </attribute>
 
 <attribute>
-    <id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-    <description>
-      PROC_CHIP Attribute
-      Minimum frequency for which undervolting is allowed.  Will be internally
-      rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value.
-
-      Consumer: OCC FW; OCC Lab Tools
-
-      Provided by the Machine Readable Workbook.
-    </description>
-    <simpleType>	
-        <uint8_t></uint8_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-    <description>
-      PROC_CHIP Attribute
-      Maximum frequency for which undervolting is allowed.  Will be internally
-      rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value.
-
-      Consumer: OCC FW; OCC Lab Tools
-
-      Provided by the Machine Readable Workbook.
-    </description>
-    <simpleType>	
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
     <id>PM_SPIVID_FREQUENCY</id>
     <description>
       SYSTEM Attribute
@@ -4684,75 +4638,6 @@ Divider for the 1us PBAX hang pulse.  A hang is detected after two divided hang
 </attribute>
 
 <attribute>
-    <id>PROC_R_LOADLINE</id>
-    <description>
-      SYSTEM Attribute
-      Impedance (binary microOhms) of the load line from a processor VRM to the
-      Processor Module pins.  This value is applied to each processor instance.
-
-      Consumers: proc_build_gpstate_table.C
-
-      Provided by the Machine Readable Workbook (via the power subsystem design
-      per system)
-    </description>
-    <simpleType>	
-        <uint32_t></uint32_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_PROC_R_LOADLINE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>PROC_R_DISTLOSS</id>
-    <description>
-      SYSTEM Attribute
-      Impedance (binary in microOhms) of the distribution loss the sense point
-      to the circuit. This value is applied to each processor instance.
-
-      Consumers: proc_build_gpstate_table.C
-
-      Provided by the Machine Readable Workbook (via the power subsystem design
-      per system)
-    </description>
-    <simpleType>	
-        <uint32_t></uint32_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_PROC_R_DISTLOSS</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>PROC_VRM_VOFFSET</id>
-    <description>
-      SYSTEM Attribute
-      Offset voltage (binary in microvolts) to apply to the VRM distribution to
-      the processor module.  This value is applied to each processor instance.
-
-      Consumers: proc_build_gpstate_table.C
-
-      Provided by the Machine Readable Workbook (via the power subsystem design
-      per system)
-    </description>
-    <simpleType>	
-        <uint32_t></uint32_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_PROC_VRM_VOFFSET</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
     <id>FREQ_CORE_MAX</id>
     <description>
       SYSTEM Attribute
@@ -12303,4 +12188,512 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </hwpfToHbAttrMap>
 </attribute>
 
+<attribute>
+    <id>PROC_VRM_VOFFSET_VDD</id>
+    <description>
+      Offset voltage (binary in microvolts) to apply to the VDD VRM distribution to
+      the processor module.  This value is applied to each processor instance.
+
+      Producer:  Machine Readable Workbook (via the power subsystem design per system)
+
+      Consumer: p8_build_gpstate_table.C
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_VRM_VOFFSET_VDD</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PROC_VRM_VOFFSET_VCS</id>
+    <description>
+      Offset voltage (binary in microvolts) to apply to the VCS VRM distribution to
+      the processor module.  This value is applied to each processor instance.
+
+      Producer:  Machine Readable Workbook (via the power subsystem design per system)
+
+      Consumer: p8_build_gpstate_table.C
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_VRM_VOFFSET_VCS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>CPM_TURBO_BOOST_PERCENT</id>
+    <description>
+     Percent of Boost Above Turbo for CPMs - (binary in 0.1 percent steps)
+
+     Used in generating extra Pstate tables beyond those that would result from
+     #V data.
+
+     Producer:  DEF file as this is CCIN based
+
+     Consumers: p8_build_gpstate_table.C, p8_cpm_cal_load.C
+
+     Platform default:  0
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_CPM_TURBO_BOOST_PERCENT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PROC_R_LOADLINE_VDD</id>
+    <description>
+      Impedance (binary microOhms) of the load line from a processor VDD VRM to the
+      Processor Module pins.  This value is applied to each processor instance.
+
+      Consumers: p8_build_gpstate_table.C
+
+      Provided by the Machine Readable Workbook (via the power subsystem design
+      per system)
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_R_LOADLINE_VDD</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PROC_R_LOADLINE_VCS</id>
+    <description>
+      Impedance (binary microOhms) of the load line from a processor VCS VRM to the
+      Processor Module pins.  This value is applied to each processor instance.
+
+      Producer:  Machine Readable Workbook (via the power subsystem design per system)
+
+      Consumer: p8_build_gpstate_table.C
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_R_LOADLINE_VCS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PROC_R_DISTLOSS_VDD</id>
+    <description>
+      Impedance (binary in microOhms) of the VDD distribution loss sense point
+      to the circuit. This value is applied to each processor instance.
+
+      Producer:  Machine Readable Workbook (via the power subsystem design per system)
+
+      Consumer: p8_build_gpstate_table.C
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_R_DISTLOSS_VDD</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PROC_R_DISTLOSS_VCS</id>
+    <description>
+      Impedance (binary in microOhms) of the VCS distribution loss sense point
+      to the circuit. This value is applied to each processor instance.
+
+      Producer:  Machine Readable Workbook (via the power subsystem design per system)
+
+      Consumer: p8_build_gpstate_table.C
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_R_DISTLOSS_VCS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>FREQ_EXT_BIAS_UP</id>
+    <description>
+     Frequency Bias - % of bias upward (binary in 0.5 percent steps) in generating
+     Pstate tables.  Either this or FREQ_EXT_BIAS_DOWN can have non-zero value
+     concurrently due to the unsigned definition of attributes.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumers: p8_build_gpstate_table.C
+
+     Platform default:  0
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_FREQ_EXT_BIAS_UP</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>FREQ_EXT_BIAS_DOWN</id>
+    <description>
+     Frequency Bias - % of bias downward (binary in 0.5 percent steps) in generating
+     Pstate tables.  Either this or FREQ_EXT_BIAS_UP can have non-zero value
+     concurrently due to the unsigned definition of attributes.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumers: p8_build_gpstate_table.C
+
+     Platform default:  0
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_FREQ_EXT_BIAS_DOWN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>VOLTAGE_EXT_VDD_BIAS_UP</id>
+    <description>
+     External VDD Voltage Bias - % of bias upward (binary in 0.5 percent steps) that
+     is applied to each VPD point in generating the Global Pstate tables. Either 
+     this or ATTR_VOLTAGE_EXT_VDD_BIAS_DOWN can have non-zero value concurrently due to
+     the unsigned definition of attributes.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumers: p8_build_gpstate_table.C
+
+     Platform default:  0
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_VOLTAGE_EXT_VDD_BIAS_UP</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>VOLTAGE_EXT_VDD_BIAS_DOWN</id>
+    <description>
+     External VDD Voltage Bias - % of bias downward (binary in 0.5 percent steps) that
+     is applied to each VPD point in generating the Global Pstate tables. Either 
+     this or ATTR_VOLTAGE_EXT_VDD_BIAS_UP can have non-zero value concurrently due to
+     the unsigned definition of attributes.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumers: p8_build_gpstate_table.C
+
+     Platform default:  0
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_VOLTAGE_EXT_VDD_BIAS_DOWN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>VOLTAGE_EXT_VCS_BIAS_UP</id>
+    <description>
+     External VCS Voltage Bias - % of bias upward (binary in 0.5 percent steps) that
+     is applied to each VPD point in generating the Global Pstate tables. Either 
+     this or ATTR_VOLTAGE_EXT_VCS_BIAS_DOWN can have non-zero value concurrently due to
+     the unsigned definition of attributes.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumers: p8_build_gpstate_table.C
+
+     Platform default:  0
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_VOLTAGE_EXT_VCS_BIAS_UP</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>VOLTAGE_EXT_VCS_BIAS_DOWN</id>
+    <description>
+     External VCS Voltage Bias - % of bias downward (binary in 0.5 percent steps) that
+     is applied to each VPD point in generating the Global Pstate tables. Either 
+     this or ATTR_VOLTAGE_EXT_VCS_BIAS_UP can have non-zero value concurrently due to
+     the unsigned definition of attributes.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumers: p8_build_gpstate_table.C
+
+     Platform default:  0
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_VOLTAGE_EXT_VCS_BIAS_DOWN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>VOLTAGE_INT_VDD_BIAS_UP</id>
+    <description>
+     Internal VDD Voltage Bias - % of bias upward (binary in 0.5 percent steps) that
+     is applied to the Local Pstate Table voltage entries based on the Global Pstate Table 
+     built *after* the ATTR_VOLTAGE_EXT_VDD_BIAS_UP/ATTR_VOLTAGE_EXT_VDD_BIAS_DOWN bias 
+     have been applied. Either this or ATTR_VOLTAGE_INT_VDD_BIAS_DOWN can have non-zero value 
+     concurrently due to the unsigned definition of attributes.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumers: p8_build_gpstate_table.C
+
+     Platform default:  0
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_VOLTAGE_INT_VDD_BIAS_UP</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>VOLTAGE_INT_VDD_BIAS_DOWN</id>
+    <description>
+     Internal VDD Voltage Bias - % of bias downward (binary in 0.5 percent steps) that
+     is applied to the Local Pstate Table voltage entries based on the Global Pstate Table 
+     built *after* the ATTR_VOLTAGE_EXT_VDD_BIAS_UP/ATTR_VOLTAGE_EXT_VDD_BIAS_DOWN bias 
+     have been applied. Either this or ATTR_VOLTAGE_INT_VDD_BIAS_UP can have non-zero value 
+     concurrently due to the unsigned definition of attributes.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumers: p8_build_gpstate_table.C
+
+     Platform default:  0
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_VOLTAGE_INT_VDD_BIAS_DOWN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>VOLTAGE_INT_VCS_BIAS_UP</id>
+    <description>
+     Internal VCS Voltage Bias - % of bias upward (binary in 0.5 percent steps) that
+     is applied to the Local Pstate Table voltage entries based on the Global Pstate Table 
+     built *after* the ATTR_VOLTAGE_EXT_VCS_BIAS_UP/ATTR_VOLTAGE_EXT_VCS_BIAS_DOWN bias 
+     have been applied. Either this or ATTR_VOLTAGE_INT_VCS_BIAS_DOWN can have non-zero value 
+     concurrently due to the unsigned definition of attributes.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumers: p8_build_gpstate_table.C
+
+     Platform default:  0
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_VOLTAGE_INT_VCS_BIAS_UP</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>VOLTAGE_INT_VCS_BIAS_DOWN</id>
+    <description>
+     Internal VCS Voltage Bias - % of bias downward (binary in 0.5 percent steps) that
+     is applied to the Local Pstate Table voltage entries based on the Global Pstate Table 
+     built *after* the ATTR_VOLTAGE_EXT_VCS_BIAS_UP/ATTR_VOLTAGE_EXT_VCS_BIAS_DOWN bias 
+     have been applied. Either this or ATTR_VOLTAGE_INT_VCS_BIAS_UP can have non-zero value 
+     concurrently due to the unsigned definition of attributes.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumers: p8_build_gpstate_table.C
+
+     Platform default:  0
+    </description>
+    <simpleType>	
+        <uint32_t></uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_VOLTAGE_INT_VCS_BIAS_DOWN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PM_UNDERVOLTING_FRQ_MINIMUM</id>
+    <description>
+      Override for Minimum frequency for which undervolting is allowed.
+      
+      If value = 0, the value of VPD CPMin data point is passed to OCC FW via 
+      Pstate SuperStructure.
+      
+      If value != 0, this value will be passed to OCC FW via Pstate SuperStructure
+      as the floor frequency for enabled CPMs.
+      
+      Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value.
+
+      Consumer: OCC FW; OCC Lab Tools
+
+      Provided by the Machine Readable Workbook.
+    </description>
+    <simpleType>	
+        <uint8_t></uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PM_UNDERVOLTING_FRQ_MINIMUM</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PM_UNDERVOLTING_FREQ_MAXIMUM</id>
+    <description>
+      Override for Maximum frequency for which undervolting is allowed.
+      
+      If value = 0, the value of VPD Turbo data point is passed to OCC FW via 
+      Pstate SuperStructure.
+      
+      If value != 0, this value will be passed to OCC FW via Pstate SuperStructure
+      as the ceiling frequency for enabled CPMs.
+      
+      Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value.
+
+      Consumer: OCC FW; OCC Lab Tools
+
+      Provided by the Machine Readable Workbook.
+    </description>
+    <simpleType>	
+        <uint8_t></uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PM_UNDERVOLTING_FREQ_MAXIMUM</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PM_WINKLE_ENTRY</id>
+    <description>Setting depends on di/dt charateristics of the system.
+
+        Set Assisted if power off serialization is needed and WINKLE_TYPE=Fast;  
+        Set to Hardware if the system can handle the unrelated powering off between cores.  
+        Hardware setting decreases entry latency
+
+        Producer: MRWB
+
+        Consumer:  p8_poreslw_init.C
+    </description>
+    <simpleType>	
+        <uint8_t></uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PM_WINKLE_ENTRY</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PM_WINKLE_EXIT</id>
+    <description>Setting depends on di/dt charateristics of the system and the setting of ATTR_PM_WINKLE_TYPE.
+
+        Set to Assisted if power on serialization is needed and WINKLE_TYPE=Fast;  Set to Hardware if the system 
+        can handle the unrelated powering off between cores.  Hardware setting decreases entry latency.
+        Must be set to Assisted if ATTR_PM_WINKLE_TYPE=Deep as this necessary for restore.
+
+        Setting to Hardware is a test mode for Fast only.
+
+        Producer: MRWB
+
+        Consumer:  p8_poreslw_init.C
+    </description>
+    <simpleType>	
+        <uint8_t></uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PM_WINKLE_EXIT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
 </attributes>
diff --git a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
index 146f1eec0..436c99e9f 100644
--- a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
@@ -171,15 +171,6 @@
         <default>4</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PROC_R_LOADLINE</id>
-        <default>890</default>
-    </attribute>
-    <attribute><id>PROC_R_DISTLOSS</id>
-        <default>100</default>
-    </attribute>
-    <attribute><id>PROC_VRM_VOFFSET</id>
-        <default>1000</default>
-    </attribute>
     <attribute><id>FREQ_CORE_MAX</id>
         <default>4000</default>
     </attribute>
@@ -336,12 +327,6 @@
         <default>1</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SPIVID_PORT_ENABLE</id>
         <default>0x4</default><!-- PORT0NONRED -->
     </attribute>
@@ -1070,12 +1055,6 @@
         <default>1</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SPIVID_PORT_ENABLE</id>
         <default>0x0</default><!-- NONE -->
     </attribute>
@@ -1809,12 +1788,6 @@
         <default>1</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SLEEP_ENTRY</id></attribute>
     <attribute><id>PM_SLEEP_EXIT</id></attribute>
     <attribute><id>PM_SLEEP_TYPE</id></attribute>
@@ -2545,12 +2518,6 @@
         <default>1</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SPIVID_PORT_ENABLE</id>
         <default>0x0</default><!-- NONE -->
     </attribute>
diff --git a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
index c3e8dffa3..c5c822068 100644
--- a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
@@ -143,15 +143,6 @@
         <default>1</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PROC_R_LOADLINE</id>
-        <default>890</default>
-    </attribute>
-    <attribute><id>PROC_R_DISTLOSS</id>
-        <default>100</default>
-    </attribute>
-    <attribute><id>PROC_VRM_VOFFSET</id>
-        <default>1000</default>
-    </attribute>
     <attribute><id>FREQ_CORE_MAX</id>
         <default>4000</default>
     </attribute>
@@ -309,12 +300,6 @@
         <default>0</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SPIVID_PORT_ENABLE</id>
         <default>0x7</default><!-- REDUNDANT -->
     </attribute>
@@ -1409,12 +1394,6 @@
         <default>0</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SPIVID_PORT_ENABLE</id>
         <default>0x7</default><!-- REDUNDANT -->
     </attribute>
@@ -2509,12 +2488,6 @@
         <default>0</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SPIVID_PORT_ENABLE</id>
         <default>0x7</default><!-- REDUNDANT -->
     </attribute>
@@ -3608,12 +3581,6 @@
         <default>0</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SPIVID_PORT_ENABLE</id>
         <default>0x7</default><!-- REDUNDANT -->
     </attribute>
@@ -4706,12 +4673,6 @@
         <default>0</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SPIVID_PORT_ENABLE</id>
         <default>0x7</default><!-- REDUNDANT -->
     </attribute>
@@ -5773,12 +5734,6 @@
         <default>0</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SPIVID_PORT_ENABLE</id>
         <default>0x7</default><!-- REDUNDANT -->
     </attribute>
@@ -6838,12 +6793,6 @@
         <default>0</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SPIVID_PORT_ENABLE</id>
         <default>0x7</default><!-- REDUNDANT -->
     </attribute>
@@ -7904,12 +7853,6 @@
         <default>0</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SPIVID_PORT_ENABLE</id>
         <default>0x7</default><!-- REDUNDANT -->
     </attribute>
@@ -15897,12 +15840,6 @@
         <default>0</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SPIVID_PORT_ENABLE</id>
         <default>0x7</default><!-- REDUNDANT -->
     </attribute>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index bb7f42153..977b3927f 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -130,9 +130,15 @@
     <attribute><id>PM_SAFE_FREQUENCY</id></attribute>
     <attribute><id>PM_SPIPSS_FREQUENCY</id></attribute>
     <attribute><id>PM_SPIVID_FREQUENCY</id></attribute>
-    <attribute><id>PROC_R_DISTLOSS</id></attribute>
-    <attribute><id>PROC_R_LOADLINE</id></attribute>
-    <attribute><id>PROC_VRM_VOFFSET</id></attribute>
+
+    <attribute><id>CPM_TURBO_BOOST_PERCENT</id></attribute>
+    <attribute><id>PROC_R_LOADLINE_VDD</id></attribute>
+    <attribute><id>PROC_R_LOADLINE_VCS</id></attribute>
+    <attribute><id>PROC_R_DISTLOSS_VDD</id></attribute>
+    <attribute><id>PROC_R_DISTLOSS_VCS</id></attribute>
+    <attribute><id>PROC_VRM_VOFFSET_VDD</id></attribute>
+    <attribute><id>PROC_VRM_VOFFSET_VCS</id></attribute>
+
     <!-- End pm_plat_attributes.xml -->
     <!--    sbe_config_update attributes    -->
     <attribute><id>NEST_FREQ_MHZ</id></attribute>
@@ -305,8 +311,6 @@
      <attribute><id>PM_PBAX_BRDCST_ID_VECTOR</id></attribute>
      <attribute><id>PM_PBAX_CHIPID</id></attribute>
      <attribute><id>PM_PBAX_NODEID</id></attribute>
-     <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id></attribute>
-     <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id></attribute>
      <attribute><id>PM_SPIVID_PORT_ENABLE</id></attribute>
      <!-- End pm_plat_attributes.xml -->
      <!-- Start pm_hwp_attributes.xml -->
@@ -399,6 +403,21 @@
     <attribute><id>PROC_MEM_BASES_ACK</id></attribute>
     <attribute><id>PROC_MEM_SIZES_ACK</id></attribute>
 
+    <attribute><id>FREQ_EXT_BIAS_UP</id></attribute>
+    <attribute><id>FREQ_EXT_BIAS_DOWN</id></attribute>
+    <attribute><id>VOLTAGE_EXT_VDD_BIAS_UP</id></attribute>
+    <attribute><id>VOLTAGE_EXT_VDD_BIAS_DOWN</id></attribute>
+    <attribute><id>VOLTAGE_EXT_VCS_BIAS_UP</id></attribute>
+    <attribute><id>VOLTAGE_EXT_VCS_BIAS_DOWN</id></attribute>
+    <attribute><id>VOLTAGE_INT_VDD_BIAS_UP</id></attribute>
+    <attribute><id>VOLTAGE_INT_VDD_BIAS_DOWN</id></attribute>
+    <attribute><id>VOLTAGE_INT_VCS_BIAS_UP</id></attribute>
+    <attribute><id>VOLTAGE_INT_VCS_BIAS_DOWN</id></attribute>
+    <attribute><id>PM_UNDERVOLTING_FRQ_MINIMUM</id></attribute>
+    <attribute><id>PM_UNDERVOLTING_FREQ_MAXIMUM</id></attribute>
+    <attribute><id>CPM_INFLECTION_POINTS</id></attribute>
+    <attribute><id>PM_WINKLE_ENTRY</id></attribute>
+    <attribute><id>PM_WINKLE_EXIT</id></attribute>
 
 </targetType>
 
diff --git a/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml b/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml
index fc67f7ed7..b836f02ca 100644
--- a/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml
+++ b/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml
@@ -159,15 +159,6 @@
         <default>1</default>
     </attribute>
      <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PROC_R_LOADLINE</id>
-        <default>890</default>
-    </attribute>
-    <attribute><id>PROC_R_DISTLOSS</id>
-        <default>100</default>
-    </attribute>
-    <attribute><id>PROC_VRM_VOFFSET</id>
-        <default>1000</default>
-    </attribute>
     <attribute><id>FREQ_CORE_MAX</id>
         <default>4000</default>
     </attribute>
diff --git a/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml b/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml
index 3c9fe4dfd..90f549c3c 100644
--- a/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml
+++ b/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml
@@ -156,15 +156,6 @@
         <default>0</default>
     </attribute>
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PROC_R_LOADLINE</id>
-        <default>890</default>
-    </attribute>
-    <attribute><id>PROC_R_DISTLOSS</id>
-        <default>100</default>
-    </attribute>
-    <attribute><id>PROC_VRM_VOFFSET</id>
-        <default>1000</default>
-    </attribute>
     <attribute><id>FREQ_CORE_MAX</id>
         <default>4000</default>
     </attribute>
@@ -329,12 +320,6 @@
     </attribute>
 
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SPIVID_PORT_ENABLE</id>
         <default>0b111</default><!-- REDUNDANT -->
     </attribute>
@@ -1400,12 +1385,6 @@
     </attribute>
 
     <!-- Start pm_plat_attributes.xml -->
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MINIMUM</id>
-        <default>900</default>
-    </attribute>
-    <attribute><id>PM_PSTATE_UNDERVOLTING_MAXIMUM</id>
-        <default>1250</default>
-    </attribute>
     <attribute><id>PM_SPIVID_PORT_ENABLE</id>
         <default>0b111</default><!-- REDUNDANT -->
     </attribute>