Added PORE target support

Change-Id: If36fbeaf629375b7158b29d44fc0ead5b3d33304
RTC: 89232
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7255
Tested-by: Jenkins Server
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: SHELDON R. BAILEY <baileysh@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

6 files changed, 337 insertions, 11 deletions

diff --git a/src/usr/targeting/common/entitypath.C b/src/usr/targeting/common/entitypath.C
index d91cbc3a1..c64b63dd6 100644
--- a/src/usr/targeting/common/entitypath.C
+++ b/src/usr/targeting/common/entitypath.C
@@ -352,6 +352,8 @@ const char* EntityPath::pathElementTypeAsString(
             return "Control Node";
         case TYPE_NX:
             return "NX";
+        case TYPE_PORE:
+            return "PORE";
         case TYPE_OSCREFCLK:
             return "OSCREFClock";
         case TYPE_OSCPCICLK:
diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl
index 91dbdcac4..fa678ba01 100755
--- a/src/usr/targeting/common/genHwsvMrwXml.pl
+++ b/src/usr/targeting/common/genHwsvMrwXml.pl
@@ -532,14 +532,14 @@ foreach my $pcie_bus (@{$pcie_buses->{'pcie-bus'}})
         if((exists($pcie_bus->{source}->{'dsmp-capable'}))&&
           ($pcie_bus->{source}->{'dsmp-capable'} eq 'Yes'))
         {
-    
+
             $dsmp_capable = 1;
         }
-    
+
         if((exists($pcie_bus->{endpoint}->{'is-slot'}))&&
           ($pcie_bus->{endpoint}->{'is-slot'} eq 'Yes'))
         {
-    
+
             $is_slot = 1;
         }
         my $lane_set = 0;
@@ -554,19 +554,19 @@ foreach my $pcie_bus (@{$pcie_buses->{'pcie-bus'}})
             {
                 $lane_set = 1;
             }
-    
+
         }
         $pcie_list{$pcie_bus->{source}->{'instance-path'}}->
-            {$pcie_bus->{source}->{iop}}->{$lane_set}->{'lane-mask'} 
+            {$pcie_bus->{source}->{iop}}->{$lane_set}->{'lane-mask'}
                 = $pcie_bus->{source}->{'lane-mask'};
         $pcie_list{$pcie_bus->{source}->{'instance-path'}}->
-            {$pcie_bus->{source}->{iop}}->{$lane_set}->{'dsmp-capable'} 
+            {$pcie_bus->{source}->{iop}}->{$lane_set}->{'dsmp-capable'}
                 = $dsmp_capable;
         $pcie_list{$pcie_bus->{source}->{'instance-path'}}->
-            {$pcie_bus->{source}->{iop}}->{$lane_set}->{'lane-swap'} 
+            {$pcie_bus->{source}->{iop}}->{$lane_set}->{'lane-swap'}
                 = oct($pcie_bus->{source}->{'lane-swap-bits'});
         $pcie_list{$pcie_bus->{source}->{'instance-path'}}->
-            {$pcie_bus->{source}->{iop}}->{$lane_set}->{'lane-reversal'} 
+            {$pcie_bus->{source}->{iop}}->{$lane_set}->{'lane-reversal'}
                 = oct($pcie_bus->{source}->{'lane-reversal-bits'});
         $pcie_list{$pcie_bus->{source}->{'instance-path'}}->
             {$pcie_bus->{source}->{iop}}->{$lane_set}->{'is-slot'} = $is_slot;
@@ -1152,6 +1152,10 @@ for (my $do_core = 0, my $i = 0; $i <= $#STargets; $i++)
             # instance path to be added
             $ipath = "";
             generate_nx($proc,$proc_ordinal_id,$ipath);
+            # TODO RTC: 87142
+            # instance path to be added
+            $ipath = "";
+            generate_pore($proc,$proc_ordinal_id,$ipath);
         }
     }
 }
@@ -1218,7 +1222,7 @@ for my $i ( 0 .. $#STargets )
             print "\n";
         }
         my $mba = $STargets[$i][UNIT_FIELD];
-        generate_mba( $memb, $membMcs, $mba, 
+        generate_mba( $memb, $membMcs, $mba,
             $STargets[$i][ORDINAL_FIELD], $ipath);
         $mba_count += 1;
         if ($mba_count == 2)
@@ -2570,6 +2574,43 @@ sub generate_nx
 ";
 }
 
+sub generate_pore
+{
+    my ($proc, $ordinalId, $ipath) = @_;
+    my $uidstr = sprintf("0x%02X1F%04X",${node},$proc);
+    print "\n<!-- $SYSNAME n${node}p$proc PORE units -->\n";
+    print "
+<targetInstance>
+    <id>sys${sys}node${node}proc${proc}pore0</id>
+    <type>unit-pore-$CHIPNAME</type>
+    <attribute><id>HUID</id><default>${uidstr}</default></attribute>
+    <attribute>
+        <id>PHYS_PATH</id>
+        <default>physical:sys-$sys/node-$node/proc-$proc/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>AFFINITY_PATH</id>
+        <default>affinity:sys-$sys/node-$node/proc-$proc/pore-0</default>
+    </attribute>
+    <compileAttribute>
+        <id>INSTANCE_PATH</id>";
+        # TODO RTC: 87142
+        print "
+        <default>instance:pore:TO_BE_ADDED</default>
+    </compileAttribute>
+    <attribute>
+        <id>CHIP_UNIT</id>
+        <default>0</default>
+    </attribute>";
+
+    # call to do any fsp per-pore attributes
+    do_plugin('fsp_pore', $proc, $ordinalId );
+
+    print "
+</targetInstance>
+";
+}
+
 my $logicalDimmInit = 0;
 my %logicalDimmList = ();
 sub generate_logicalDimms
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 52fb18ce8..1bf36be3f 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -198,14 +198,18 @@
         <name>NX</name>
         <value>30</value>
     </enumerator>
+    <enumerator>
+        <name>PORE</name>
+        <value>31</value>
+    </enumerator>
     <!-- add any new types here, and increment TEST_FAIL and LAST_IN_RANGE -->
     <enumerator>
         <name>TEST_FAIL</name>
-        <value>31</value>
+        <value>32</value>
     </enumerator>
     <enumerator>
         <name>LAST_IN_RANGE</name>
-        <value>32</value>
+        <value>33</value>
     </enumerator>
     <default>NA</default>
 </enumerationType>
diff --git a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
index 378ea6ad4..1e6a4fce4 100644
--- a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
@@ -1075,6 +1075,26 @@
     </attribute>
 </targetInstance>
 
+<!-- murano n0p0 PORE unit -->
+
+<targetInstance>
+    <id>sys0node0proc0pore0</id>
+    <type>unit-pore-murano</type>
+    <attribute><id>HUID</id><default>0x001F0000</default></attribute>
+    <attribute>
+        <id>PHYS_PATH</id>
+        <default>physical:sys-0/node-0/proc-0/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>AFFINITY_PATH</id>
+        <default>physical:sys-0/node-0/proc-0/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>CHIP_UNIT</id>
+        <default>0</default>
+    </attribute>
+</targetInstance>
+
 <!-- Murano n0p1 processor chip -->
 
 <targetInstance>
@@ -1871,6 +1891,26 @@
     </attribute>
 </targetInstance>
 
+<!-- murano n0p1 PORE unit -->
+
+<targetInstance>
+    <id>sys0node0proc1pore0</id>
+    <type>unit-pore-murano</type>
+    <attribute><id>HUID</id><default>0x001F0001</default></attribute>
+    <attribute>
+        <id>PHYS_PATH</id>
+        <default>physical:sys-0/node-0/proc-1/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>AFFINITY_PATH</id>
+        <default>physical:sys-0/node-0/proc-1/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>CHIP_UNIT</id>
+        <default>0</default>
+    </attribute>
+</targetInstance>
+
 <!-- Murano n0p2 processor chip -->
 
 <targetInstance>
@@ -2669,6 +2709,26 @@
     </attribute>
 </targetInstance>
 
+<!-- murano n0p2 PORE unit -->
+
+<targetInstance>
+    <id>sys0node0proc2pore0</id>
+    <type>unit-pore-murano</type>
+    <attribute><id>HUID</id><default>0x001F0002</default></attribute>
+    <attribute>
+        <id>PHYS_PATH</id>
+        <default>physical:sys-0/node-0/proc-2/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>AFFINITY_PATH</id>
+        <default>physical:sys-0/node-0/proc-2/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>CHIP_UNIT</id>
+        <default>0</default>
+    </attribute>
+</targetInstance>
+
 <!-- Murano n0p3 processor chip -->
 
 <targetInstance>
@@ -3465,6 +3525,26 @@
     </attribute>
 </targetInstance>
 
+<!-- murano n0p3 PORE unit -->
+
+<targetInstance>
+    <id>sys0node0proc3pore0</id>
+    <type>unit-pore-murano</type>
+    <attribute><id>HUID</id><default>0x001F0003</default></attribute>
+    <attribute>
+        <id>PHYS_PATH</id>
+        <default>physical:sys-0/node-0/proc-3/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>AFFINITY_PATH</id>
+        <default>physical:sys-0/node-0/proc-3/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>CHIP_UNIT</id>
+        <default>0</default>
+    </attribute>
+</targetInstance>
+
 <!-- Centaur n0p4 : start -->
 
 <targetInstance>
diff --git a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
index 5348557df..288f1c80d 100644
--- a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
@@ -1438,6 +1438,26 @@
     </attribute>
 </targetInstance>
 
+<!-- venice n0p0 PORE unit -->
+
+<targetInstance>
+    <id>sys0node0proc0pore0</id>
+    <type>unit-pore-venice</type>
+    <attribute><id>HUID</id><default>0x001F0000</default></attribute>
+    <attribute>
+        <id>PHYS_PATH</id>
+        <default>physical:sys-0/node-0/proc-0/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>AFFINITY_PATH</id>
+        <default>physical:sys-0/node-0/proc-0/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>CHIP_UNIT</id>
+        <default>0</default>
+    </attribute>
+</targetInstance>
+
 <!-- Venice n0p1 processor chip -->
 
 <targetInstance>
@@ -2595,6 +2615,25 @@
     </attribute>
 </targetInstance>
 
+<!-- venice n0p1 PORE unit -->
+
+<targetInstance>
+    <id>sys0node0proc1pore0</id>
+    <type>unit-pore-venice</type>
+    <attribute><id>HUID</id><default>0x001F0001</default></attribute>
+    <attribute>
+        <id>PHYS_PATH</id>
+        <default>physical:sys-0/node-0/proc-1/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>AFFINITY_PATH</id>
+        <default>physical:sys-0/node-0/proc-1/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>CHIP_UNIT</id>
+        <default>0</default>
+    </attribute>
+</targetInstance>
 
 <!-- Venice n0p2 processor chip -->
 
@@ -3754,6 +3793,26 @@
     </attribute>
 </targetInstance>
 
+<!-- venice n0p2 PORE unit -->
+
+<targetInstance>
+    <id>sys0node0proc2pore0</id>
+    <type>unit-pore-venice</type>
+    <attribute><id>HUID</id><default>0x001F0002</default></attribute>
+    <attribute>
+        <id>PHYS_PATH</id>
+        <default>physical:sys-0/node-0/proc-2/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>AFFINITY_PATH</id>
+        <default>physical:sys-0/node-0/proc-2/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>CHIP_UNIT</id>
+        <default>0</default>
+    </attribute>
+</targetInstance>
+
 <!-- Venice n0p3 processor chip -->
 
 
@@ -4912,6 +4971,26 @@
     </attribute>
 </targetInstance>
 
+<!-- venice n0p3 PORE unit -->
+
+<targetInstance>
+    <id>sys0node0proc3pore0</id>
+    <type>unit-pore-venice</type>
+    <attribute><id>HUID</id><default>0x001F0003</default></attribute>
+    <attribute>
+        <id>PHYS_PATH</id>
+        <default>physical:sys-0/node-0/proc-3/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>AFFINITY_PATH</id>
+        <default>physical:sys-0/node-0/proc-3/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>CHIP_UNIT</id>
+        <default>0</default>
+    </attribute>
+</targetInstance>
+
 <!-- Venice n0p4 processor chip -->
 
 <targetInstance>
@@ -6038,6 +6117,26 @@
     </attribute>
 </targetInstance>
 
+<!-- venice n0p4 PORE unit -->
+
+<targetInstance>
+    <id>sys0node0proc4pore0</id>
+    <type>unit-pore-venice</type>
+    <attribute><id>HUID</id><default>0x001F0004</default></attribute>
+    <attribute>
+        <id>PHYS_PATH</id>
+        <default>physical:sys-0/node-0/proc-4/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>AFFINITY_PATH</id>
+        <default>physical:sys-0/node-0/proc-4/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>CHIP_UNIT</id>
+        <default>0</default>
+    </attribute>
+</targetInstance>
+
 <!-- Venice n0p5 processor chip -->
 
 <targetInstance>
@@ -7162,6 +7261,26 @@
     </attribute>
 </targetInstance>
 
+<!-- venice n0p5 PORE unit -->
+
+<targetInstance>
+    <id>sys0node0proc5pore0</id>
+    <type>unit-pore-venice</type>
+    <attribute><id>HUID</id><default>0x001F0005</default></attribute>
+    <attribute>
+        <id>PHYS_PATH</id>
+        <default>physical:sys-0/node-0/proc-5/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>AFFINITY_PATH</id>
+        <default>physical:sys-0/node-0/proc-5/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>CHIP_UNIT</id>
+        <default>0</default>
+    </attribute>
+</targetInstance>
+
 <!-- Venice n0p6 processor chip -->
 
 <targetInstance>
@@ -8286,6 +8405,26 @@
     </attribute>
 </targetInstance>
 
+<!-- venice n0p6 PORE unit -->
+
+<targetInstance>
+    <id>sys0node0proc6pore0</id>
+    <type>unit-pore-venice</type>
+    <attribute><id>HUID</id><default>0x001F0006</default></attribute>
+    <attribute>
+        <id>PHYS_PATH</id>
+        <default>physical:sys-0/node-0/proc-6/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>AFFINITY_PATH</id>
+        <default>physical:sys-0/node-0/proc-6/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>CHIP_UNIT</id>
+        <default>0</default>
+    </attribute>
+</targetInstance>
+
 <!-- Venice n0p7 processor chip -->
 
 <targetInstance>
@@ -9409,6 +9548,26 @@
     </attribute>
 </targetInstance>
 
+<!-- venice n0p7 PORE unit -->
+
+<targetInstance>
+    <id>sys0node0proc7pore0</id>
+    <type>unit-pore-venice</type>
+    <attribute><id>HUID</id><default>0x001F0007</default></attribute>
+    <attribute>
+        <id>PHYS_PATH</id>
+        <default>physical:sys-0/node-0/proc-7/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>AFFINITY_PATH</id>
+        <default>physical:sys-0/node-0/proc-7/pore-0</default>
+    </attribute>
+    <attribute>
+        <id>CHIP_UNIT</id>
+        <default>0</default>
+    </attribute>
+</targetInstance>
+
 <!-- Centaur n0p0 : start -->
 
 <targetInstance>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 37496f949..6e80d5b0c 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -1312,4 +1312,44 @@
     </attribute>
 </targetType>
 
+<targetType>
+    <id>unit-pore-power8</id>
+    <parent>unit</parent>
+    <attribute>
+        <id>TYPE</id>
+        <default>PORE</default>
+    </attribute>
+    <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute>
+    <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id>
+        <default>0x00000001</default> <!--GARD -->
+    </attribute>
+    <attribute>
+        <id>PRIMARY_CAPABILITIES</id>
+        <default>
+            <field><id>supportsFsiScom</id><value>0</value></field>
+            <field><id>supportsXscom</id><value>0</value></field>
+            <field><id>supportsInbandScom</id><value>0</value></field>
+            <field><id>reserved</id><value>0</value></field>
+        </default>
+    </attribute>
+</targetType>
+
+<targetType>
+    <id>unit-pore-venice</id>
+    <parent>unit-pore-power8</parent>
+    <attribute>
+        <id>MODEL</id>
+        <default>VENICE</default>
+    </attribute>
+</targetType>
+
+<targetType>
+    <id>unit-pore-murano</id>
+    <parent>unit-pore-power8</parent>
+    <attribute>
+        <id>MODEL</id>
+        <default>MURANO</default>
+    </attribute>
+</targetType>
+
 </attributes>